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aiengine
Xilinx SDK Drivers API Documentation
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This typedef contains the attributes for Stream Switch Event Port Selection register. More...
Data Fields | |
u32 | RegAddr |
Register Address. More... | |
XAieGbl_RegFldAttr | PortIndex [8U] |
Port index. More... | |
XAieGbl_RegFldAttr | PortMode [8U] |
Port type. More... | |
This typedef contains the attributes for Stream Switch Event Port Selection register.
XAieGbl_RegFldAttr XAieGbl_RegStrmSwEventPortSelect::PortIndex[8U] |
Port index.
Referenced by XAieTile_CoreStrmSwEventPortSelectSet(), and XAieTile_PlStrmSwEventPortSelectSet().
XAieGbl_RegFldAttr XAieGbl_RegStrmSwEventPortSelect::PortMode[8U] |
Port type.
Referenced by XAieTile_CoreStrmSwEventPortSelectSet(), and XAieTile_PlStrmSwEventPortSelectSet().
u32 XAieGbl_RegStrmSwEventPortSelect::RegAddr |
Register Address.
Referenced by XAieTile_CoreStrmSwEventPortSelectGet(), XAieTile_CoreStrmSwEventPortSelectGet32(), XAieTile_CoreStrmSwEventPortSelectSet(), XAieTile_CoreStrmSwEventPortSelectSet32(), XAieTile_PlStrmSwEventPortSelectGet(), XAieTile_PlStrmSwEventPortSelectGet32(), XAieTile_PlStrmSwEventPortSelectSet(), and XAieTile_PlStrmSwEventPortSelectSet32().