xdmapcie
Xilinx SDK Drivers API Documentation
xdmapcie_hw.h File Reference

Overview

This header file contains identifiers and basic driver functions for the XDmaPcie device driver.

Note
None.
MODIFICATION HISTORY:
Ver   Who  Date     Changes


1.0 tk 01/30/2019 First release

Macros

#define XDmaPcie_ReadReg(BaseAddress, RegOffset)   Xil_In32((BaseAddress) + (RegOffset))
 Macro to read register. More...
 
#define XDmaPcie_WriteReg(BaseAddress, RegOffset, Data)   Xil_Out32((BaseAddress) + (RegOffset), (Data))
 Macro to write register. More...
 
Registers

Register offsets for this device.

Some of the registers are configurable at hardware build time such that may or may not exist in the hardware.

#define XDMAPCIE_PCIE_CORE_OFFSET   0x000
 PCI Express hard core configuration register offset. More...
 
#define XDMAPCIE_VSECC_OFFSET   0x128
 VSEC Capability Register. More...
 
#define XDMAPCIE_VSECH_OFFSET   0x12C
 VSEC Header Register. More...
 
#define XDMAPCIE_BI_OFFSET   0x130
 Bridge Info Register. More...
 
#define XDMAPCIE_BSC_OFFSET   0x134
 Bridge Status and Control Register. More...
 
#define XDMAPCIE_ID_OFFSET   0x138
 Interrupt Decode Register. More...
 
#define XDMAPCIE_IM_OFFSET   0x13C
 Interrupt Mask Register. More...
 
#define XDMAPCIE_BL_OFFSET   0x140
 Bus Location Register. More...
 
#define XDMAPCIE_PHYSC_OFFSET   0x144
 Physical status and Control Register. More...
 
#define XDMAPCIE_RPSC_OFFSET   0x148
 Root Port Status & Control Register. More...
 
#define XDMAPCIE_RPMSIB_UPPER_OFFSET   0x14C
 Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written. More...
 
#define XDMAPCIE_RPMSIB_LOWER_OFFSET   0x150
 Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written. More...
 
#define XDMAPCIE_RPEFR_OFFSET   0x154
 Root Port Error FIFO Read Register. More...
 
#define XDMAPCIE_RPIFR1_OFFSET   0x158
 Root Port Interrupt FIFO Read1 Register. More...
 
#define XDMAPCIE_RPIFR2_OFFSET   0x15C
 Root Port Interrupt FIFO Read2 Register. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET   0x208
 AXIBAR 2 PCIBAR translation 0 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET   0x20C
 AXIBAR to PCIBAR translation 0 lower 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_1U_OFFSET   0x210
 AXIBAR to PCIBAR translation 1 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_1L_OFFSET   0x214
 AXIBAR to PCIBAR translation 1 lower 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_2U_OFFSET   0x218
 AXIBAR to PCIBAR translation 2 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_2L_OFFSET   0x21C
 AXIBAR to PCIBAR translation 2 lower 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_3U_OFFSET   0x220
 AXIBAR to PCIBAR translation 3 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_3L_OFFSET   0x224
 AXIBAR to PCIBAR translation 3 lower 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_4U_OFFSET   0x228
 AXIBAR to PCIBAR translation 4 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_4L_OFFSET   0x22C
 AXIBAR to PCIBAR translation 4 lower 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_5U_OFFSET   0x230
 AXIBAR to PCIBAR translation 5 upper 32 bits. More...
 
#define XDMAPCIE_AXIBAR2PCIBAR_5L_OFFSET   0x234
 AXIBAR to PCIBAR translation 5 lower 32 bits. More...
 
VSECC Register bitmaps and masks
#define XDMAPCIE_VSECC_ID_MASK   0x0000FFFF
 Vsec capability Id. More...
 
#define XDMAPCIE_VSECC_VER_MASK   0x000F0000
 Version of capability Structure. More...
 
#define XDMAPCIE_VSECC_NEXT_MASK   0xFFF00000
 Offset to next capability. More...
 
#define XDMAPCIE_VSECC_VER_SHIFT   16
 VSEC Version shift. More...
 
#define XDMAPCIE_VSECC_NEXT_SHIFT   20
 Next capability offset shift. More...
 
VSECH Register bitmaps and masks
#define XDMAPCIE_VSECH_ID_MASK   0x0000FFFF
 Vsec structure Id. More...
 
#define XDMAPCIE_VSECH_REV_MASK   0x000F0000
 Vsec header version. More...
 
#define XDMAPCIE_VSECH_LEN_MASK   0xFFF00000
 Length of Vsec capability structure. More...
 
#define XDMAPCIE_VSECH_REV_SHIFT   16
 Vsec version shift. More...
 
#define XDMAPCIE_VSECH_LEN_SHIFT   20
 Vsec length shift. More...
 
Bridge Info Register bitmaps and masks
#define XDMAPCIE_BI_GEN2_MASK   0x00000001
 PCIe Gen2 Speed Support Mask. More...
 
#define XDMAPCIE_BI_RP_MASK   0x00000002
 PCIe Root Port Support. More...
 
#define XDMAPCIE_UP_CONFIG_CAPABLE   0x00000004
 Up Config Capable. More...
 
#define XDMAPCIE_BI_ECAM_SIZE_MASK   0x00070000
 ECAM size. More...
 
#define XDMAPCIE_BI_RP_SHIFT   1
 PCIe Root Port Shift. More...
 
#define XDMAPCIE_BI_ECAM_SIZE_SHIFT   16
 PCIe ECAM Size Shift. More...
 
Bridge Status & Control Register bitmaps and masks
#define XDMAPCIE_BSC_ECAM_BUSY_MASK   0x00000001
 ECAM Busy Status. More...
 
#define XDMAPCIE_BSC_GI_MASK   0x00000100
 Global Interrupt Disable. More...
 
#define XDMAPCIE_BSC_RW1C_MASK   0x00010000
 RW Permissions to RW1C Registers. More...
 
#define XDMAPCIE_BSC_RO_MASK   0x00020000
 RW Permissions to RO Registers. More...
 
#define XDMAPCIE_BSC_GI_SHIFT   8
 Global Interrupt Disable Shift. More...
 
#define XDMAPCIE_BSC_RW1C_SHIFT   16
 RW1C Shift. More...
 
#define XDMAPCIE_BSC_RO_SHIFT   17
 RO as RW Shift. More...
 
Interrupt Decode Register bitmaps and masks
#define XDMAPCIE_ID_LINK_DOWN_MASK   0x00000001
 Link Down Mask. More...
 
#define XDMAPCIE_ID_ECRC_ERR_MASK   0x00000002
 Rx Packet CRC failed. More...
 
#define XDMAPCIE_ID_STR_ERR_MASK   0x00000004
 Streaming Error Mask. More...
 
#define XDMAPCIE_ID_HOT_RST_MASK   0x00000008
 Hot Reset Mask. More...
 
#define XDMAPCIE_ID_CFG_COMPL_STATE_MASK   0x000000E0
 Cfg Completion Status Mask. More...
 
#define XDMAPCIE_ID_CFG_TIMEOUT_MASK   0x00000100
 Cfg timeout Mask. More...
 
#define XDMAPCIE_ID_CORRECTABLE_ERR_MASK   0x00000200
 Correctable Error Mask. More...
 
#define XDMAPCIE_ID_NONFATAL_ERR_MASK   0x00000400
 Non-Fatal Error Mask. More...
 
#define XDMAPCIE_ID_FATAL_ERR_MASK   0x00000800
 Fatal Error Mask. More...
 
#define XDMAPCIE_ID_INTX_INTERRUPT   0x00010000
 INTX Interrupt. More...
 
#define XDMAPCIE_ID_MSI_INTERRUPT   0x00020000
 MSI Interrupt. More...
 
#define XDMAPCIE_ID_UNSUPP_CMPL_MASK   0x00100000
 Slave Unsupported Request Mask. More...
 
#define XDMAPCIE_ID_UNEXP_CMPL_MASK   0x00200000
 Slave Unexpected Completion Mask. More...
 
#define XDMAPCIE_ID_CMPL_TIMEOUT_MASK   0x00400000
 Slave completion Time Mask. More...
 
#define XDMAPCIE_ID_SLV_EP_MASK   0x00800000
 Slave Error Poison Mask. More...
 
#define XDMAPCIE_ID_CMPL_ABT_MASK   0x01000000
 Slave completion Abort Mask. More...
 
#define XDMAPCIE_ID_ILL_BURST_MASK   0x02000000
 Slave Illegal Burst Mask. More...
 
#define XDMAPCIE_ID_DECODE_ERR_MASK   0x04000000
 Master Decode Error Interrupt Mask. More...
 
#define XDMAPCIE_ID_SLAVE_ERR_MASK   0x08000000
 Master Slave Error Interrupt Mask. More...
 
#define XDMAPCIE_ID_MASTER_EP_MASK   0x10000000
 Master Error Poison Mask. More...
 
#define XDMAPCIE_ID_CLEAR_ALL_MASK   0xFFFFFFFF
 Mask of all Interrupts. More...
 
Interrupt Mask Register bitmaps and masks
#define XDMAPCIE_IM_ENABLE_ALL_MASK   0xFFFFFFFF
 Enable All Interrupts. More...
 
#define XDMAPCIE_IM_DISABLE_ALL_MASK   0x00000000
 Disable All Interrupts. More...
 
Bus Location Register bitmaps and masks
#define XDMAPCIE_BL_FUNC_MASK   0x00000007
 Requester ID Function Number. More...
 
#define XDMAPCIE_BL_DEV_MASK   0x000000F8
 Requester ID Device Number. More...
 
#define XDMAPCIE_BL_BUS_MASK   0x0000FF00
 Requester ID Bus Number. More...
 
#define XDMAPCIE_BL_PORT_MASK   0x00FF0000
 Requester ID Port Number. More...
 
#define XDMAPCIE_BL_DEV_SHIFT   3
 Requester ID Device Number Shift Value. More...
 
#define XDMAPCIE_BL_BUS_SHIFT   8
 Requester ID Bus Number Shift Value. More...
 
#define XDMAPCIE_BL_PORT_SHIFT   16
 Requester ID Bus Number Shift Value. More...
 
PHY Status & Control Register bitmaps and masks
#define XDMAPCIE_PHYSC_LINK_RATE_MASK   0x00000001
 Link Rate. More...
 
#define XDMAPCIE_PHYSC_LINK_WIDTH_MASK   0x00000006
 Link Width Mask. More...
 
#define XDMAPCIE_PHYSC_LTSSM_STATE_MASK   0x000001F8
 LTSSM State Mask. More...
 
#define XDMAPCIE_PHYSC_LANE_REV_MASK   0x00000600
 Lane Reversal Mask. More...
 
#define XDMAPCIE_PHYSC_LINK_UP_MASK   0x00000800
 Link Up Status Mask. More...
 
#define XDMAPCIE_PHYSC_DLW_MASK   0x00030000
 Directed Link Width to change Mask. More...
 
#define XDMAPCIE_PHYSC_DLWS_MASK   0x00040000
 Directed Link Width Speed to change Mask. More...
 
#define XDMAPCIE_PHYSC_DLA_MASK   0x00080000
 Directed Link Change change to reliability or Autonomus Mask. More...
 
#define XDMAPCIE_PHYSC_DLC_MASK   0x00300000
 Directed Link change Mask. More...
 
#define XDMAPCIE_PHYSC_LINK_WIDTH_SHIFT   1
 Link Status Shift. More...
 
#define XDMAPCIE_PHYSC_LTSSM_STATE_SHIFT   3
 LTSSM State Shift. More...
 
#define XDMAPCIE_PHYSC_LANE_REV_SHIFT   9
 Lane Reversal Shift. More...
 
#define XDMAPCIE_PHYSC_LINK_UP_SHIFT   11
 Link Up Status Shift. More...
 
#define XDMAPCIE_PHYSC_DLW_SHIFT   16
 Directed Link Width to change Shift. More...
 
#define XDMAPCIE_PHYSC_DLWS_SHIFT   18
 Directed Link Width Speed to change Shift. More...
 
#define XDMAPCIE_PHYSC_DLA_SHIFT   19
 Directed Link change to reliability or Autonomus Shift. More...
 
#define XDMAPCIE_PHYSC_DLC_SHIFT   20
 Directed Link change Shift. More...
 
Root Port Status/Control Register bitmaps and masks
#define XDMAPCIE_RPSC_MASK   0x0FFF0001
 Root Port Register mask. More...
 
#define XDMAPCIE_RPSC_BRIDGE_ENABLE_MASK   0x00000001
 Bridge Enable Mask. More...
 
#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK   0x00010000
 Root Port Error FIFO Not Empty. More...
 
#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK   0x00020000
 Root Port Error FIFO Overflow. More...
 
#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK   0x00040000
 Root Port Interrupt FIFO Not Empty. More...
 
#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_MASK   0x00080000
 Root Port Interrupt FIFO Overflow. More...
 
#define XDMAPCIE_RPSC_COMP_TIMEOUT_MASK   0x0FF00000
 Root Port Completion Timeout. More...
 
#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT   16
 Root Port Error FIFO Empty Shift. More...
 
#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT   17
 Root Port Error FIFO Overflow Shift. More...
 
#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT   18
 Root Port Interrupt FIFO Empty Shift. More...
 
#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT   19
 Root Port Interrupt FIFO Overflow Shift. More...
 
#define XDMAPCIE_RPSC_COMP_TIMEOUT_SHIFT   20
 Root Port Completion Timeout Shift. More...
 
Root Port MSI Base Register bitmaps and masks
#define XDMAPCIE_RPMSIB_UPPER_MASK   0xFFFFFFFF
 Upper 32 bits of 64 bit MSI Base Address. More...
 
#define XDMAPCIE_RPMSIB_UPPER_SHIFT   32 /* Shift of Upper 32 bits */
 
#define XDMAPCIE_RPMSIB_LOWER_MASK   0xFFFFF000
 Lower 32 bits of 64 bit MSI Base Address. More...
 
Root Port Error FIFO Read Register bitmaps and masks
#define XDMAPCIE_RPEFR_REQ_ID_MASK   0x0000FFFF
 Requester of Error Msg. More...
 
#define XDMAPCIE_RPEFR_ERR_TYPE_MASK   0x00030000
 Type of Error. More...
 
#define XDMAPCIE_RPEFR_ERR_VALID_MASK   0x00040000
 Error Read Succeeded Status. More...
 
#define XDMAPCIE_RPEFR_ERR_TYPE_SHIFT   16
 Type of Error Shift. More...
 
#define XDMAPCIE_RPEFR_ERR_VALID_SHIFT   18
 Error Read Succeeded Status Shift. More...
 
Root Port Interrupt FIFO Read 1 Register bitmaps and masks
#define XDMAPCIE_RPIFR1_REQ_ID_MASK   0x0000FFFF
 Requester Id of Interrupt Message. More...
 
#define XDMAPCIE_RPIFR1_MSI_ADDR_MASK   0x07FF0000
 MSI Address. More...
 
#define XDMAPCIE_RPIFR1_INTR_LINE_MASK   0x18000000
 Intr Line Mask. More...
 
#define XDMAPCIE_RPIFR1_INTR_ASSERT_MASK   0x20000000
 Whether Interrupt INTx is asserted. More...
 
#define XDMAPCIE_RPIFR1_MSIINTR_VALID_MASK   0x40000000
 Whether Interrupt is MSI or INTx. More...
 
#define XDMAPCIE_RPIFR1_INTR_VALID_MASK   0x80000000
 Interrupt Read Succeeded Status. More...
 
#define XDMAPCIE_RPIFR1_MSI_ADDR_SHIFT   16
 MSI Address Shift. More...
 
#define XDMAPCIE_RPIFR1_MSIINTR_VALID_SHIFT   30
 MSI/INTx Interrupt Shift. More...
 
#define XDMAPCIE_RPIFR1_INTR_VALID_SHIFT   31
 Interrupt Read Valid Shift. More...
 
Root Port Interrupt FIFO Read 2 Register bitmaps and masks
#define XDMAPCIE_RPIFR2_MSG_DATA_MASK   0x0000FFFF
 Pay Load for MSI Message. More...
 
ECAM Address Register bitmaps and masks
#define XDMAPCIE_ECAM_MASK   0x0FFFFFFF
 Mask of all valid bits. More...
 
#define XDMAPCIE_ECAM_BUS_MASK   0x0FF00000
 Bus Number Mask. More...
 
#define XDMAPCIE_ECAM_DEV_MASK   0x000F8000
 Device Number Mask. More...
 
#define XDMAPCIE_ECAM_FUN_MASK   0x00007000
 Function Number Mask. More...
 
#define XDMAPCIE_ECAM_REG_MASK   0x00000FFC
 Register Number Mask. More...
 
#define XDMAPCIE_ECAM_BYT_MASK   0x00000003
 Byte Address Mask. More...
 
#define XDMAPCIE_ECAM_BUS_SHIFT   20
 Bus Number Shift Value. More...
 
#define XDMAPCIE_ECAM_DEV_SHIFT   15
 Device Number Shift Value. More...
 
#define XDMAPCIE_ECAM_FUN_SHIFT   12
 Function Number Shift Value. More...
 
#define XDMAPCIE_ECAM_REG_SHIFT   2
 Register Number Shift Value. More...
 
#define XDMAPCIE_ECAM_BYT_SHIFT   0
 Byte Offset Shift Value. More...
 

Macro Definition Documentation

#define XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET   0x20C

AXIBAR to PCIBAR translation 0 lower 32 bits.

Referenced by XDmaPcie_GetLocalBusBar2PcieBar(), and XDmaPcie_SetLocalBusBar2PcieBar().

#define XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET   0x208

AXIBAR 2 PCIBAR translation 0 upper 32 bits.

Referenced by XDmaPcie_GetLocalBusBar2PcieBar(), and XDmaPcie_SetLocalBusBar2PcieBar().

#define XDMAPCIE_AXIBAR2PCIBAR_1L_OFFSET   0x214

AXIBAR to PCIBAR translation 1 lower 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_1U_OFFSET   0x210

AXIBAR to PCIBAR translation 1 upper 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_2L_OFFSET   0x21C

AXIBAR to PCIBAR translation 2 lower 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_2U_OFFSET   0x218

AXIBAR to PCIBAR translation 2 upper 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_3L_OFFSET   0x224

AXIBAR to PCIBAR translation 3 lower 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_3U_OFFSET   0x220

AXIBAR to PCIBAR translation 3 upper 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_4L_OFFSET   0x22C

AXIBAR to PCIBAR translation 4 lower 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_4U_OFFSET   0x228

AXIBAR to PCIBAR translation 4 upper 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_5L_OFFSET   0x234

AXIBAR to PCIBAR translation 5 lower 32 bits.

#define XDMAPCIE_AXIBAR2PCIBAR_5U_OFFSET   0x230

AXIBAR to PCIBAR translation 5 upper 32 bits.

#define XDMAPCIE_BI_ECAM_SIZE_MASK   0x00070000

ECAM size.

Referenced by XDmaPcie_CfgInitialize(), and XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BI_ECAM_SIZE_SHIFT   16

PCIe ECAM Size Shift.

Referenced by XDmaPcie_CfgInitialize(), and XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BI_GEN2_MASK   0x00000001

PCIe Gen2 Speed Support Mask.

Referenced by XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BI_OFFSET   0x130

Bridge Info Register.

Referenced by XDmaPcie_CfgInitialize(), and XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BI_RP_MASK   0x00000002

PCIe Root Port Support.

Referenced by XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BI_RP_SHIFT   1

PCIe Root Port Shift.

Referenced by XDmaPcie_GetBridgeInfo().

#define XDMAPCIE_BL_BUS_MASK   0x0000FF00

Requester ID Bus Number.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_BUS_SHIFT   8

Requester ID Bus Number Shift Value.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_DEV_MASK   0x000000F8

Requester ID Device Number.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_DEV_SHIFT   3

Requester ID Device Number Shift Value.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_FUNC_MASK   0x00000007

Requester ID Function Number.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_OFFSET   0x140

Bus Location Register.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_PORT_MASK   0x00FF0000

Requester ID Port Number.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BL_PORT_SHIFT   16

Requester ID Bus Number Shift Value.

Referenced by XDmaPcie_GetRequesterId().

#define XDMAPCIE_BSC_ECAM_BUSY_MASK   0x00000001

ECAM Busy Status.

#define XDMAPCIE_BSC_GI_MASK   0x00000100

Global Interrupt Disable.

Referenced by XDmaPcie_DisableGlobalInterrupt(), and XDmaPcie_EnableGlobalInterrupt().

#define XDMAPCIE_BSC_GI_SHIFT   8

Global Interrupt Disable Shift.

Referenced by XDmaPcie_DisableGlobalInterrupt(), and XDmaPcie_EnableGlobalInterrupt().

#define XDMAPCIE_BSC_OFFSET   0x134

Bridge Status and Control Register.

Referenced by XDmaPcie_DisableGlobalInterrupt(), and XDmaPcie_EnableGlobalInterrupt().

#define XDMAPCIE_BSC_RO_MASK   0x00020000

RW Permissions to RO Registers.

#define XDMAPCIE_BSC_RO_SHIFT   17

RO as RW Shift.

#define XDMAPCIE_BSC_RW1C_MASK   0x00010000

RW Permissions to RW1C Registers.

#define XDMAPCIE_BSC_RW1C_SHIFT   16

RW1C Shift.

#define XDMAPCIE_ECAM_BUS_MASK   0x0FF00000

Bus Number Mask.

#define XDMAPCIE_ECAM_BUS_SHIFT   20

Bus Number Shift Value.

#define XDMAPCIE_ECAM_BYT_MASK   0x00000003

Byte Address Mask.

#define XDMAPCIE_ECAM_BYT_SHIFT   0

Byte Offset Shift Value.

#define XDMAPCIE_ECAM_DEV_MASK   0x000F8000

Device Number Mask.

#define XDMAPCIE_ECAM_DEV_SHIFT   15

Device Number Shift Value.

#define XDMAPCIE_ECAM_FUN_MASK   0x00007000

Function Number Mask.

#define XDMAPCIE_ECAM_FUN_SHIFT   12

Function Number Shift Value.

#define XDMAPCIE_ECAM_MASK   0x0FFFFFFF

Mask of all valid bits.

#define XDMAPCIE_ECAM_REG_MASK   0x00000FFC

Register Number Mask.

#define XDMAPCIE_ECAM_REG_SHIFT   2

Register Number Shift Value.

#define XDMAPCIE_ID_CFG_COMPL_STATE_MASK   0x000000E0

Cfg Completion Status Mask.

#define XDMAPCIE_ID_CFG_TIMEOUT_MASK   0x00000100

Cfg timeout Mask.

#define XDMAPCIE_ID_CLEAR_ALL_MASK   0xFFFFFFFF

Mask of all Interrupts.

Referenced by PcieInitRootComplex().

#define XDMAPCIE_ID_CMPL_ABT_MASK   0x01000000

Slave completion Abort Mask.

#define XDMAPCIE_ID_CMPL_TIMEOUT_MASK   0x00400000

Slave completion Time Mask.

#define XDMAPCIE_ID_CORRECTABLE_ERR_MASK   0x00000200

Correctable Error Mask.

#define XDMAPCIE_ID_DECODE_ERR_MASK   0x04000000

Master Decode Error Interrupt Mask.

#define XDMAPCIE_ID_ECRC_ERR_MASK   0x00000002

Rx Packet CRC failed.

#define XDMAPCIE_ID_FATAL_ERR_MASK   0x00000800

Fatal Error Mask.

#define XDMAPCIE_ID_HOT_RST_MASK   0x00000008

Hot Reset Mask.

#define XDMAPCIE_ID_ILL_BURST_MASK   0x02000000

Slave Illegal Burst Mask.

#define XDMAPCIE_ID_INTX_INTERRUPT   0x00010000

INTX Interrupt.

#define XDMAPCIE_ID_LINK_DOWN_MASK   0x00000001

Link Down Mask.

#define XDMAPCIE_ID_MASTER_EP_MASK   0x10000000

Master Error Poison Mask.

#define XDMAPCIE_ID_MSI_INTERRUPT   0x00020000

MSI Interrupt.

#define XDMAPCIE_ID_NONFATAL_ERR_MASK   0x00000400

Non-Fatal Error Mask.

#define XDMAPCIE_ID_OFFSET   0x138

Interrupt Decode Register.

Referenced by XDmaPcie_ClearPendingInterrupts(), and XDmaPcie_GetPendingInterrupts().

#define XDMAPCIE_ID_SLAVE_ERR_MASK   0x08000000

Master Slave Error Interrupt Mask.

#define XDMAPCIE_ID_SLV_EP_MASK   0x00800000

Slave Error Poison Mask.

#define XDMAPCIE_ID_STR_ERR_MASK   0x00000004

Streaming Error Mask.

#define XDMAPCIE_ID_UNEXP_CMPL_MASK   0x00200000

Slave Unexpected Completion Mask.

#define XDMAPCIE_ID_UNSUPP_CMPL_MASK   0x00100000

Slave Unsupported Request Mask.

#define XDMAPCIE_IM_DISABLE_ALL_MASK   0x00000000

Disable All Interrupts.

Referenced by XDmaPcie_CfgInitialize().

#define XDMAPCIE_IM_ENABLE_ALL_MASK   0xFFFFFFFF

Enable All Interrupts.

Referenced by PcieInitRootComplex().

#define XDMAPCIE_IM_OFFSET   0x13C
#define XDMAPCIE_PCIE_CORE_OFFSET   0x000

PCI Express hard core configuration register offset.

Referenced by XDmaPcie_ReadLocalConfigSpace(), and XDmaPcie_WriteLocalConfigSpace().

#define XDMAPCIE_PHYSC_DLA_MASK   0x00080000

Directed Link Change change to reliability or Autonomus Mask.

#define XDMAPCIE_PHYSC_DLA_SHIFT   19

Directed Link change to reliability or Autonomus Shift.

#define XDMAPCIE_PHYSC_DLC_MASK   0x00300000

Directed Link change Mask.

#define XDMAPCIE_PHYSC_DLC_SHIFT   20

Directed Link change Shift.

#define XDMAPCIE_PHYSC_DLW_MASK   0x00030000

Directed Link Width to change Mask.

#define XDMAPCIE_PHYSC_DLW_SHIFT   16

Directed Link Width to change Shift.

#define XDMAPCIE_PHYSC_DLWS_MASK   0x00040000

Directed Link Width Speed to change Mask.

#define XDMAPCIE_PHYSC_DLWS_SHIFT   18

Directed Link Width Speed to change Shift.

#define XDMAPCIE_PHYSC_LANE_REV_MASK   0x00000600

Lane Reversal Mask.

#define XDMAPCIE_PHYSC_LANE_REV_SHIFT   9

Lane Reversal Shift.

#define XDMAPCIE_PHYSC_LINK_RATE_MASK   0x00000001

Link Rate.

#define XDMAPCIE_PHYSC_LINK_UP_MASK   0x00000800

Link Up Status Mask.

#define XDMAPCIE_PHYSC_LINK_UP_SHIFT   11

Link Up Status Shift.

#define XDMAPCIE_PHYSC_LINK_WIDTH_MASK   0x00000006

Link Width Mask.

#define XDMAPCIE_PHYSC_LINK_WIDTH_SHIFT   1

Link Status Shift.

#define XDMAPCIE_PHYSC_LTSSM_STATE_MASK   0x000001F8

LTSSM State Mask.

#define XDMAPCIE_PHYSC_LTSSM_STATE_SHIFT   3

LTSSM State Shift.

#define XDMAPCIE_PHYSC_OFFSET   0x144

Physical status and Control Register.

Referenced by XDmaPcie_GetPhyStatusCtrl().

#define XDMAPCIE_RPEFR_ERR_TYPE_MASK   0x00030000

Type of Error.

Referenced by XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPEFR_ERR_TYPE_SHIFT   16

Type of Error Shift.

Referenced by XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPEFR_ERR_VALID_MASK   0x00040000

Error Read Succeeded Status.

Referenced by XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPEFR_ERR_VALID_SHIFT   18

Error Read Succeeded Status Shift.

Referenced by XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPEFR_OFFSET   0x154

Root Port Error FIFO Read Register.

Referenced by XDmaPcie_ClearRootPortErrFIFOMsg(), and XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPEFR_REQ_ID_MASK   0x0000FFFF

Requester of Error Msg.

Referenced by XDmaPcie_GetRootPortErrFIFOMsg().

#define XDMAPCIE_RPIFR1_INTR_ASSERT_MASK   0x20000000

Whether Interrupt INTx is asserted.

#define XDMAPCIE_RPIFR1_INTR_LINE_MASK   0x18000000

Intr Line Mask.

#define XDMAPCIE_RPIFR1_INTR_VALID_MASK   0x80000000

Interrupt Read Succeeded Status.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_INTR_VALID_SHIFT   31

Interrupt Read Valid Shift.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_MSI_ADDR_MASK   0x07FF0000

MSI Address.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_MSI_ADDR_SHIFT   16

MSI Address Shift.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_MSIINTR_VALID_MASK   0x40000000

Whether Interrupt is MSI or INTx.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_MSIINTR_VALID_SHIFT   30

MSI/INTx Interrupt Shift.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_OFFSET   0x158

Root Port Interrupt FIFO Read1 Register.

Referenced by XDmaPcie_ClearRootPortIntFIFOReg(), and XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR1_REQ_ID_MASK   0x0000FFFF

Requester Id of Interrupt Message.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR2_MSG_DATA_MASK   0x0000FFFF

Pay Load for MSI Message.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPIFR2_OFFSET   0x15C

Root Port Interrupt FIFO Read2 Register.

Referenced by XDmaPcie_GetRootPortIntFIFOReg().

#define XDMAPCIE_RPMSIB_LOWER_MASK   0xFFFFF000

Lower 32 bits of 64 bit MSI Base Address.

Referenced by XDmaPcie_SetRootPortMSIBase().

#define XDMAPCIE_RPMSIB_LOWER_OFFSET   0x150

Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written.

Referenced by XDmaPcie_SetRootPortMSIBase().

#define XDMAPCIE_RPMSIB_UPPER_MASK   0xFFFFFFFF

Upper 32 bits of 64 bit MSI Base Address.

Referenced by XDmaPcie_SetRootPortMSIBase().

#define XDMAPCIE_RPMSIB_UPPER_OFFSET   0x14C

Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written.

Referenced by XDmaPcie_SetRootPortMSIBase().

#define XDMAPCIE_RPSC_BRIDGE_ENABLE_MASK   0x00000001

Bridge Enable Mask.

#define XDMAPCIE_RPSC_COMP_TIMEOUT_MASK   0x0FF00000

Root Port Completion Timeout.

#define XDMAPCIE_RPSC_COMP_TIMEOUT_SHIFT   20

Root Port Completion Timeout Shift.

#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK   0x00010000

Root Port Error FIFO Not Empty.

#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT   16

Root Port Error FIFO Empty Shift.

#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK   0x00020000

Root Port Error FIFO Overflow.

#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT   17

Root Port Error FIFO Overflow Shift.

#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK   0x00040000

Root Port Interrupt FIFO Not Empty.

#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT   18

Root Port Interrupt FIFO Empty Shift.

#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_MASK   0x00080000

Root Port Interrupt FIFO Overflow.

#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT   19

Root Port Interrupt FIFO Overflow Shift.

#define XDMAPCIE_RPSC_MASK   0x0FFF0001

Root Port Register mask.

Referenced by XDmaPcie_SetRootPortStatusCtrl().

#define XDMAPCIE_RPSC_OFFSET   0x148

Root Port Status & Control Register.

Referenced by XDmaPcie_GetRootPortStatusCtrl(), and XDmaPcie_SetRootPortStatusCtrl().

#define XDMAPCIE_UP_CONFIG_CAPABLE   0x00000004

Up Config Capable.

#define XDMAPCIE_VSECC_ID_MASK   0x0000FFFF

Vsec capability Id.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECC_NEXT_MASK   0xFFF00000

Offset to next capability.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECC_NEXT_SHIFT   20

Next capability offset shift.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECC_OFFSET   0x128

VSEC Capability Register.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECC_VER_MASK   0x000F0000

Version of capability Structure.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECC_VER_SHIFT   16

VSEC Version shift.

Referenced by XDmaPcie_GetVsecCapability().

#define XDMAPCIE_VSECH_ID_MASK   0x0000FFFF

Vsec structure Id.

Referenced by XDmaPcie_GetVsecHeader().

#define XDMAPCIE_VSECH_LEN_MASK   0xFFF00000

Length of Vsec capability structure.

Referenced by XDmaPcie_GetVsecHeader().

#define XDMAPCIE_VSECH_LEN_SHIFT   20

Vsec length shift.

Referenced by XDmaPcie_GetVsecHeader().

#define XDMAPCIE_VSECH_OFFSET   0x12C

VSEC Header Register.

Referenced by XDmaPcie_GetVsecHeader().

#define XDMAPCIE_VSECH_REV_MASK   0x000F0000

Vsec header version.

Referenced by XDmaPcie_GetVsecHeader().

#define XDMAPCIE_VSECH_REV_SHIFT   16

Vsec version shift.

Referenced by XDmaPcie_GetVsecHeader().

#define XDmaPcie_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    Xil_Out32((BaseAddress) + (RegOffset), (Data))

Macro to write register.

Parameters
BaseAddressis the base address of the PCIe.
RegOffsetis the register offset.
Datais the data to write.
Returns
None
Note
C-style signature: void XDmaPcie_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XDmaPcie_ClearPendingInterrupts(), XDmaPcie_ClearRootPortErrFIFOMsg(), XDmaPcie_ClearRootPortIntFIFOReg(), XDmaPcie_DisableGlobalInterrupt(), XDmaPcie_DisableInterrupts(), XDmaPcie_EnableGlobalInterrupt(), XDmaPcie_EnableInterrupts(), XDmaPcie_SetLocalBusBar2PcieBar(), XDmaPcie_SetRootPortMSIBase(), XDmaPcie_SetRootPortStatusCtrl(), XDmaPcie_WriteLocalConfigSpace(), and XDmaPcie_WriteRemoteConfigSpace().