aiengine
Xilinx SDK Drivers API Documentation
XAieGbl_RegTileDmaCh Struct Reference

This typedef contains the attributes for Tile DMA Channel registers. More...

Data Fields

u32 CtrlOff
 Control register offset. More...
 
u32 StatQOff
 Start BD register offset. More...
 
u32 StsOff
 Status register offset. More...
 
XAieGbl_RegFldAttr Rst
 Reset bit field attributes. More...
 
XAieGbl_RegFldAttr En
 Enable bit field attributes. More...
 
XAieGbl_RegFldAttr StatQ
 Start BD bit field attributes. More...
 
XAieGbl_RegFldAttr Sts
 Channel status field attributes. More...
 

Detailed Description

This typedef contains the attributes for Tile DMA Channel registers.

Field Documentation

u32 XAieGbl_RegTileDmaCh::CtrlOff

Control register offset.

Referenced by XAieDma_TileChControl().

XAieGbl_RegFldAttr XAieGbl_RegTileDmaCh::En

Enable bit field attributes.

Referenced by XAieDma_TileChControl().

XAieGbl_RegFldAttr XAieGbl_RegTileDmaCh::Rst

Reset bit field attributes.

Referenced by XAieDma_TileChControl().

XAieGbl_RegFldAttr XAieGbl_RegTileDmaCh::StatQ

Start BD bit field attributes.

u32 XAieGbl_RegTileDmaCh::StatQOff

Start BD register offset.

XAieGbl_RegFldAttr XAieGbl_RegTileDmaCh::Sts

Channel status field attributes.

u32 XAieGbl_RegTileDmaCh::StsOff

Status register offset.