aiengine
Xilinx SDK Drivers API Documentation
XAieGbl_RegStrmMstr Struct Reference

This typedef contains the attributes for Stream switch master port config register. More...

Data Fields

u32 RegOff
 Register offset. More...
 
XAieGbl_RegFldAttr MstrEn
 Enable bit field attributes. More...
 
XAieGbl_RegFldAttr PktEn
 Packet enable bit field attributes. More...
 
XAieGbl_RegFldAttr DrpHdr
 Drop header bit field attributes. More...
 
XAieGbl_RegFldAttr Config
 Configuration bit field attributes. More...
 

Detailed Description

This typedef contains the attributes for Stream switch master port config register.

Field Documentation

XAieGbl_RegFldAttr XAieGbl_RegStrmMstr::Config

Configuration bit field attributes.

Referenced by XAieTile_StrmConfigMstr().

XAieGbl_RegFldAttr XAieGbl_RegStrmMstr::DrpHdr

Drop header bit field attributes.

Referenced by XAieTile_StrmConfigMstr().

XAieGbl_RegFldAttr XAieGbl_RegStrmMstr::MstrEn

Enable bit field attributes.

Referenced by XAieTile_StrmConfigMstr().

XAieGbl_RegFldAttr XAieGbl_RegStrmMstr::PktEn

Packet enable bit field attributes.

Referenced by XAieTile_StrmConfigMstr().

u32 XAieGbl_RegStrmMstr::RegOff

Register offset.

Referenced by XAieTile_StrmConfigMstr().