iicps
Xilinx SDK Drivers API Documentation
Iicps_v3_10

Data Structures

struct  XIicPs_Config
 This typedef contains configuration information for the device. More...
 
struct  XIicPs
 The XIicPs driver instance data. More...
 

Macros

#define XIICPS_POLL_DEFAULT_TIMEOUT_VAL   1000U
 Timeout in us. More...
 
#define XIicPs_ReadReg(BaseAddress, RegOffset)   XIicPs_In32((BaseAddress) + (u32)(RegOffset))
 Read an IIC register. More...
 
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue)   XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
 Write an IIC register. More...
 
#define XIicPs_ReadIER(BaseAddress)   XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
 Read the interrupt enable register. More...
 
#define XIicPs_EnableInterrupts(BaseAddress, IntrMask)   XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
 Write to the interrupt enable register. More...
 
#define XIicPs_DisableAllInterrupts(BaseAddress)
 Disable all interrupts. More...
 
#define XIicPs_DisableInterrupts(BaseAddress, IntrMask)
 Disable selected interrupts. More...
 

Functions

void XIicPs_ResetHw (u32 BaseAddress)
 This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specific registers the i2cps reset sequence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values. More...
 

Variables

u16 XIicPs_Config::DeviceId
 Unique ID of device. More...
 
u32 XIicPs_Config::BaseAddress
 Base address of the device. More...
 
u32 XIicPs_Config::InputClockHz
 Input clock frequency. More...
 
XIicPs_Config XIicPs_ConfigTable [XPAR_XIICPS_NUM_INSTANCES]
 This table contains configuration information for each IIC device in the system. More...
 
XIicPs_Config XIicPs_ConfigTable [XPAR_XIICPS_NUM_INSTANCES]
 This table contains configuration information for each IIC device in the system. More...
 

Configuration options

The following options may be specified or retrieved for the device and enable/disable additional features of the IIC.

Each of the options are bit fields, so more than one may be specified.

#define XIICPS_7_BIT_ADDR_OPTION   0x01U
 7-bit address mode More...
 
#define XIICPS_10_BIT_ADDR_OPTION   0x02U
 10-bit address mode More...
 
#define XIICPS_SLAVE_MON_OPTION   0x04U
 Slave monitor mode. More...
 
#define XIICPS_REP_START_OPTION   0x08U
 Repeated Start. More...
 

Callback events

These constants specify the handler events that are passed to an application event handler from the driver.

These constants are bit masks such that more than one event can be passed to the handler.

#define XIICPS_EVENT_COMPLETE_SEND   0x0001U
 Transmit Complete Event. More...
 
#define XIICPS_EVENT_COMPLETE_RECV   0x0002U
 Receive Complete Event. More...
 
#define XIICPS_EVENT_TIME_OUT   0x0004U
 Transfer timed out. More...
 
#define XIICPS_EVENT_ERROR   0x0008U
 Receive error. More...
 
#define XIICPS_EVENT_ARB_LOST   0x0010U
 Arbitration lost. More...
 
#define XIICPS_EVENT_NACK   0x0020U
 NACK Received. More...
 
#define XIICPS_EVENT_SLAVE_RDY   0x0040U
 Slave ready. More...
 
#define XIICPS_EVENT_RX_OVR   0x0080U
 RX overflow. More...
 
#define XIICPS_EVENT_TX_OVR   0x0100U
 TX overflow. More...
 
#define XIICPS_EVENT_RX_UNF   0x0200U
 RX underflow. More...
 

Role constants

These constants are used to pass into the device setup routines to set up the device according to transfer direction.

typedef void(* XIicPs_IntrHandler )(void *CallBackRef, u32 StatusEvent)
 The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...
 
s32 XIicPs_CfgInitialize (XIicPs *InstancePtr, XIicPs_Config *ConfigPtr, u32 EffectiveAddr)
 Initializes a specific XIicPs instance such that the driver is ready to use. More...
 
s32 XIicPs_BusIsBusy (XIicPs *InstancePtr)
 Check whether the I2C bus is busy. More...
 
void XIicPs_Abort (XIicPs *InstancePtr)
 Aborts a transfer in progress by resetting the FIFOs. More...
 
void XIicPs_Reset (XIicPs *InstancePtr)
 Resets the IIC device. More...
 
s32 TransmitFifoFill (XIicPs *InstancePtr)
 Put more data into the transmit FIFO, number of bytes is ether expected number of bytes for this transfer or available space in FIFO, which ever is less. More...
 
XIicPs_ConfigXIicPs_LookupConfig (u16 DeviceId)
 Looks up the device configuration based on the unique device ID. More...
 
void XIicPs_SetStatusHandler (XIicPs *InstancePtr, void *CallBackRef, XIicPs_IntrHandler FunctionPtr)
 This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More...
 
void XIicPs_MasterSend (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr)
 This function initiates an interrupt-driven send in master mode. More...
 
void XIicPs_MasterRecv (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr)
 This function initiates an interrupt-driven receive in master mode. More...
 
s32 XIicPs_MasterSendPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr)
 This function initiates a polled mode send in master mode. More...
 
s32 XIicPs_MasterRecvPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr)
 This function initiates a polled mode receive in master mode. More...
 
void XIicPs_EnableSlaveMonitor (XIicPs *InstancePtr, u16 SlaveAddr)
 This function enables the slave monitor mode. More...
 
void XIicPs_DisableSlaveMonitor (XIicPs *InstancePtr)
 This function disables slave monitor mode. More...
 
void XIicPs_MasterInterruptHandler (XIicPs *InstancePtr)
 The interrupt handler for the master mode. More...
 
void XIicPs_SetupSlave (XIicPs *InstancePtr, u16 SlaveAddr)
 This function sets up the device to be a slave. More...
 
void XIicPs_SlaveSend (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 This function setup a slave interrupt-driven send. More...
 
void XIicPs_SlaveRecv (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 This function setup a slave interrupt-driven receive. More...
 
s32 XIicPs_SlaveSendPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 This function sends a buffer in polled mode as a slave. More...
 
s32 XIicPs_SlaveRecvPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 This function receives a buffer in polled mode as a slave. More...
 
void XIicPs_SlaveInterruptHandler (XIicPs *InstancePtr)
 The interrupt handler for slave mode. More...
 
s32 XIicPs_SelfTest (XIicPs *InstancePtr)
 Runs a self-test on the driver/device. More...
 
s32 XIicPs_SetOptions (XIicPs *InstancePtr, u32 Options)
 This function sets the options for the IIC device driver. More...
 
s32 XIicPs_ClearOptions (XIicPs *InstancePtr, u32 Options)
 This function clears the options for the IIC device driver. More...
 
u32 XIicPs_GetOptions (XIicPs *InstancePtr)
 This function gets the options for the IIC device. More...
 
s32 XIicPs_SetSClk (XIicPs *InstancePtr, u32 FsclHz)
 This function sets the serial clock rate for the IIC device. More...
 
u32 XIicPs_GetSClk (XIicPs *InstancePtr)
 This function gets the serial clock rate for the IIC device. More...
 
#define SENDING_ROLE   1
 Transfer direction is sending. More...
 
#define RECVING_ROLE   0
 Transfer direction is receiving. More...
 
#define XIICPS_MAX_TRANSFER_SIZE   (u32)(255U - 3U)
 Max transfer size. More...
 
#define XIicPs_SendByte(InstancePtr)
 Place one byte into the transmit FIFO. More...
 
#define XIicPs_RecvByte(InstancePtr)
 Receive one byte from FIFO. More...
 

Register Map

Register offsets for the IIC.

#define XIICPS_CR_OFFSET   0x00U
 32-bit Control More...
 
#define XIICPS_SR_OFFSET   0x04U
 Status. More...
 
#define XIICPS_ADDR_OFFSET   0x08U
 IIC Address. More...
 
#define XIICPS_DATA_OFFSET   0x0CU
 IIC FIFO Data. More...
 
#define XIICPS_ISR_OFFSET   0x10U
 Interrupt Status. More...
 
#define XIICPS_TRANS_SIZE_OFFSET   0x14U
 Transfer Size. More...
 
#define XIICPS_SLV_PAUSE_OFFSET   0x18U
 Slave monitor pause. More...
 
#define XIICPS_TIME_OUT_OFFSET   0x1CU
 Time Out. More...
 
#define XIICPS_IMR_OFFSET   0x20U
 Interrupt Enabled Mask. More...
 
#define XIICPS_IER_OFFSET   0x24U
 Interrupt Enable. More...
 
#define XIICPS_IDR_OFFSET   0x28U
 Interrupt Disable. More...
 

Control Register

This register contains various control bits that affects the operation of the IIC controller.

Read/Write.

#define XIICPS_CR_DIV_A_MASK   0x0000C000U
 Clock Divisor A. More...
 
#define XIICPS_CR_DIV_A_SHIFT   14U
 Clock Divisor A shift. More...
 
#define XIICPS_DIV_A_MAX   4U
 Maximum value of Divisor A. More...
 
#define XIICPS_CR_DIV_B_MASK   0x00003F00U
 Clock Divisor B. More...
 
#define XIICPS_CR_DIV_B_SHIFT   8U
 Clock Divisor B shift. More...
 
#define XIICPS_CR_CLR_FIFO_MASK   0x00000040U
 Clear FIFO, auto clears. More...
 
#define XIICPS_CR_SLVMON_MASK   0x00000020U
 Slave monitor mode. More...
 
#define XIICPS_CR_HOLD_MASK   0x00000010U
 Hold bus 1=Hold scl, 0=terminate transfer. More...
 
#define XIICPS_CR_ACKEN_MASK   0x00000008U
 Enable TX of ACK when Master receiver. More...
 
#define XIICPS_CR_NEA_MASK   0x00000004U
 Addressing Mode 1=7 bit, 0=10 bit. More...
 
#define XIICPS_CR_MS_MASK   0x00000002U
 Master mode bit 1=Master, 0=Slave. More...
 
#define XIICPS_CR_RD_WR_MASK   0x00000001U
 Read or Write Master transfer 0=Transmitter, 1=Receiver. More...
 
#define XIICPS_CR_RESET_VALUE   0U
 Reset value of the Control register. More...
 

IIC Status Register

This register is used to indicate status of the IIC controller.

Read only

#define XIICPS_SR_BA_MASK   0x00000100U
 Bus Active Mask. More...
 
#define XIICPS_SR_RXOVF_MASK   0x00000080U
 Receiver Overflow Mask. More...
 
#define XIICPS_SR_TXDV_MASK   0x00000040U
 Transmit Data Valid Mask. More...
 
#define XIICPS_SR_RXDV_MASK   0x00000020U
 Receiver Data Valid Mask. More...
 
#define XIICPS_SR_RXRW_MASK   0x00000008U
 Receive read/write Mask. More...
 

IIC Address Register

Normal addressing mode uses add[6:0].

Extended addressing mode uses add[9:0]. A write access to this register always initiates a transfer if the IIC is in master mode. Read/Write

#define XIICPS_ADDR_MASK   0x000003FF
 IIC Address Mask. More...
 

IIC Data Register

When written to, the data register sets data to transmit.

When read from, the data register reads the last received byte of data. Read/Write

#define XIICPS_DATA_MASK   0x000000FF
 IIC Data Mask. More...
 

IIC Interrupt Registers

IIC Interrupt Status Register

This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered

  • i.e. are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set one the interrupt condition occurs then remain set until they are cleared by software. The interrupts are cleared by writing a one to the interrupt bit position in the Interrupt Status Register. Read/Write.

IIC Interrupt Enable Register

This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only.

IIC Interrupt Disable Register

This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only.

IIC Interrupt Mask Register

This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only.

All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register

#define XIICPS_IXR_ARB_LOST_MASK   0x00000200U
 Arbitration Lost Interrupt mask. More...
 
#define XIICPS_IXR_RX_UNF_MASK   0x00000080U
 FIFO Receive Underflow Interrupt mask. More...
 
#define XIICPS_IXR_TX_OVR_MASK   0x00000040U
 Transmit Overflow Interrupt mask. More...
 
#define XIICPS_IXR_RX_OVR_MASK   0x00000020U
 Receive Overflow Interrupt mask. More...
 
#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U
 Monitored Slave Ready Interrupt mask. More...
 
#define XIICPS_IXR_TO_MASK   0x00000008U
 Transfer Time Out Interrupt mask. More...
 
#define XIICPS_IXR_NACK_MASK   0x00000004U
 NACK Interrupt mask. More...
 
#define XIICPS_IXR_DATA_MASK   0x00000002U
 Data Interrupt mask. More...
 
#define XIICPS_IXR_COMP_MASK   0x00000001U
 Transfer Complete Interrupt mask. More...
 
#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU
 Default ISR Mask. More...
 
#define XIICPS_IXR_ALL_INTR_MASK   0x000002FFU
 All ISR Mask. More...
 

IIC Transfer Size Register

The register's meaning varies according to the operating mode as follows:

  • Master transmitter mode: number of data bytes still not transmitted minus one
  • Master receiver mode: number of data bytes that are still expected to be received
  • Slave transmitter mode: number of bytes remaining in the FIFO after the master terminates the transfer
  • Slave receiver mode: number of valid data bytes in the FIFO

This register is cleared if CLR_FIFO bit in the control register is set. Read/Write

#define XIICPS_TRANS_SIZE_MASK   0x0000003F
 IIC Transfer Size Mask. More...
 
#define XIICPS_FIFO_DEPTH   16
 Number of bytes in the FIFO. More...
 
#define XIICPS_DATA_INTR_DEPTH   14
 Number of bytes at DATA intr. More...
 

IIC Slave Monitor Pause Register

This register is associated with the slave monitor mode of the I2C interface.

It is meaningful only when the module is in master mode and bit SLVMON in the control register is set.

This register defines the pause interval between consecutive attempts to address the slave once a write to an I2C address register is done by the host. It represents the number of sclk cycles minus one between two attempts.

The reset value of the register is 0, which results in the master repeatedly trying to access the slave immediately after unsuccessful attempt. Read/Write

#define XIICPS_SLV_PAUSE_MASK   0x0000000F
 Slave monitor pause mask. More...
 

IIC Time Out Register

The value of time out register represents the time out interval in number of sclk cycles minus one.

When the accessed slave holds the sclk line low for longer than the time out period, thus prohibiting the I2C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set.

The reset value of the register is 0x1f. Read/Write

#define XIICPS_TIME_OUT_MASK   0x000000FFU
 IIC Time Out mask. More...
 
#define XIICPS_TO_RESET_VALUE   0x000000FFU
 IIC Time Out reset value. More...
 

Macro Definition Documentation

#define RECVING_ROLE   0

Transfer direction is receiving.

Referenced by XIicPs_MasterRecv(), and XIicPs_MasterRecvPolled().

#define SENDING_ROLE   1

Transfer direction is sending.

Referenced by XIicPs_MasterSend(), and XIicPs_MasterSendPolled().

#define XIICPS_10_BIT_ADDR_OPTION   0x02U

10-bit address mode

Referenced by XIicPs_ClearOptions(), XIicPs_GetOptions(), and XIicPs_SetOptions().

#define XIICPS_7_BIT_ADDR_OPTION   0x01U

7-bit address mode

#define XIICPS_ADDR_MASK   0x000003FF
#define XIICPS_CR_ACKEN_MASK   0x00000008U

Enable TX of ACK when Master receiver.

Referenced by XIicPs_ResetHw(), and XIicPs_SetupSlave().

#define XIICPS_CR_CLR_FIFO_MASK   0x00000040U

Clear FIFO, auto clears.

Referenced by XIicPs_Abort(), XIicPs_EnableSlaveMonitor(), XIicPs_ResetHw(), and XIicPs_SetupSlave().

#define XIICPS_CR_DIV_A_MASK   0x0000C000U

Clock Divisor A.

Referenced by XIicPs_GetSClk(), and XIicPs_SetSClk().

#define XIICPS_CR_DIV_A_SHIFT   14U

Clock Divisor A shift.

Referenced by XIicPs_GetSClk(), and XIicPs_SetSClk().

#define XIICPS_CR_DIV_B_MASK   0x00003F00U

Clock Divisor B.

Referenced by XIicPs_GetSClk(), and XIicPs_SetSClk().

#define XIICPS_CR_DIV_B_SHIFT   8U

Clock Divisor B shift.

Referenced by XIicPs_GetSClk(), and XIicPs_SetSClk().

#define XIICPS_CR_HOLD_MASK   0x00000010U
#define XIICPS_CR_MS_MASK   0x00000002U

Master mode bit 1=Master, 0=Slave.

Referenced by XIicPs_EnableSlaveMonitor(), XIicPs_ResetHw(), and XIicPs_SetupSlave().

#define XIICPS_CR_NEA_MASK   0x00000004U

Addressing Mode 1=7 bit, 0=10 bit.

Referenced by XIicPs_EnableSlaveMonitor(), XIicPs_GetOptions(), and XIicPs_SetupSlave().

#define XIICPS_CR_RD_WR_MASK   0x00000001U

Read or Write Master transfer 0=Transmitter, 1=Receiver.

Referenced by XIicPs_EnableSlaveMonitor().

#define XIICPS_CR_RESET_VALUE   0U

Reset value of the Control register.

Referenced by XIicPs_Abort(), XIicPs_Reset(), and XIicPs_SelfTest().

#define XIICPS_CR_SLVMON_MASK   0x00000020U

Slave monitor mode.

Referenced by XIicPs_DisableSlaveMonitor(), and XIicPs_EnableSlaveMonitor().

#define XIICPS_DATA_INTR_DEPTH   14

Number of bytes at DATA intr.

Referenced by XIicPs_MasterInterruptHandler(), and XIicPs_MasterRecvPolled().

#define XIICPS_DATA_MASK   0x000000FF

IIC Data Mask.

#define XIICPS_DATA_OFFSET   0x0CU

IIC FIFO Data.

#define XIicPs_DisableAllInterrupts (   BaseAddress)
Value:
#define XIICPS_IDR_OFFSET
Interrupt Disable.
Definition: xiicps_hw.h:80
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an IIC register.
Definition: xiicps_hw.h:312
#define XIICPS_IXR_ALL_INTR_MASK
All ISR Mask.
Definition: xiicps_hw.h:211

Disable all interrupts.

Parameters
BaseAddresscontains the base address of the device.
Returns
None.
Note
C-Style signature: void XIicPs_DisableAllInterrupts(u32 BaseAddress)

Referenced by XIicPs_SetupSlave().

#define XIicPs_DisableInterrupts (   BaseAddress,
  IntrMask 
)
Value:
(IntrMask))
#define XIICPS_IDR_OFFSET
Interrupt Disable.
Definition: xiicps_hw.h:80
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write an IIC register.
Definition: xiicps_hw.h:312

Disable selected interrupts.

Parameters
BaseAddresscontains the base address of the device.
IntrMaskis the interrupts to be disabled.
Returns
None.
Note
C-Style signature: void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)

Referenced by XIicPs_DisableSlaveMonitor(), and XIicPs_MasterInterruptHandler().

#define XIICPS_DIV_A_MAX   4U

Maximum value of Divisor A.

#define XIicPs_EnableInterrupts (   BaseAddress,
  IntrMask 
)    XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))

Write to the interrupt enable register.

Parameters
BaseAddresscontains the base address of the device.
IntrMaskis the interrupts to be enabled.
Returns
None.
Note
C-Style signature: void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)

Referenced by XIicPs_EnableSlaveMonitor(), XIicPs_MasterInterruptHandler(), XIicPs_MasterRecv(), XIicPs_MasterSend(), XIicPs_SlaveRecv(), and XIicPs_SlaveSend().

#define XIICPS_EVENT_ARB_LOST   0x0010U

Arbitration lost.

Referenced by XIicPs_MasterInterruptHandler().

#define XIICPS_EVENT_COMPLETE_RECV   0x0002U

Receive Complete Event.

Referenced by Handler(), XIicPs_MasterInterruptHandler(), and XIicPs_SlaveInterruptHandler().

#define XIICPS_EVENT_COMPLETE_SEND   0x0001U

Transmit Complete Event.

Referenced by Handler(), XIicPs_MasterInterruptHandler(), and XIicPs_SlaveInterruptHandler().

#define XIICPS_EVENT_ERROR   0x0008U
#define XIICPS_EVENT_NACK   0x0020U
#define XIICPS_EVENT_RX_OVR   0x0080U

RX overflow.

#define XIICPS_EVENT_RX_UNF   0x0200U

RX underflow.

#define XIICPS_EVENT_SLAVE_RDY   0x0040U

Slave ready.

Referenced by Handler(), and XIicPs_MasterInterruptHandler().

#define XIICPS_EVENT_TIME_OUT   0x0004U

Transfer timed out.

Referenced by XIicPs_MasterInterruptHandler().

#define XIICPS_EVENT_TX_OVR   0x0100U

TX overflow.

#define XIICPS_IDR_OFFSET   0x28U

Interrupt Disable.

Referenced by XIicPs_Abort(), XIicPs_Reset(), and XIicPs_ResetHw().

#define XIICPS_IER_OFFSET   0x24U

Interrupt Enable.

Referenced by XIicPs_Abort().

#define XIICPS_IMR_OFFSET   0x20U
#define XIICPS_IXR_ALL_INTR_MASK   0x000002FFU

All ISR Mask.

Referenced by XIicPs_Abort(), XIicPs_Reset(), XIicPs_ResetHw(), and XIicPs_SelfTest().

#define XIICPS_IXR_ARB_LOST_MASK   0x00000200U
#define XIICPS_IXR_DATA_MASK   0x00000002U
#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU

Default ISR Mask.

#define XIICPS_IXR_RX_OVR_MASK   0x00000020U
#define XIICPS_IXR_RX_UNF_MASK   0x00000080U
#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U

Monitored Slave Ready Interrupt mask.

Referenced by XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), and XIicPs_MasterInterruptHandler().

#define XIICPS_IXR_TO_MASK   0x00000008U
#define XIICPS_IXR_TX_OVR_MASK   0x00000040U
#define XIICPS_MAX_TRANSFER_SIZE   (u32)(255U - 3U)
#define XIICPS_POLL_DEFAULT_TIMEOUT_VAL   1000U

Timeout in us.

Referenced by XIicPs_SlaveSendPolled().

#define XIicPs_ReadIER (   BaseAddress)    XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)

Read the interrupt enable register.

Parameters
BaseAddresscontains the base address of the device.
Returns
Current bit mask that represents currently enabled interrupts.
Note
C-Style signature: u32 XIicPs_ReadIER(u32 BaseAddress)
#define XIicPs_ReadReg (   BaseAddress,
  RegOffset 
)    XIicPs_In32((BaseAddress) + (u32)(RegOffset))

Read an IIC register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to select the specific register.
Returns
The value read from the register.
Note
C-Style signature: u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)

Referenced by TransmitFifoFill(), XIicPs_Abort(), XIicPs_BusIsBusy(), XIicPs_ClearOptions(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_GetOptions(), XIicPs_GetSClk(), XIicPs_MasterInterruptHandler(), XIicPs_MasterRecv(), XIicPs_MasterRecvPolled(), XIicPs_MasterSend(), XIicPs_MasterSendPolled(), XIicPs_ResetHw(), XIicPs_SelfTest(), XIicPs_SetOptions(), XIicPs_SetSClk(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().

#define XIicPs_RecvByte (   InstancePtr)
Value:
{ \
u8 *Data, Value; \
Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ (u32)XIICPS_DATA_OFFSET)); \
Data = &Value; \
*(InstancePtr)->RecvBufferPtr = *Data; \
(InstancePtr)->RecvBufferPtr += 1; \
(InstancePtr)->RecvByteCount --; \
}
#define XIICPS_DATA_OFFSET
IIC FIFO Data.
Definition: xiicps_hw.h:73

Receive one byte from FIFO.

Parameters
InstancePtris the instance of IIC
Returns
None.
Note
C-Style signature: u8 XIicPs_RecvByte(XIicPs *InstancePtr)

Referenced by XIicPs_MasterInterruptHandler(), XIicPs_MasterRecvPolled(), and XIicPs_SlaveRecvPolled().

#define XIICPS_REP_START_OPTION   0x08U
#define XIicPs_SendByte (   InstancePtr)
Value:
{ \
u8 Data; \
Data = *((InstancePtr)->SendBufferPtr); \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ (u32)(XIICPS_DATA_OFFSET), \
(u32)(Data)); \
(InstancePtr)->SendBufferPtr += 1; \
(InstancePtr)->SendByteCount -= 1;\
}
#define XIICPS_DATA_OFFSET
IIC FIFO Data.
Definition: xiicps_hw.h:73

Place one byte into the transmit FIFO.

Parameters
InstancePtris the instance of IIC
Returns
None.
Note
C-Style signature: void XIicPs_SendByte(XIicPs *InstancePtr)

Referenced by TransmitFifoFill(), and XIicPs_SlaveSendPolled().

#define XIICPS_SLAVE_MON_OPTION   0x04U

Slave monitor mode.

#define XIICPS_SLV_PAUSE_MASK   0x0000000F

Slave monitor pause mask.

#define XIICPS_SLV_PAUSE_OFFSET   0x18U

Slave monitor pause.

Referenced by XIicPs_EnableSlaveMonitor(), and XIicPs_SelfTest().

#define XIICPS_SR_BA_MASK   0x00000100U

Bus Active Mask.

Referenced by XIicPs_BusIsBusy().

#define XIICPS_SR_RXDV_MASK   0x00000020U
#define XIICPS_SR_RXOVF_MASK   0x00000080U

Receiver Overflow Mask.

#define XIICPS_SR_RXRW_MASK   0x00000008U

Receive read/write Mask.

Referenced by XIicPs_SlaveSendPolled().

#define XIICPS_SR_TXDV_MASK   0x00000040U

Transmit Data Valid Mask.

Referenced by XIicPs_MasterSendPolled(), and XIicPs_SlaveSendPolled().

#define XIICPS_TIME_OUT_MASK   0x000000FFU

IIC Time Out mask.

#define XIICPS_TIME_OUT_OFFSET   0x1CU

Time Out.

Referenced by XIicPs_Reset(), and XIicPs_ResetHw().

#define XIICPS_TO_RESET_VALUE   0x000000FFU

IIC Time Out reset value.

Referenced by XIicPs_Reset(), and XIicPs_ResetHw().

#define XIICPS_TRANS_SIZE_MASK   0x0000003F

IIC Transfer Size Mask.

#define XIicPs_WriteReg (   BaseAddress,
  RegOffset,
  RegisterValue 
)    XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))

Write an IIC register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to select the specific register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)

Referenced by XIicPs_Abort(), XIicPs_ClearOptions(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_MasterInterruptHandler(), XIicPs_MasterRecv(), XIicPs_MasterRecvPolled(), XIicPs_MasterSend(), XIicPs_MasterSendPolled(), XIicPs_Reset(), XIicPs_ResetHw(), XIicPs_SelfTest(), XIicPs_SetOptions(), XIicPs_SetSClk(), XIicPs_SetupSlave(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().

Typedef Documentation

typedef void(* XIicPs_IntrHandler)(void *CallBackRef, u32 StatusEvent)

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters
CallBackRefis the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEventindicates one or more status events that occurred.

Function Documentation

s32 TransmitFifoFill ( XIicPs InstancePtr)

Put more data into the transmit FIFO, number of bytes is ether expected number of bytes for this transfer or available space in FIFO, which ever is less.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
Number of bytes left for this instance.
Note
This is function is shared by master and slave.

References XIicPs_Config::BaseAddress, XIICPS_FIFO_DEPTH, XIicPs_ReadReg, XIicPs_SendByte, and XIICPS_TRANS_SIZE_OFFSET.

Referenced by XIicPs_MasterSend(), XIicPs_MasterSendPolled(), and XIicPs_SlaveInterruptHandler().

void XIicPs_Abort ( XIicPs InstancePtr)

Aborts a transfer in progress by resetting the FIFOs.

The byte counts are cleared.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IDR_OFFSET, XIICPS_IER_OFFSET, XIICPS_IMR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.

Referenced by XIicPs_Reset().

s32 XIicPs_BusIsBusy ( XIicPs InstancePtr)

Check whether the I2C bus is busy.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
  • TRUE if the bus is busy.
  • FALSE if the bus is not busy.
Note
None.

References XIicPs_Config::BaseAddress, XIicPs_ReadReg, XIICPS_SR_BA_MASK, and XIICPS_SR_OFFSET.

Referenced by EepromReadDataRepStart(), EepromWriteData(), IicPsMasterIntrExample(), IicPsMasterPolledExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

s32 XIicPs_CfgInitialize ( XIicPs InstancePtr,
XIicPs_Config ConfigPtr,
u32  EffectiveAddr 
)

Initializes a specific XIicPs instance such that the driver is ready to use.

The state of the device after initialization is:

  • Device is disabled
  • Slave mode
Parameters
InstancePtris a pointer to the XIicPs instance.
ConfigPtris a reference to a structure containing information about a specific IIC device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddris the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->BaseAddress for this parameter, passing the physical address instead.
Returns
The return value is XST_SUCCESS if successful.
Note
None.

References XIicPs_Config::BaseAddress, XIicPs_Config::DeviceId, XIicPs_Config::InputClockHz, XIicPs_GetOptions(), and XIicPs_Reset().

Referenced by IicPsMasterIntrExample(), IicPsMasterPolledExample(), IicPsRepeatedStartExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

s32 XIicPs_ClearOptions ( XIicPs InstancePtr,
u32  Options 
)

This function clears the options for the IIC device driver.

The options control how the device behaves relative to the IIC bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters
InstancePtris a pointer to the XIicPs instance.
Optionscontains the specified options to be cleared. This is a bit mask where a 1 means to turn the option off. One or more bit values may be contained in the mask. See the bit definitions named XIICPS_*_OPTION in xiicps.h.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_IS_STARTED if the device is currently transferring data. The transfer must complete or be aborted before setting options.
Note
None

References XIicPs_Config::BaseAddress, XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_OFFSET, XIicPs_GetOptions(), XIicPs_ReadReg, XIICPS_REP_START_OPTION, and XIicPs_WriteReg.

Referenced by EepromReadDataRepStart().

void XIicPs_DisableSlaveMonitor ( XIicPs InstancePtr)

This function disables slave monitor mode.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIICPS_CR_SLVMON_MASK, XIicPs_DisableInterrupts, XIICPS_IXR_SLV_RDY_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.

void XIicPs_EnableSlaveMonitor ( XIicPs InstancePtr,
u16  SlaveAddr 
)

This function enables the slave monitor mode.

It enables slave monitor in the control register and enables slave ready interrupt. It then does an address transfer to slave. Interrupt handler will signal the caller if slave responds to the address transfer.

Parameters
InstancePtris a pointer to the XIicPs instance.
SlaveAddris the address of the slave we want to contact.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_ADDR_OFFSET, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_MS_MASK, XIICPS_CR_NEA_MASK, XIICPS_CR_OFFSET, XIICPS_CR_RD_WR_MASK, XIICPS_CR_SLVMON_MASK, XIicPs_EnableInterrupts, XIICPS_IXR_SLV_RDY_MASK, XIicPs_ReadReg, XIICPS_SLV_PAUSE_OFFSET, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

u32 XIicPs_GetOptions ( XIicPs InstancePtr)

This function gets the options for the IIC device.

The options control how the device behaves relative to the IIC bus.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
32 bit mask of the options, where a 1 means the option is on, and a 0 means to the option is off. One or more bit values may be contained in the mask. See the bit definitions named XIICPS_*_OPTION in the file xiicps.h.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK, XIICPS_CR_OFFSET, XIicPs_ReadReg, and XIICPS_REP_START_OPTION.

Referenced by XIicPs_CfgInitialize(), XIicPs_ClearOptions(), and XIicPs_SetOptions().

u32 XIicPs_GetSClk ( XIicPs InstancePtr)

This function gets the serial clock rate for the IIC device.

The device must be idle rather than busy transferring data before setting these device options.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
The value of the IIC clock to the nearest Hz based on the control register settings. The actual value may not be exact to to integer math rounding errors.
Note
None.

References XIicPs_Config::BaseAddress, XIicPs_Config::InputClockHz, XIICPS_CR_DIV_A_MASK, XIICPS_CR_DIV_A_SHIFT, XIICPS_CR_DIV_B_MASK, XIICPS_CR_DIV_B_SHIFT, XIICPS_CR_OFFSET, and XIicPs_ReadReg.

XIicPs_Config * XIicPs_LookupConfig ( u16  DeviceId)

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters
DeviceIdcontains the ID of the device to look up the configuration for.
Returns
A pointer to the configuration found or NULL if the specified device ID was not found. See xiicps.h for the definition of XIicPs_Config.
Note
None.

Referenced by IicPsMasterIntrExample(), IicPsMasterPolledExample(), IicPsRepeatedStartExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

void XIicPs_MasterInterruptHandler ( XIicPs InstancePtr)

The interrupt handler for the master mode.

It does the protocol handling for the interrupt-driven transfers.

Completion events and errors are signaled to upper layer for proper handling.

The interrupts that are handled are:

  • DATA This case is handled only for master receive data. The master has to request for more data (if there is more data to receive) and read the data from the FIFO .
  • COMP If the Master is transmitting data and there is more data to be sent then the data is written to the FIFO. If there is no more data to be transmitted then a completion event is signalled to the upper layer by calling the callback handler.

    If the Master is receiving data then the data is read from the FIFO and the Master has to request for more data (if there is more data to receive). If all the data has been received then a completion event is signalled to the upper layer by calling the callback handler. It is an error if the amount of received data is more than expected.

  • NAK and SLAVE_RDY This is signalled to the upper layer by calling the callback handler.
  • All Other interrupts These interrupts are marked as error. This is signalled to the upper layer by calling the callback handler.
Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_ADDR_OFFSET, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIICPS_DATA_INTR_DEPTH, XIicPs_DisableInterrupts, XIicPs_EnableInterrupts, XIICPS_EVENT_ARB_LOST, XIICPS_EVENT_COMPLETE_RECV, XIICPS_EVENT_COMPLETE_SEND, XIICPS_EVENT_ERROR, XIICPS_EVENT_NACK, XIICPS_EVENT_SLAVE_RDY, XIICPS_EVENT_TIME_OUT, XIICPS_FIFO_DEPTH, XIICPS_IMR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_ARB_LOST_MASK, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_RX_UNF_MASK, XIICPS_IXR_SLV_RDY_MASK, XIICPS_IXR_TO_MASK, XIICPS_IXR_TX_OVR_MASK, XIICPS_MAX_TRANSFER_SIZE, XIicPs_ReadReg, XIicPs_RecvByte, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

void XIicPs_MasterRecv ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount,
u16  SlaveAddr 
)

This function initiates an interrupt-driven receive in master mode.

It sets the transfer size register so the slave can send data to us. The rest of the work is managed by interrupt handler.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the receive buffer.
ByteCountis the number of bytes to be received.
SlaveAddris the address of the slave we are receiving from.
Returns
None.
Note
This receive routine is for interrupt-driven transfer only.

References XIicPs_Config::BaseAddress, RECVING_ROLE, XIICPS_ADDR_MASK, XIICPS_ADDR_OFFSET, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIicPs_EnableInterrupts, XIICPS_FIFO_DEPTH, XIICPS_IXR_ARB_LOST_MASK, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_TO_MASK, XIICPS_MAX_TRANSFER_SIZE, XIicPs_ReadReg, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

Referenced by IicPsMasterIntrExample().

s32 XIicPs_MasterRecvPolled ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount,
u16  SlaveAddr 
)

This function initiates a polled mode receive in master mode.

It repeatedly sets the transfer size register so the slave can send data to us. It polls the data register for data to come in. If master fails to read data due arbitration lost, will return with arbitration lost status. If slave fails to send us data, it fails with time out.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the receive buffer.
ByteCountis the number of bytes to be received.
SlaveAddris the address of the slave we are receiving from.
Returns
  • XST_SUCCESS if everything went well.
  • XST_FAILURE if timed out.
  • XST_IIC_ARB_LOST if arbitration lost
Note
This receive routine is for polled mode transfer only.

References XIicPs_Config::BaseAddress, RECVING_ROLE, XIICPS_ADDR_MASK, XIICPS_ADDR_OFFSET, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIICPS_DATA_INTR_DEPTH, XIICPS_FIFO_DEPTH, XIICPS_ISR_OFFSET, XIICPS_IXR_ARB_LOST_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_RX_UNF_MASK, XIICPS_MAX_TRANSFER_SIZE, XIicPs_ReadReg, XIicPs_RecvByte, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

Referenced by EepromReadDataRepStart(), and IicPsMasterPolledExample().

void XIicPs_MasterSend ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount,
u16  SlaveAddr 
)

This function initiates an interrupt-driven send in master mode.

It tries to send the first FIFO-full of data, then lets the interrupt handler to handle the rest of the data if there is any.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the send buffer.
ByteCountis the number of bytes to be sent.
SlaveAddris the address of the slave we are sending to.
Returns
None.
Note
This send routine is for interrupt-driven transfer only.

References XIicPs_Config::BaseAddress, SENDING_ROLE, TransmitFifoFill(), XIICPS_ADDR_MASK, XIICPS_ADDR_OFFSET, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIicPs_EnableInterrupts, XIICPS_FIFO_DEPTH, XIICPS_IXR_ARB_LOST_MASK, XIICPS_IXR_COMP_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_TO_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.

Referenced by IicPsMasterIntrExample().

s32 XIicPs_MasterSendPolled ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount,
u16  SlaveAddr 
)

This function initiates a polled mode send in master mode.

It sends data to the FIFO and waits for the slave to pick them up. If master fails to send data due arbitration lost, will stop transfer and with arbitration lost status If slave fails to remove data from FIFO, the send fails with time out.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the send buffer.
ByteCountis the number of bytes to be sent.
SlaveAddris the address of the slave we are sending to.
Returns
  • XST_SUCCESS if everything went well.
  • XST_FAILURE if timed out.
  • XST_IIC_ARB_LOST if arbitration lost
Note
This send routine is for polled mode transfer only.

References XIicPs_Config::BaseAddress, SENDING_ROLE, TransmitFifoFill(), XIICPS_ADDR_MASK, XIICPS_ADDR_OFFSET, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIICPS_FIFO_DEPTH, XIICPS_ISR_OFFSET, XIICPS_IXR_ARB_LOST_MASK, XIICPS_IXR_COMP_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_TX_OVR_MASK, XIicPs_ReadReg, XIICPS_SR_OFFSET, XIICPS_SR_TXDV_MASK, and XIicPs_WriteReg.

Referenced by EepromWriteData(), and IicPsMasterPolledExample().

void XIicPs_Reset ( XIicPs InstancePtr)

Resets the IIC device.

Reset must only be called after the driver has been initialized. The configuration of the device after reset is the same as its configuration after initialization. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and reenabling interrupts for the IIC device after the reset.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, XIicPs_Abort(), XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE, and XIicPs_WriteReg.

Referenced by XIicPs_CfgInitialize(), and XIicPs_SelfTest().

void XIicPs_ResetHw ( u32  BaseAddress)

This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specific registers the i2cps reset sequence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values.

Parameters
BaseAddressof the interface
Returns
N/A
Note
This function will not modify the slcr registers that are relevant for I2c controller

References XIICPS_CR_ACKEN_MASK, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_HOLD_MASK, XIICPS_CR_MS_MASK, XIICPS_CR_OFFSET, XIICPS_IDR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, XIICPS_SR_OFFSET, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

s32 XIicPs_SelfTest ( XIicPs InstancePtr)

Runs a self-test on the driver/device.

The self-test is destructive in that a reset of the device is performed in order to check the reset values of the registers and to get the device into a known state.

Upon successful return from the self-test, the device is reset.

Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
  • XST_SUCCESS if successful.
  • XST_REGISTER_ERROR indicates a register did not read or write correctly
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IMR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, XIicPs_Reset(), XIICPS_SLV_PAUSE_OFFSET, and XIicPs_WriteReg.

Referenced by IicPsMasterIntrExample(), IicPsMasterPolledExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

s32 XIicPs_SetOptions ( XIicPs InstancePtr,
u32  Options 
)

This function sets the options for the IIC device driver.

The options control how the device behaves relative to the IIC bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters
InstancePtris a pointer to the XIicPs instance.
Optionscontains the specified options to be set. This is a bit mask where a 1 means to turn the option on. One or more bit values may be contained in the mask. See the bit definitions named XIICPS_*_OPTION in xiicps.h.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_IS_STARTED if the device is currently transferring data. The transfer must complete or be aborted before setting options.
Note
None.

References XIicPs_Config::BaseAddress, XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_OFFSET, XIicPs_GetOptions(), XIicPs_ReadReg, XIICPS_REP_START_OPTION, and XIicPs_WriteReg.

Referenced by EepromReadDataRepStart().

s32 XIicPs_SetSClk ( XIicPs InstancePtr,
u32  FsclHz 
)

This function sets the serial clock rate for the IIC device.

The device must be idle rather than busy transferring data before setting these device options.

The data rate is set by values in the control register. The formula for determining the correct register values is: Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) See the hardware data sheet for a full explanation of setting the serial clock rate.

Parameters
InstancePtris a pointer to the XIicPs instance.
FsclHzis the clock frequency in Hz. The two most common clock rates are 100KHz and 400KHz.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_IS_STARTED if the device is currently transferring data. The transfer must complete or be aborted before setting options.
  • XST_FAILURE if the Fscl frequency can not be set.
Note
The clock can not be faster than the input clock divide by 22.

References XIicPs_Config::BaseAddress, XIicPs_Config::InputClockHz, XIICPS_CR_DIV_A_MASK, XIICPS_CR_DIV_A_SHIFT, XIICPS_CR_DIV_B_MASK, XIICPS_CR_DIV_B_SHIFT, XIICPS_CR_OFFSET, XIicPs_ReadReg, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.

Referenced by IicPsMasterIntrExample(), IicPsMasterPolledExample(), IicPsRepeatedStartExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

void XIicPs_SetStatusHandler ( XIicPs InstancePtr,
void *  CallBackRef,
XIicPs_IntrHandler  FunctionPtr 
)

This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.

The handler executes in an interrupt context, so the amount of processing should be minimized

Refer to the xiicps.h file for a list of the Callback events. The events are defined to start with XIICPS_EVENT_*.

Parameters
InstancePtris a pointer to the XIicPs instance.
CallBackRefis the upper layer callback reference passed back when the callback function is invoked.
FunctionPtris the pointer to the callback function.
Returns
None.
Note

The handler is called within interrupt context, so it should finish its work quickly.

Referenced by IicPsMasterIntrExample(), and IicPsSlaveIntrExample().

void XIicPs_SetupSlave ( XIicPs InstancePtr,
u16  SlaveAddr 
)

This function sets up the device to be a slave.

Parameters
InstancePtris a pointer to the XIicPs instance.
SlaveAddris the address of the slave we are receiving from.
Returns
None.
Note
Interrupt is always enabled no matter the transfer is interrupt- driven or polled mode. Whether device will be interrupted or not depends on whether the device is connected to an interrupt controller and interrupt for the device is enabled.

References XIicPs_Config::BaseAddress, XIICPS_ADDR_MASK, XIICPS_ADDR_OFFSET, XIICPS_CR_ACKEN_MASK, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_MS_MASK, XIICPS_CR_NEA_MASK, XIICPS_CR_OFFSET, XIicPs_DisableAllInterrupts, and XIicPs_WriteReg.

Referenced by IicPsSlaveIntrExample(), and IicPsSlavePolledExample().

void XIicPs_SlaveInterruptHandler ( XIicPs InstancePtr)

The interrupt handler for slave mode.

It does the protocol handling for the interrupt-driven transfers.

Completion events and errors are signaled to upper layer for proper handling.

The interrupts that are handled are:

  • DATA If the instance is sending, it means that the master wants to read more data from us. Send more data, and check whether we are done with this send.

    If the instance is receiving, it means that the master has written more data to us. Receive more data, and check whether we are done with with this receive.

  • COMP This marks that stop sequence has been sent from the master, transfer is about to terminate. However, for receiving, the master may have written us some data, so receive that first.

    It is an error if the amount of transferred data is less than expected.

  • NAK This marks that master does not want our data. It is for send only.
  • Other interrupts These interrupts are marked as error.
Parameters
InstancePtris a pointer to the XIicPs instance.
Returns
None.
Note
None.

References XIicPs_Config::BaseAddress, TransmitFifoFill(), XIICPS_EVENT_COMPLETE_RECV, XIICPS_EVENT_COMPLETE_SEND, XIICPS_EVENT_ERROR, XIICPS_EVENT_NACK, XIICPS_IMR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_RX_UNF_MASK, XIICPS_IXR_TO_MASK, XIICPS_IXR_TX_OVR_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.

void XIicPs_SlaveRecv ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount 
)

This function setup a slave interrupt-driven receive.

Data processing for the receive is handled by the interrupt handler.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the receive buffer.
ByteCountis the number of bytes to be received.
Returns
None.
Note
This routine is for interrupt-driven transfer only.

References XIicPs_Config::BaseAddress, XIicPs_EnableInterrupts, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_RX_UNF_MASK, and XIICPS_IXR_TO_MASK.

Referenced by IicPsSlaveIntrExample().

s32 XIicPs_SlaveRecvPolled ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount 
)

This function receives a buffer in polled mode as a slave.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the receive buffer.
ByteCountis the number of bytes to be received.
Returns
  • XST_SUCCESS if everything went well.
  • XST_FAILURE if timed out.
Note
This receive routine is for polled mode transfer only.

References XIicPs_Config::BaseAddress, XIICPS_ISR_OFFSET, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIicPs_ReadReg, XIicPs_RecvByte, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, and XIicPs_WriteReg.

Referenced by IicPsSlavePolledExample().

void XIicPs_SlaveSend ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount 
)

This function setup a slave interrupt-driven send.

It set the repeated start for the device is the transfer size is larger than FIFO depth. Data processing for the send is initiated by the interrupt handler.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the send buffer.
ByteCountis the number of bytes to be sent.
Returns
None.
Note
This send routine is for interrupt-driven transfer only.

References XIicPs_Config::BaseAddress, XIicPs_EnableInterrupts, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_TO_MASK, and XIICPS_IXR_TX_OVR_MASK.

Referenced by IicPsSlaveIntrExample().

s32 XIicPs_SlaveSendPolled ( XIicPs InstancePtr,
u8 *  MsgPtr,
s32  ByteCount 
)

This function sends a buffer in polled mode as a slave.

Parameters
InstancePtris a pointer to the XIicPs instance.
MsgPtris the pointer to the send buffer.
ByteCountis the number of bytes to be sent.
Returns
  • XST_SUCCESS if everything went well.
  • XST_FAILURE if master sends us data or master terminates the transfer before all data has sent out.
Note
This send routine is for polled mode transfer only.

References XIicPs_Config::BaseAddress, XIICPS_FIFO_DEPTH, XIICPS_ISR_OFFSET, XIICPS_IXR_COMP_MASK, XIICPS_IXR_NACK_MASK, XIICPS_POLL_DEFAULT_TIMEOUT_VAL, XIicPs_ReadReg, XIicPs_SendByte, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, XIICPS_SR_RXRW_MASK, XIICPS_SR_TXDV_MASK, and XIicPs_WriteReg.

Referenced by IicPsSlavePolledExample().

Variable Documentation

u16 XIicPs_Config::DeviceId

Unique ID of device.

Referenced by XIicPs_CfgInitialize().

u32 XIicPs_Config::InputClockHz

Input clock frequency.

Referenced by XIicPs_CfgInitialize(), XIicPs_GetSClk(), and XIicPs_SetSClk().

XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES]

This table contains configuration information for each IIC device in the system.

XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES]
Initial value:
= {
{
(u16)XPAR_XIICPS_0_DEVICE_ID,
(u32)XPAR_XIICPS_0_BASEADDR,
(u32)XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
},
}

This table contains configuration information for each IIC device in the system.