v_hdmiphy1
Xilinx SDK Drivers API Documentation
xhdmiphy1_hdmi.c File Reference

Overview

This file contains video PHY functionality specific to the HDMI protocol.

Note
None.
MODIFICATION HISTORY:
Ver   Who  Date     Changes


dd/mm/yy


1.0 gm 10/12/18 Initial release.

Functions

void XHdmiphy1_Ch2Ids (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 *Id0, u8 *Id1)
 This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More...
 
u32 XHdmiphy1_Hdmi_CfgInitialize (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_Config *CfgPtr)
 This function initializes the Video PHY for HDMI. More...
 
void XHdmiphy1_HdmiUpdateClockSelection (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_SysClkDataSelType TxSysPllClkSel, XHdmiphy1_SysClkDataSelType RxSysPllClkSel)
 This function Updates the HDMIPHY clocking. More...
 
void XHdmiphy1_TxAlignReset (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Reset)
 This function resets the GT TX alignment module. More...
 
void XHdmiphy1_TxAlignStart (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Start)
 This function resets the GT TX alignment module. More...
 
void XHdmiphy1_ClkDetEnable (XHdmiphy1 *InstancePtr, u8 Enable)
 This function enables the HDMIPHY's detector peripheral. More...
 
void XHdmiphy1_ClkDetTimerClear (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)
 This function clears the clock detector TX/RX timer. More...
 
void XHdmiphy1_ClkDetFreqReset (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)
 This function resets clock detector TX/RX frequency. More...
 
void XHdmiphy1_ClkDetSetFreqLockThreshold (XHdmiphy1 *InstancePtr, u16 ThresholdVal)
 This function sets the clock detector frequency lock counter threshold value. More...
 
u8 XHdmiphy1_ClkDetCheckFreqZero (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir)
 This function checks clock detector RX/TX frequency zero indicator bit. More...
 
void XHdmiphy1_ClkDetSetFreqTimeout (XHdmiphy1 *InstancePtr, u32 TimeoutVal)
 This function sets clock detector frequency lock counter threshold value. More...
 
void XHdmiphy1_ClkDetTimerLoad (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u32 TimeoutVal)
 This function loads the timer to TX/RX in the clock detector. More...
 
u32 XHdmiphy1_ClkDetGetRefClkFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir)
 This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral. More...
 
u32 XHdmiphy1_DruGetRefClkFreqHz (XHdmiphy1 *InstancePtr)
 This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral. More...
 
void XHdmiphy1_DruReset (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Reset)
 This function resets the DRU in the HDMIPHY. More...
 
void XHdmiphy1_DruEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Enable)
 This function enabled/disables the DRU in the HDMIPHY. More...
 
u16 XHdmiphy1_DruGetVersion (XHdmiphy1 *InstancePtr)
 This function gets the DRU version. More...
 
void XHdmiphy1_DruSetCenterFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u64 CenterFreqHz)
 This function sets the DRU center frequency. More...
 
u64 XHdmiphy1_DruCalcCenterFreqHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId)
 This function calculates the center frequency value for the DRU. More...
 
void XHdmiphy1_HdmiGtDruModeEnable (XHdmiphy1 *InstancePtr, u8 Enable)
 This function sets the GT RX CDR and Equalization for DRU mode. More...
 
u32 XHdmiphy1_HdmiCfgCalcMmcmParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc)
 This function calculates the HDMI MMCM parameters. More...
 
u32 XHdmiphy1_HdmiQpllParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
 This function calculates the QPLL parameters. More...
 
u32 XHdmiphy1_HdmiCpllParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
 This function calculates the CPLL parameters. More...
 
u32 XHdmiphy1_SetHdmiTxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc, XVidC_ColorFormat ColorFormat)
 This function update/set the HDMI TX parameter. More...
 
u32 XHdmiphy1_SetHdmiRxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId)
 This function update/set the HDMI RX parameter. More...
 
void XHdmiphy1_PatgenEnable (XHdmiphy1 *InstancePtr, u8 QuadId, u8 Enable)
 This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock. More...
 
void XHdmiphy1_PatgenSetRatio (XHdmiphy1 *InstancePtr, u8 QuadId, u64 TxLineRate)
 This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock. More...
 
u32 XHdmiphy1_Hdmi20Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir)
 This function will configure the HDMIPHY to HDMI 2.0 mode. More...
 
u32 XHdmiphy1_Hdmi21Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels)
 This function will configure the GT for HDMI 2.1 operation. More...
 
void XHdmiphy1_HdmiDebugInfo (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId)
 This function prints Video PHY debug information related to HDMI. More...
 

Function Documentation

void XHdmiphy1_Ch2Ids ( XHdmiphy1 InstancePtr,
XHdmiphy1_ChannelId  ChId,
u8 *  Id0,
u8 *  Id1 
)
u32 XHdmiphy1_HdmiCpllParam ( XHdmiphy1 InstancePtr,
u8  QuadId,
XHdmiphy1_ChannelId  ChId,
XHdmiphy1_DirectionType  Dir 
)
void XHdmiphy1_TxAlignReset ( XHdmiphy1 InstancePtr,
XHdmiphy1_ChannelId  ChId,
u8  Reset 
)

This function resets the GT TX alignment module.

Parameters
InstancePtris a pointer to the XHdmiphy1 core instance.
ChIdis the channel ID to operate on.
Resetspecifies TRUE/FALSE value to either assert or deassert reset on the TX alignment module, respectively.
Returns
None.
Note
None.

References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.

Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler().

void XHdmiphy1_TxAlignStart ( XHdmiphy1 InstancePtr,
XHdmiphy1_ChannelId  ChId,
u8  Start 
)

This function resets the GT TX alignment module.

Parameters
InstancePtris a pointer to the XHdmiphy1 core instance.
ChIdis the channel ID to operate on.
Startspecifies TRUE/FALSE value to either start or ttop the TX alignment module, respectively.
Returns
None.
Note
None.

References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.

Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().