clk_wiz
Xilinx SDK Drivers API Documentation
Clk_wiz_v1_2

Data Structures

struct  XClk_Wiz_Config
 The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver. More...
 
struct  XClk_Wiz
 The XClk_Wiz driver instance data. More...
 

Macros

#define XCLK_WIZ_IER_ALLINTR_MASK   0x0000FFFF
 All interrupts enable mask. More...
 
#define XCLK_WIZ_IER_ALLINTR_SHIFT   0
 All interrupts enable shift bits. More...
 
#define XCLK_WIZ_ISR_ALLINTR_MASK   0x0000FFFF
 All interrupt status register mask. More...
 
#define XCLK_WIZ_ISR_ALLINTR_SHIFT   0
 All interrupts status register shift. More...
 

Typedefs

typedef void(* XClk_Wiz_CallBack )(void *CallBackRef, u32 Mask)
 Callback type for all interrupts defined. More...
 

Functions

u32 XClk_Wiz_CfgInitialize (XClk_Wiz *InstancePtr, XClk_Wiz_Config *CfgPtr, UINTPTR EffectiveAddr)
 Initialize the XClk_Wiz instance provided by the caller based on the given Config structure. More...
 
void XClk_Wiz_GetInterruptSettings (XClk_Wiz *InstancePtr)
 XClk_Wiz_GetInterruptSettings will get the information from clock wizard IER and ISR Registers. More...
 
XClk_Wiz_ConfigXClk_Wiz_LookupConfig (u32 DeviceId)
 Look up the hardware configuration for a device instance. More...
 
int XClk_Wiz_SetCallBack (XClk_Wiz *InstancePtr, u32 HandleType, void *CallBackFunc, void *CallBackRef)
 This routine installs an asynchronous callback function for the given HandlerType: More...
 
void XClk_Wiz_InterruptEnable (XClk_Wiz *InstancePtr, u32 Mask)
 XClk_Wiz_InterruptEnable will enable the interrupts present in the interrupt mask passed onto the function. More...
 
void XClk_Wiz_InterruptDisable (XClk_Wiz *InstancePtr, u32 Mask)
 XClk_Wiz_InterruptDisable will disable the interrupts present in the interrupt mask passed onto the function. More...
 
u32 XClk_Wiz_InterruptGetEnabled (XClk_Wiz *InstancePtr)
 XClk_Wiz_InterruptGetEnabled will get the interrupt mask set (enabled) in the CLK_WIZ core. More...
 
u32 XClk_Wiz_InterruptGetStatus (XClk_Wiz *InstancePtr)
 XClk_Wiz_InterruptGetStatus will get the list of interrupts pending in the Interrupt Status Register of the CLK_WIZ core. More...
 
void XClk_Wiz_InterruptClear (XClk_Wiz *InstancePtr, u32 Mask)
 XClk_Wiz_InterruptClear will clear the interrupts set in the Interrupt Status Register of the CLK_WIZ core. More...
 
void XClk_Wiz_IntrHandler (void *InstancePtr)
 This function is the interrupt handler for the CLK_WIZ core. More...
 

Interrupt Types for setting Callbacks

#define XCLK_WIZ_HANDLER_CLK_OUTOF_RANGE   1
 
#define XCLK_WIZ_HANDLER_CLK_GLITCH   2
 
#define XCLK_WIZ_HANDLER_CLK_STOP   3
 
#define XCLK_WIZ_HANDLER_CLK_OTHER_ERROR   4
 

Device registers

Register sets of CLK_WIZ

#define XCLK_WIZ_ISR_OFFSET   0x0000000C
 Interrupt Status Register. More...
 
#define XCLK_WIZ_IER_OFFSET   0x00000010
 Interrupt Enable Register. More...
 

Bitmasks and offsets of XCLK_WIZ_ISR_OFFSET register

This register is used to display interrupt status register

#define XCLK_WIZ_ISR_CLK3_STOP_MASK   0x00008000
 User clock 3 stopped. More...
 
#define XCLK_WIZ_ISR_CLK2_STOP_MASK   0x00004000
 User clock 2 stopped. More...
 
#define XCLK_WIZ_ISR_CLK1_STOP_MASK   0x00002000
 User clock 1 stopped. More...
 
#define XCLK_WIZ_ISR_CLK0_STOP_MASK   0x00001000
 User clock 0 stopped. More...
 
#define XCLK_WIZ_ISR_CLK3_GLITCH_MASK   0x00000800
 User clock 3 has glitch. More...
 
#define XCLK_WIZ_ISR_CLK2_GLITCH_MASK   0x00000400
 User clock 2 has glitch. More...
 
#define XCLK_WIZ_ISR_CLK1_GLITCH_MASK   0x00000200
 User clock 1 has glitch. More...
 
#define XCLK_WIZ_ISR_CLK0_GLITCH_MASK   0x00000100
 User clock 0 has glitch. More...
 
#define XCLK_WIZ_ISR_CLK3_MINFREQ_MASK   0x00000080
 User clock 3 is less than specification. More...
 
#define XCLK_WIZ_ISR_CLK2_MINFREQ_MASK   0x00000040
 User clock 2 is less than specification. More...
 
#define XCLK_WIZ_ISR_CLK1_MINFREQ_MASK   0x00000020
 User clock 1 is less than specification. More...
 
#define XCLK_WIZ_ISR_CLK0_MINFREQ_MASK   0x00000010
 User clock 0 is less than specification. More...
 
#define XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK   0x00000008
 User clock 3 is max than specification. More...
 
#define XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK   0x00000004
 User clock 2 is max than specification. More...
 
#define XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK   0x00000002
 User clock 1 is max than specification. More...
 
#define XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK   0x00000001
 User clock 0 is max than specification. More...
 
#define XCLK_WIZ_ISR_CLKALL_STOP_MASK   0x0000F000
 User clock[0-3] has stopped. More...
 
#define XCLK_WIZ_ISR_CLKALL_GLITCH_MASK   0x00000F00
 User clock[0-3] has glitch. More...
 
#define XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK   0x000000F0
 User clock[0-3] is min than specification. More...
 
#define XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK   0x0000000F
 User clock[0-3] is max than specification. More...
 
#define XCLK_WIZ_ISR_CLK3_STOP_SHIFT   15
 Shift bits for User clock 3 stop. More...
 
#define XCLK_WIZ_ISR_CLK2_STOP_SHIFT   14
 Shift bits for User clock 2 stop. More...
 
#define XCLK_WIZ_ISR_CLK1_STOP_SHIFT   13
 Shift bits for User clock 1 stop. More...
 
#define XCLK_WIZ_ISR_CLK0_STOP_SHIFT   12
 Shift bits for User clock 0 stop. More...
 
#define XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT   11
 Shift bits for User clock 3 glitch. More...
 
#define XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT   10
 Shift bits for User clock 2 glitch. More...
 
#define XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT   9
 Shift bits for User clock 1 glitch. More...
 
#define XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT   8
 Shift bits for User clock 0 glitch. More...
 
#define XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT   7
 Shift bits for User clock 3 less. More...
 
#define XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT   6
 Shift bits for User clock 2 less. More...
 
#define XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT   5
 Shift bits for User clock 1 less. More...
 
#define XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT   4
 Shift bits for User clock 0 less. More...
 
#define XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT   3
 Shift bits for User clock 3 max. More...
 
#define XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT   2
 Shift bits for User clock 2 max. More...
 
#define XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT   1
 Shift bits for User clock 1 max. More...
 
#define XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT   0
 Shift bits for User clock 0 max. More...
 

Bitmasks and offsets of XCLK_WIZ_IER_OFFSET register

This register is used to display interrupt status register

#define XCLK_WIZ_IER_CLK3_STOP_MASK   0x00008000
 User clock 3 stopped. More...
 
#define XCLK_WIZ_IER_CLK2_STOP_MASK   0x00004000
 User clock 2 stopped. More...
 
#define XCLK_WIZ_IER_CLK1_STOP_MASK   0x00002000
 User clock 1 stopped. More...
 
#define XCLK_WIZ_IER_CLK0_STOP_MASK   0x00001000
 User clock 0 stopped. More...
 
#define XCLK_WIZ_IER_CLK3_GLITCH_MASK   0x00000800
 User clock 3 has glitch. More...
 
#define XCLK_WIZ_IER_CLK2_GLITCH_MASK   0x00000400
 User clock 2 has glitch. More...
 
#define XCLK_WIZ_IER_CLK1_GLITCH_MASK   0x00000200
 User clock 1 has glitch. More...
 
#define XCLK_WIZ_IER_CLK0_GLITCH_MASK   0x00000100
 User clock 0 has glitch. More...
 
#define XCLK_WIZ_IER_CLK3_MINFREQ_MASK   0x00000080
 User clock 3 is less than specification. More...
 
#define XCLK_WIZ_IER_CLK2_MINFREQ_MASK   0x00000040
 User clock 2 is less than specification. More...
 
#define XCLK_WIZ_IER_CLK1_MINFREQ_MASK   0x00000020
 User clock 1 is less than specification. More...
 
#define XCLK_WIZ_IER_CLK0_MINFREQ_MASK   0x00000010
 User clock 0 is less than specification. More...
 
#define XCLK_WIZ_IER_CLK3_MAXFREQ_MASK   0x00000008
 User clock 3 is max than specification. More...
 
#define XCLK_WIZ_IER_CLK2_MAXFREQ_MASK   0x00000004
 User clock 2 is max than specification. More...
 
#define XCLK_WIZ_IER_CLK1_MAXFREQ_MASK   0x00000002
 User clock 1 is max than specification. More...
 
#define XCLK_WIZ_IER_CLK0_MAXFREQ_MASK   0x00000001
 User clock 0 is max than specification. More...
 
#define XCLK_WIZ_IER_CLK3_STOP_SHIFT   15
 Shift bits for User clock 3 stop. More...
 
#define XCLK_WIZ_IER_CLK2_STOP_SHIFT   14
 Shift bits for User clock 2 stop. More...
 
#define XCLK_WIZ_IER_CLK1_STOP_SHIFT   13
 Shift bits for User clock 1 stop. More...
 
#define XCLK_WIZ_IER_CLK0_STOP_SHIFT   12
 Shift bits for User clock 0 stop. More...
 
#define XCLK_WIZ_IER_CLK3_GLITCH_SHIFT   11
 Shift bits for User clock 3 glitch. More...
 
#define XCLK_WIZ_IER_CLK2_GLITCH_SHIFT   10
 Shift bits for User clock 2 glitch. More...
 
#define XCLK_WIZ_IER_CLK1_GLITCH_SHIFT   9
 Shift bits for User clock 1 glitch. More...
 
#define XCLK_WIZ_IER_CLK0_GLITCH_SHIFT   8
 Shift bits for User clock 0 glitch. More...
 
#define XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT   7
 Shift bits for User clock 3 less. More...
 
#define XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT   6
 Shift bits for User clock 2 less. More...
 
#define XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT   5
 Shift bits for User clock 1 less. More...
 
#define XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT   4
 Shift bits for User clock 0 less. More...
 
#define XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT   3
 Shift bits for User clock 3 max. More...
 
#define XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT   2
 Shift bits for User clock 2 max. More...
 
#define XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT   1
 Shift bits for User clock 1 max. More...
 
#define XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT   0
 Shift bits for User clock 0 max. More...
 

Macro Definition Documentation

#define XCLK_WIZ_IER_ALLINTR_MASK   0x0000FFFF
#define XCLK_WIZ_IER_ALLINTR_SHIFT   0

All interrupts enable shift bits.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_IER_CLK0_GLITCH_MASK   0x00000100

User clock 0 has glitch.

#define XCLK_WIZ_IER_CLK0_GLITCH_SHIFT   8

Shift bits for User clock 0 glitch.

#define XCLK_WIZ_IER_CLK0_MAXFREQ_MASK   0x00000001

User clock 0 is max than specification.

#define XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT   0

Shift bits for User clock 0 max.

#define XCLK_WIZ_IER_CLK0_MINFREQ_MASK   0x00000010

User clock 0 is less than specification.

#define XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT   4

Shift bits for User clock 0 less.

#define XCLK_WIZ_IER_CLK0_STOP_MASK   0x00001000

User clock 0 stopped.

#define XCLK_WIZ_IER_CLK0_STOP_SHIFT   12

Shift bits for User clock 0 stop.

#define XCLK_WIZ_IER_CLK1_GLITCH_MASK   0x00000200

User clock 1 has glitch.

#define XCLK_WIZ_IER_CLK1_GLITCH_SHIFT   9

Shift bits for User clock 1 glitch.

#define XCLK_WIZ_IER_CLK1_MAXFREQ_MASK   0x00000002

User clock 1 is max than specification.

#define XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT   1

Shift bits for User clock 1 max.

#define XCLK_WIZ_IER_CLK1_MINFREQ_MASK   0x00000020

User clock 1 is less than specification.

#define XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT   5

Shift bits for User clock 1 less.

#define XCLK_WIZ_IER_CLK1_STOP_MASK   0x00002000

User clock 1 stopped.

#define XCLK_WIZ_IER_CLK1_STOP_SHIFT   13

Shift bits for User clock 1 stop.

#define XCLK_WIZ_IER_CLK2_GLITCH_MASK   0x00000400

User clock 2 has glitch.

#define XCLK_WIZ_IER_CLK2_GLITCH_SHIFT   10

Shift bits for User clock 2 glitch.

#define XCLK_WIZ_IER_CLK2_MAXFREQ_MASK   0x00000004

User clock 2 is max than specification.

#define XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT   2

Shift bits for User clock 2 max.

#define XCLK_WIZ_IER_CLK2_MINFREQ_MASK   0x00000040

User clock 2 is less than specification.

#define XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT   6

Shift bits for User clock 2 less.

#define XCLK_WIZ_IER_CLK2_STOP_MASK   0x00004000

User clock 2 stopped.

#define XCLK_WIZ_IER_CLK2_STOP_SHIFT   14

Shift bits for User clock 2 stop.

#define XCLK_WIZ_IER_CLK3_GLITCH_MASK   0x00000800

User clock 3 has glitch.

#define XCLK_WIZ_IER_CLK3_GLITCH_SHIFT   11

Shift bits for User clock 3 glitch.

#define XCLK_WIZ_IER_CLK3_MAXFREQ_MASK   0x00000008

User clock 3 is max than specification.

#define XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT   3

Shift bits for User clock 3 max.

#define XCLK_WIZ_IER_CLK3_MINFREQ_MASK   0x00000080

User clock 3 is less than specification.

#define XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT   7

Shift bits for User clock 3 less.

#define XCLK_WIZ_IER_CLK3_STOP_MASK   0x00008000

User clock 3 stopped.

#define XCLK_WIZ_IER_CLK3_STOP_SHIFT   15

Shift bits for User clock 3 stop.

#define XCLK_WIZ_IER_OFFSET   0x00000010

Interrupt Enable Register.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_ALLINTR_MASK   0x0000FFFF

All interrupt status register mask.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_ALLINTR_SHIFT   0

All interrupts status register shift.

Referenced by XClk_Wiz_GetInterruptSettings().

#define XCLK_WIZ_ISR_CLK0_GLITCH_MASK   0x00000100

User clock 0 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT   8

Shift bits for User clock 0 glitch.

#define XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK   0x00000001

User clock 0 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT   0

Shift bits for User clock 0 max.

#define XCLK_WIZ_ISR_CLK0_MINFREQ_MASK   0x00000010

User clock 0 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT   4

Shift bits for User clock 0 less.

#define XCLK_WIZ_ISR_CLK0_STOP_MASK   0x00001000

User clock 0 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK0_STOP_SHIFT   12

Shift bits for User clock 0 stop.

#define XCLK_WIZ_ISR_CLK1_GLITCH_MASK   0x00000200

User clock 1 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT   9

Shift bits for User clock 1 glitch.

#define XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK   0x00000002

User clock 1 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT   1

Shift bits for User clock 1 max.

#define XCLK_WIZ_ISR_CLK1_MINFREQ_MASK   0x00000020

User clock 1 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT   5

Shift bits for User clock 1 less.

#define XCLK_WIZ_ISR_CLK1_STOP_MASK   0x00002000

User clock 1 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK1_STOP_SHIFT   13

Shift bits for User clock 1 stop.

#define XCLK_WIZ_ISR_CLK2_GLITCH_MASK   0x00000400

User clock 2 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT   10

Shift bits for User clock 2 glitch.

#define XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK   0x00000004

User clock 2 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT   2

Shift bits for User clock 2 max.

#define XCLK_WIZ_ISR_CLK2_MINFREQ_MASK   0x00000040

User clock 2 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT   6

Shift bits for User clock 2 less.

#define XCLK_WIZ_ISR_CLK2_STOP_MASK   0x00004000

User clock 2 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK2_STOP_SHIFT   14

Shift bits for User clock 2 stop.

#define XCLK_WIZ_ISR_CLK3_GLITCH_MASK   0x00000800

User clock 3 has glitch.

Referenced by ClkWiz_ClkGlitchEventHandler().

#define XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT   11

Shift bits for User clock 3 glitch.

#define XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK   0x00000008

User clock 3 is max than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT   3

Shift bits for User clock 3 max.

#define XCLK_WIZ_ISR_CLK3_MINFREQ_MASK   0x00000080

User clock 3 is less than specification.

Referenced by ClkWiz_ClkOutOfRangeEventHandler().

#define XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT   7

Shift bits for User clock 3 less.

#define XCLK_WIZ_ISR_CLK3_STOP_MASK   0x00008000

User clock 3 stopped.

Referenced by ClkWiz_ClkStopEventHandler().

#define XCLK_WIZ_ISR_CLK3_STOP_SHIFT   15

Shift bits for User clock 3 stop.

#define XCLK_WIZ_ISR_CLKALL_GLITCH_MASK   0x00000F00

User clock[0-3] has glitch.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK   0x0000000F

User clock[0-3] is max than specification.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK   0x000000F0

User clock[0-3] is min than specification.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_CLKALL_STOP_MASK   0x0000F000

User clock[0-3] has stopped.

Referenced by XClk_Wiz_IntrHandler().

#define XCLK_WIZ_ISR_OFFSET   0x0000000C

Interrupt Status Register.

Referenced by XClk_Wiz_GetInterruptSettings().

Typedef Documentation

typedef void(* XClk_Wiz_CallBack)(void *CallBackRef, u32 Mask)

Callback type for all interrupts defined.

Parameters
CallBackRefis a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.
Maskis a bit mask indicating the cause of the event. For current core version, this parameter is "OR" of 0 or more XCLK_WIZ_ISR_*_MASK constants defined in xclmon_hw.h.
Returns
None
Note
None

Function Documentation

u32 XClk_Wiz_CfgInitialize ( XClk_Wiz InstancePtr,
XClk_Wiz_Config CfgPtr,
UINTPTR  EffectiveAddr 
)

Initialize the XClk_Wiz instance provided by the caller based on the given Config structure.

Parameters
InstancePtris the XClk_Wiz instance to operate on.
CfgPtris the device configuration structure containing information about a specific CLK_WIZ.
EffectiveAddris the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.
Returns
  • XST_SUCCESS Initialization was successful.
  • XST_FAILURE Initialization was failure.
Note
None

References XClk_Wiz_Config::BaseAddr, XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkStopCallBack, XClk_Wiz::Config, XClk_Wiz::ErrorCallBack, and XClk_Wiz::IsReady.

Referenced by ClkWiz_IntrExample().

void XClk_Wiz_GetInterruptSettings ( XClk_Wiz InstancePtr)

XClk_Wiz_GetInterruptSettings will get the information from clock wizard IER and ISR Registers.

Parameters
InstancePtris the XClk_Wiz instance to operate on.
Returns
None

References XClk_Wiz::ClkIntrEnable, XClk_Wiz::ClkWizIntrStatus, XCLK_WIZ_IER_ALLINTR_MASK, XCLK_WIZ_IER_ALLINTR_SHIFT, XCLK_WIZ_IER_OFFSET, XCLK_WIZ_ISR_ALLINTR_MASK, XCLK_WIZ_ISR_ALLINTR_SHIFT, and XCLK_WIZ_ISR_OFFSET.

void XClk_Wiz_InterruptClear ( XClk_Wiz InstancePtr,
u32  Mask 
)

XClk_Wiz_InterruptClear will clear the interrupts set in the Interrupt Status Register of the CLK_WIZ core.

Parameters
InstancePtris the XClk_Wiz instance to operate on
Maskis Interrupt Mask with bits set for corresponding interrupt to be cleared in the Interrupt Status register
Returns
None
Note
None

References XCLK_WIZ_IER_ALLINTR_MASK.

Referenced by XClk_Wiz_IntrHandler().

void XClk_Wiz_InterruptDisable ( XClk_Wiz InstancePtr,
u32  Mask 
)

XClk_Wiz_InterruptDisable will disable the interrupts present in the interrupt mask passed onto the function.

Parameters
InstancePtris the XClk_Wiz instance to operate on
Maskis the interrupt mask which need to be enabled in core
Returns
None
Note
None

References XCLK_WIZ_IER_ALLINTR_MASK.

void XClk_Wiz_InterruptEnable ( XClk_Wiz InstancePtr,
u32  Mask 
)

XClk_Wiz_InterruptEnable will enable the interrupts present in the interrupt mask passed onto the function.

Parameters
InstancePtris the XClk_Wiz instance to operate on
Maskis the interrupt mask which need to be enabled in core
Returns
None
Note
None

References XCLK_WIZ_IER_ALLINTR_MASK.

Referenced by ClkWiz_IntrExample().

u32 XClk_Wiz_InterruptGetEnabled ( XClk_Wiz InstancePtr)

XClk_Wiz_InterruptGetEnabled will get the interrupt mask set (enabled) in the CLK_WIZ core.

Parameters
InstancePtris the XClk_Wiz instance to operate on
Returns
Interrupt Mask with bits set for corresponding interrupt in Interrupt enable register
Note
None
u32 XClk_Wiz_InterruptGetStatus ( XClk_Wiz InstancePtr)

XClk_Wiz_InterruptGetStatus will get the list of interrupts pending in the Interrupt Status Register of the CLK_WIZ core.

Parameters
InstancePtris the XClk_Wiz instance to operate on
Returns
Interrupt Mask with bits set for corresponding interrupt in Interrupt Status register
Note
None

Referenced by XClk_Wiz_IntrHandler().

void XClk_Wiz_IntrHandler ( void *  InstancePtr)

This function is the interrupt handler for the CLK_WIZ core.

This handler reads the pending interrupt from the Interrupt Status register determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in Interrupt Enable register and finally clears the interrupts.

The application is responsible for connecting this function to the interrupt system. Application beyond this core is also responsible for providing callbacks to handle interrupts and installing the callbacks using XClk_Wiz_SetCallBack() during initialization phase.

Parameters
InstancePtris a pointer to the XClk_Wiz core instance.
Returns
None
Note
Interrupt should be enabled to execute interrupt handler.

References XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkGlitchRef, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkOutOfRangeRef, XClk_Wiz::ClkStopCallBack, XClk_Wiz::ClkStopRef, XClk_Wiz::IsReady, XClk_Wiz_InterruptClear(), XClk_Wiz_InterruptGetStatus(), XCLK_WIZ_ISR_CLKALL_GLITCH_MASK, XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK, XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK, and XCLK_WIZ_ISR_CLKALL_STOP_MASK.

Referenced by SetupInterruptSystem().

XClk_Wiz_Config * XClk_Wiz_LookupConfig ( u32  DeviceId)

Look up the hardware configuration for a device instance.

Parameters
DeviceIdis the unique device ID of the device to lookup for
Returns
The reference to the configuration record in the configuration table (in xclk_wiz_g.c) corresponding to the Device ID or if not found, a NULL pointer is returned.
Note
None

Referenced by ClkWiz_IntrExample().

int XClk_Wiz_SetCallBack ( XClk_Wiz InstancePtr,
u32  HandleType,
void *  CallBackFunc,
void *  CallBackRef 
)

This routine installs an asynchronous callback function for the given HandlerType:

HandlerType                             Invoked by this driver when:
-----------------------  --------------------------------------------------
XCLK_WIZ_HANDLER_CLK_OUTOF_RANGE        Clock under flow/over flow
XCLK_WIZ_HANDLER_CLK_GLITCH             Clock Glitch
XCLK_WIZ_HANDLER_CLK_STOP               Clock Stop
XCLK_WIZ_HANDLER_OTHERERROR             Any other type of interrupts
Parameters
InstancePtris the XClk_Wiz instance to operate on
HandleTypeis the type of call back to be registered.
CallBackFuncis the pointer to a call back funtion which is called when a particular event occurs.
CallBackRefis a void pointer to data to be referenced to by the CallBackFunc
Returns
  • XST_SUCCESS when handler is installed.
  • XST_INVALID_PARAM when HandlerType is invalid.
Note
Invoking this function for a handler that already has been installed replaces it with the new handler.

References XClk_Wiz::ClkGlitchCallBack, XClk_Wiz::ClkGlitchRef, XClk_Wiz::ClkOutOfRangeCallBack, XClk_Wiz::ClkOutOfRangeRef, XClk_Wiz::ClkStopCallBack, XClk_Wiz::ClkStopRef, XClk_Wiz::ErrorCallBack, XClk_Wiz::ErrRef, and XClk_Wiz::IsReady.

Referenced by SetupInterruptSystem().