aiengine
Xilinx SDK Drivers API Documentation
XAieGbl_RegStrmSlv Struct Reference

This typedef contains the attributes for Stream switch slave port config register. More...

Data Fields

u32 RegOff
 Register offset. More...
 
XAieGbl_RegFldAttr SlvEn
 Enable bit field attributes. More...
 
XAieGbl_RegFldAttr PktEn
 Packet enable bit field attributes. More...
 

Detailed Description

This typedef contains the attributes for Stream switch slave port config register.

Field Documentation

XAieGbl_RegFldAttr XAieGbl_RegStrmSlv::PktEn

Packet enable bit field attributes.

Referenced by XAieTile_StrmConfigSlv().

u32 XAieGbl_RegStrmSlv::RegOff

Register offset.

Referenced by XAieTile_StrmConfigSlv().

XAieGbl_RegFldAttr XAieGbl_RegStrmSlv::SlvEn

Enable bit field attributes.

Referenced by XAieTile_StrmConfigSlv().