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v_hdmiphy1
Xilinx SDK Drivers API Documentation
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This file contains video PHY functionality specific to the HDMI protocol.
MODIFICATION HISTORY:
Ver Who Date Changes
dd/mm/yy
1.0 gm 10/12/18 Initial release.
Functions | |
void | XHdmiphy1_Ch2Ids (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 *Id0, u8 *Id1) |
This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More... | |
u32 | XHdmiphy1_Hdmi_CfgInitialize (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_Config *CfgPtr) |
This function initializes the Video PHY for HDMI. More... | |
void | XHdmiphy1_HdmiUpdateClockSelection (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_SysClkDataSelType TxSysPllClkSel, XHdmiphy1_SysClkDataSelType RxSysPllClkSel) |
This function Updates the HDMIPHY clocking. More... | |
void | XHdmiphy1_TxAlignReset (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Reset) |
This function resets the GT TX alignment module. More... | |
void | XHdmiphy1_TxAlignStart (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Start) |
This function resets the GT TX alignment module. More... | |
void | XHdmiphy1_ClkDetEnable (XHdmiphy1 *InstancePtr, u8 Enable) |
This function enables the HDMIPHY's detector peripheral. More... | |
void | XHdmiphy1_ClkDetTimerClear (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function clears the clock detector TX/RX timer. More... | |
void | XHdmiphy1_ClkDetFreqReset (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function resets clock detector TX/RX frequency. More... | |
void | XHdmiphy1_ClkDetSetFreqLockThreshold (XHdmiphy1 *InstancePtr, u16 ThresholdVal) |
This function sets the clock detector frequency lock counter threshold value. More... | |
u8 | XHdmiphy1_ClkDetCheckFreqZero (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function checks clock detector RX/TX frequency zero indicator bit. More... | |
void | XHdmiphy1_ClkDetSetFreqTimeout (XHdmiphy1 *InstancePtr, u32 TimeoutVal) |
This function sets clock detector frequency lock counter threshold value. More... | |
void | XHdmiphy1_ClkDetTimerLoad (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u32 TimeoutVal) |
This function loads the timer to TX/RX in the clock detector. More... | |
u32 | XHdmiphy1_ClkDetGetRefClkFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral. More... | |
u32 | XHdmiphy1_DruGetRefClkFreqHz (XHdmiphy1 *InstancePtr) |
This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral. More... | |
void | XHdmiphy1_DruReset (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Reset) |
This function resets the DRU in the HDMIPHY. More... | |
void | XHdmiphy1_DruEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Enable) |
This function enabled/disables the DRU in the HDMIPHY. More... | |
u16 | XHdmiphy1_DruGetVersion (XHdmiphy1 *InstancePtr) |
This function gets the DRU version. More... | |
void | XHdmiphy1_DruSetCenterFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u64 CenterFreqHz) |
This function sets the DRU center frequency. More... | |
u64 | XHdmiphy1_DruCalcCenterFreqHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function calculates the center frequency value for the DRU. More... | |
void | XHdmiphy1_HdmiGtDruModeEnable (XHdmiphy1 *InstancePtr, u8 Enable) |
This function sets the GT RX CDR and Equalization for DRU mode. More... | |
u32 | XHdmiphy1_HdmiCfgCalcMmcmParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc) |
This function calculates the HDMI MMCM parameters. More... | |
u32 | XHdmiphy1_HdmiQpllParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function calculates the QPLL parameters. More... | |
u32 | XHdmiphy1_HdmiCpllParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function calculates the CPLL parameters. More... | |
u32 | XHdmiphy1_SetHdmiTxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc, XVidC_ColorFormat ColorFormat) |
This function update/set the HDMI TX parameter. More... | |
u32 | XHdmiphy1_SetHdmiRxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function update/set the HDMI RX parameter. More... | |
void | XHdmiphy1_PatgenEnable (XHdmiphy1 *InstancePtr, u8 QuadId, u8 Enable) |
This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock. More... | |
void | XHdmiphy1_PatgenSetRatio (XHdmiphy1 *InstancePtr, u8 QuadId, u64 TxLineRate) |
This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock. More... | |
u32 | XHdmiphy1_Hdmi20Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will configure the HDMIPHY to HDMI 2.0 mode. More... | |
u32 | XHdmiphy1_Hdmi21Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels) |
This function will configure the GT for HDMI 2.1 operation. More... | |
void | XHdmiphy1_HdmiDebugInfo (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function prints Video PHY debug information related to HDMI. More... | |
void XHdmiphy1_Ch2Ids | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 * | Id0, | ||
u8 * | Id1 | ||
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This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.
HDMI uses 3 channels; This ID translation is done to allow other functions to operate iteratively over multiple channels.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID used to determine the indices. |
Id0 | is a pointer to the start channel ID to set. |
Id1 | is a pointer to the end channel ID to set. |
Referenced by XHdmiphy1_CfgLineRate(), XHdmiphy1_CfgPllRefClkSel(), XHdmiphy1_CfgSysClkDataSel(), XHdmiphy1_CfgSysClkOutSel(), XHdmiphy1_ClkCalcParams(), XHdmiphy1_ClkReconfig(), XHdmiphy1_DirReconfig(), XHdmiphy1_DruEnable(), XHdmiphy1_DruReset(), XHdmiphy1_DruSetCenterFreqHz(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiCpllLockHandler(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxAlignDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiQpllLockHandler(), XHdmiphy1_HdmiQpllParam(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_HdmiUpdateClockSelection(), XHdmiphy1_OutDivReconfig(), XHdmiphy1_PllCalculator(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_TxAlignReset(), and XHdmiphy1_TxAlignStart().
u32 XHdmiphy1_HdmiCpllParam | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir | ||
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This function calculates the CPLL parameters.
InstancePtr | is a pointer to the HDMI GT core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1::HdmiRxRefClkHz, XHdmiphy1::HdmiRxTmdsClockRatio, XHdmiphy1::HdmiTxRefClkHz, XHdmiphy1::HdmiTxSampleRate, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1_Hdmi21Cfg::LineRate, XHdmiphy1::Quads, XHdmiphy1::RxHdmi21Cfg, XHdmiphy1_Config::TransceiverWidth, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_CfgLineRate(), XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkCalcParams(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_ErrorHandler(), XHdmiphy1_GetLineRateHz(), XHDMIPHY1_LOG_EVT_DRU_CLK_ERR, XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_NO_DRU, XHDMIPHY1_LOG_EVT_USRCLK_ERR, XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_SetHdmiRxParam(), and XHdmiphy1_SetHdmiTxParam().
u32 XHdmiphy1_HdmiQpllParam | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function calculates the QPLL parameters.
InstancePtr | is a pointer to the HDMI GT core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1::HdmiRxRefClkHz, XHdmiphy1::HdmiRxTmdsClockRatio, XHdmiphy1::HdmiTxRefClkHz, XHdmiphy1::HdmiTxSampleRate, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1_Hdmi21Cfg::LineRate, XHdmiphy1::Quads, XHdmiphy1_Channel::RxDataWidth, XHdmiphy1::RxHdmi21Cfg, XHdmiphy1_Channel::RxIntDataWidth, XHdmiphy1_Config::TransceiverWidth, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_CfgLineRate(), XHdmiphy1_CfgSysClkDataSel(), XHdmiphy1_CfgSysClkOutSel(), XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkCalcParams(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_ErrorHandler(), XHdmiphy1_GetLineRateHz(), XHDMIPHY1_LOG_EVT_DRU_CLK_ERR, XHDMIPHY1_LOG_EVT_GT_QPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_NO_DRU, XHDMIPHY1_LOG_EVT_USRCLK_ERR, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_SetHdmiRxParam(), and XHdmiphy1_SetHdmiTxParam().
void XHdmiphy1_TxAlignReset | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 | Reset | ||
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This function resets the GT TX alignment module.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID to operate on. |
Reset | specifies TRUE/FALSE value to either assert or deassert reset on the TX alignment module, respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler().
void XHdmiphy1_TxAlignStart | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 | Start | ||
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This function resets the GT TX alignment module.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID to operate on. |
Start | specifies TRUE/FALSE value to either start or ttop the TX alignment module, respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().