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hdcp22_cipher_dp
Xilinx SDK Drivers API Documentation
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Macros | |
#define | XHDCP22_CIPHER_HW_H |
< Prevent circular inclusions by using protection macros More... | |
#define | XHDCP22_CIPHER_VER_ID_OFFSET ((XHDCP22_CIPHER_VER_BASE)+(0*4)) |
VER Identification register * register offset. More... | |
#define | XHDCP22_CIPHER_VER_VERSION_OFFSET ((XHDCP22_CIPHER_VER_BASE)+(1*4)) |
VER Version register * offset. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(0*4)) |
Control register * register offset. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_SET_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(1*4)) |
Control set register * offset. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_CLR_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(2*4)) |
Control clear register * offset. More... | |
#define | XHDCP22_CIPHER_REG_STA_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(3*4)) |
Status register * offset. More... | |
#define | XHDCP22_CIPHER_REG_KS_1_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(4*4)) |
Ks register 1 * offset. More... | |
#define | XHDCP22_CIPHER_REG_KS_2_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(5*4)) |
Ks register 2 * offset. More... | |
#define | XHDCP22_CIPHER_REG_KS_3_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(6*4)) |
Ks register 3 * offset. More... | |
#define | XHDCP22_CIPHER_REG_KS_4_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(7*4)) |
Ks register 4 * offset. More... | |
#define | XHDCP22_CIPHER_REG_LC128_1_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(8*4)) |
Lc128 register 1 * offset. More... | |
#define | XHDCP22_CIPHER_REG_LC128_2_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(9*4)) |
Lc128 register 2 * offset. More... | |
#define | XHDCP22_CIPHER_REG_LC128_3_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(10*4)) |
Lc128 register 3 * offset. More... | |
#define | XHDCP22_CIPHER_REG_LC128_4_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(11*4)) |
Lc128 register 4 * offset. More... | |
#define | XHDCP22_CIPHER_REG_RIV_1_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(12*4)) |
Riv register 1 * offset. More... | |
#define | XHDCP22_CIPHER_REG_RIV_2_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(13*4)) |
Riv register 2 * offset. More... | |
#define | XHDCP22_CIPHER_REG_INPUTCTR_1_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(14*4)) |
InputCtr register 1 * offset. More... | |
#define | XHDCP22_CIPHER_REG_INPUTCTR_2_OFFSET ((XHDCP22_CIPHER_REG_BASE)+(15*4)) |
InputCtr register 2 * offset. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_RUN_MASK (1<<0) |
Control register Run mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_IE_MASK (1<<1) |
Control register Interrupt Enable mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_MODE_MASK (1<<2) |
Control register Mode mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_ENCRYPT_MASK (1<<3) |
Control register Encrypt mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_BLANK_MASK (1<<4) |
Control register blank mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_NOISE_MASK (1<<5) |
Control register noise mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_LANE_CNT_MASK (0x0F<<6) |
Control register lane count mask. More... | |
#define | XHDCP22_CIPHER_REG_CTRL_LANE_CNT_BIT_POS 6 |
Control register lane count bits position. More... | |
#define | XHDCP22_CIPHER_REG_STA_IRQ_MASK (1<<0) |
Status register interrupt mask. More... | |
#define | XHDCP22_CIPHER_REG_STA_EVT_MASK (1<<1) |
Status register event mask. More... | |
#define | XHDCP22_CIPHER_REG_STA_ENCRYPTED_MASK (1<<2) |
Status register encrypted mask. More... | |
#define | XHDCP22_CIPHER_SHIFT_16 16 |
16 shift value More... | |
#define | XHDCP22_CIPHER_MASK_16 0xFFFF |
16 bit mask value More... | |
#define | XHDCP22_CIPHER_VER_ID 0x2200 |
Version ID. More... | |
Register access macro definition | |
#define | XHdcp22Cipher_In32 Xil_In32 |
Input Operations. More... | |
#define | XHdcp22Cipher_Out32 Xil_Out32 |
Output Operations. More... | |
#define | XHdcp22Cipher_ReadReg(BaseAddress, RegOffset) XHdcp22Cipher_In32((BaseAddress) + ((u32)RegOffset)) |
This macro reads a value from a HDCP22 Cipher register. More... | |
#define | XHdcp22Cipher_WriteReg(BaseAddress, RegOffset, Data) XHdcp22Cipher_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) |
This macro writes a value to a HDCP22 Cipher register. More... | |
#define | XHdcp22Cipher_GetStatusReg(BaseAddress) XHdcp22Cipher_ReadReg(BaseAddress, XHDCP22_CIPHER_REG_STA_OFFSET) |
This macro reads the status register from the HDCP22 Cipher. More... | |
#define | XHdcp22Cipher_GetControlReg(BaseAddress) XHdcp22Cipher_ReadReg(BaseAddress, XHDCP22_CIPHER_REG_CTRL_OFFSET) |
This macro reads the control register from the HDCP22 Cipher. More... | |