aiengine
Xilinx SDK Drivers API Documentation
xaietile_strm.h File Reference

Overview

Header file for stream switch configuration.

MODIFICATION HISTORY:
Ver   Who     Date     Changes


1.0 Naresh 04/06/2018 Initial creation 1.1 Naresh 07/11/2018 Updated copyright info 1.2 Hyun 10/03/2018 Added the event port select function 1.3 Hyun 10/08/2018 Added the offset for shim trace slave port 1.4 Nishad 12/05/2018 Renamed ME attributes to AIE 1.5 Wendy 16/05/2019 Wrap pointers parameters with () in macro

#define XAIETILE_STRSW_MPORT_CFGPKT(TileInstPtr, Master, DropHdr, Msk, Arbiter)
 Macro to frame the configuration word for the Master port. More...
 
#define XAIETILE_STRSW_SLVSLOT_CFG(TileInstPtr, Slave, SlotIdx, SlotId,SlotMask, SlotEnable, SlotMsel, SlotArbiter)
 Macro to frame the configuration word for the slave port slot register. More...
 
#define XAIETILE_STRSW_SPORT_CORE(TileInstPtr, Idx)   (XAIETILE_TILESTRSW_SPORT_CORE_OFF + Idx)
 Macro to compute the ID value of stream switch slave port-Core. More...
 
#define XAIETILE_STRSW_SPORT_DMA(TileInstPtr, Idx)   (XAIETILE_TILESTRSW_SPORT_DMA_OFF + Idx)
 Macro to compute the ID value of stream switch slave port-DMA. More...
 
#define XAIETILE_STRSW_SPORT_CTRL(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-Ctrl. More...
 
#define XAIETILE_STRSW_SPORT_FIFO(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-FIFO. More...
 
#define XAIETILE_STRSW_SPORT_SOUTH(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-South. More...
 
#define XAIETILE_STRSW_SPORT_WEST(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-West. More...
 
#define XAIETILE_STRSW_SPORT_NORTH(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-North. More...
 
#define XAIETILE_STRSW_SPORT_EAST(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-East. More...
 
#define XAIETILE_STRSW_SPORT_TRACE(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch slave port-Trace. More...
 
#define XAIETILE_STRSW_MPORT_CORE(TileInstPtr, Idx)   (XAIETILE_TILESTRSW_MPORT_CORE_OFF + Idx)
 Macro to compute the ID value of stream switch master port-Core. More...
 
#define XAIETILE_STRSW_MPORT_DMA(TileInstPtr, Idx)   (XAIETILE_TILESTRSW_MPORT_DMA_OFF + Idx)
 Macro to compute the ID value of stream switch master port-DMA. More...
 
#define XAIETILE_STRSW_MPORT_CTRL(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-Ctrl. More...
 
#define XAIETILE_STRSW_MPORT_FIFO(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-FIFO. More...
 
#define XAIETILE_STRSW_MPORT_SOUTH(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-South. More...
 
#define XAIETILE_STRSW_MPORT_WEST(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-West. More...
 
#define XAIETILE_STRSW_MPORT_NORTH(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-North. More...
 
#define XAIETILE_STRSW_MPORT_EAST(TileInstPtr, Idx)
 Macro to compute the ID value of stream switch master port-East. More...
 
#define XAIETILE_STRSW_MPORT_TRACE(TileInstPtr, Idx)   (XAIETILE_TILESTRSW_MPORT_TRACE_OFF + Idx)
 Macro to compute the ID value of stream switch master port-Trace. More...
 
void XAieTile_StrmConnectCct (XAieGbl_Tile *TileInstPtr, u8 Slave, u8 Master, u8 SlvEnable)
 This API is used to connect the selected master port to the specified slave port of the stream switch. More...
 
void XAieTile_StrmConfigMstr (XAieGbl_Tile *TileInstPtr, u8 Master, u8 Enable, u8 PktEnable, u8 Config)
 This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters. More...
 
void XAieTile_StrmConfigSlv (XAieGbl_Tile *TileInstPtr, u8 Slave, u8 Enable, u8 PktEnable)
 This API is used to configure the selected slave port of the stream switch in the corresponding tile. More...
 
void XAieTile_StrmConfigSlvSlot (XAieGbl_Tile *TileInstPtr, u8 Slave, u8 Slot, u8 Enable, u32 RegVal)
 This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile. More...
 
void XAieTile_ShimStrmMuxConfig (XAieGbl_Tile *TileInstPtr, u32 Port, u32 Input)
 This API sets up the mux configuraiton for Shim. More...
 
void XAieTile_ShimStrmDemuxConfig (XAieGbl_Tile *TileInstPtr, u32 Port, u32 Output)
 This API sets up the mux configuraiton for Shim DMA. More...
 
void XAieTile_StrmEventPortSelect (XAieGbl_Tile *TileInstPtr, u8 Port, u8 Master, u8 Id)
 This API sets up the event port in stream switch. More...
 

Macro Definition Documentation

#define XAIETILE_STRSW_MPORT_CFGPKT (   TileInstPtr,
  Master,
  DropHdr,
  Msk,
  Arbiter 
)
Value:
({ \
XAieGbl_RegStrmMstr *TmpPtr; \
TmpPtr = ((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
&TileStrmMstr[Master]:&ShimStrmMstr[Master]; \
(XAie_SetField(DropHdr, TmpPtr->DrpHdr.Lsb, TmpPtr->DrpHdr.Mask) | \
((u32)Msk << XAIETILE_STRSW_MPORT_PKTMSEL_SHIFT) | \
((u32)Arbiter << XAIETILE_STRSW_MPORT_PKTARB_SHIFT)); \
})

Macro to frame the configuration word for the Master port.

Parameters
TileInstPtr- Pointer to the Tile instance.
Master- Master port ID value.
DropHdr- Drop header on packet.
Msk- Mask to be used on packet ID.
Arbiter- Arbiter to use when packet matches.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_MPORT_CORE (   TileInstPtr,
  Idx 
)    (XAIETILE_TILESTRSW_MPORT_CORE_OFF + Idx)

Macro to compute the ID value of stream switch master port-Core.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_MPORT_CTRL (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_CTRL_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_CTRL_OFF + Idx)

Macro to compute the ID value of stream switch master port-Ctrl.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_MPORT_DMA (   TileInstPtr,
  Idx 
)    (XAIETILE_TILESTRSW_MPORT_DMA_OFF + Idx)

Macro to compute the ID value of stream switch master port-DMA.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_MPORT_EAST (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_EAST_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_EAST_OFF + Idx)

Macro to compute the ID value of stream switch master port-East.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_MPORT_FIFO (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_FIFO_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_FIFO_OFF + Idx)

Macro to compute the ID value of stream switch master port-FIFO.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_MPORT_NORTH (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_NORTH_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_NORTH_OFF + Idx)

Macro to compute the ID value of stream switch master port-North.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_MPORT_SOUTH (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_SOUTH_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_SOUTH_OFF + Idx)

Macro to compute the ID value of stream switch master port-South.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_MPORT_TRACE (   TileInstPtr,
  Idx 
)    (XAIETILE_TILESTRSW_MPORT_TRACE_OFF + Idx)

Macro to compute the ID value of stream switch master port-Trace.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_MPORT_WEST (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_MPORT_WEST_OFF + Idx): \
(XAIETILE_SHIMSTRSW_MPORT_WEST_OFF + Idx)

Macro to compute the ID value of stream switch master port-West.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SLVSLOT_CFG (   TileInstPtr,
  Slave,
  SlotIdx,
  SlotId,
  SlotMask,
  SlotEnable,
  SlotMsel,
  SlotArbiter 
)
Value:
({ \
XAieGbl_RegStrmSlot *TmpPtr; \
TmpPtr = (((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
&TileStrmSlot[XAIETILE_STRSW_SPORT_NUMSLOTS*Slave + SlotIdx]: \
&ShimStrmSlot[XAIETILE_STRSW_SPORT_NUMSLOTS*Slave + SlotIdx]); \
(XAie_SetField(SlotId, TmpPtr->Id.Lsb, TmpPtr->Id.Mask) | \
XAie_SetField(SlotMask, TmpPtr->Mask.Lsb, TmpPtr->Mask.Mask) | \
XAie_SetField(SlotEnable, TmpPtr->En.Lsb, TmpPtr->En.Mask) | \
XAie_SetField(SlotMsel, TmpPtr->Msel.Lsb, TmpPtr->Msel.Mask) | \
XAie_SetField(SlotArbiter, TmpPtr->Arb.Lsb, TmpPtr->Arb.Mask)); \
})

Macro to frame the configuration word for the slave port slot register.

Parameters
TileInstPtr- Pointer to the Tile instance.
Slave- Slave port ID value.
SlotIdx- Slave slot ID value, ranging from 0-3.
SlotId- Slot ID value.
SlotMask- Slot mask value.
SlotEnable- Slot enable (1-Enable,0-Disable).
SlotMsel- master select.
SlotArbiter- Arbiter to use.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_SPORT_CORE (   TileInstPtr,
  Idx 
)    (XAIETILE_TILESTRSW_SPORT_CORE_OFF + Idx)

Macro to compute the ID value of stream switch slave port-Core.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SPORT_CTRL (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_CTRL_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_CTRL_OFF + Idx)

Macro to compute the ID value of stream switch slave port-Ctrl.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SPORT_DMA (   TileInstPtr,
  Idx 
)    (XAIETILE_TILESTRSW_SPORT_DMA_OFF + Idx)

Macro to compute the ID value of stream switch slave port-DMA.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_SPORT_EAST (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_EAST_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_EAST_OFF + Idx)

Macro to compute the ID value of stream switch slave port-East.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SPORT_FIFO (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_FIFO_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_FIFO_OFF + Idx)

Macro to compute the ID value of stream switch slave port-FIFO.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SPORT_NORTH (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_NORTH_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_NORTH_OFF + Idx)

Macro to compute the ID value of stream switch slave port-North.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_SPORT_SOUTH (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_SOUTH_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_SOUTH_OFF + Idx)

Macro to compute the ID value of stream switch slave port-South.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Referenced by main().

#define XAIETILE_STRSW_SPORT_TRACE (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_TRACE_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_TRACE_OFF + Idx)

Macro to compute the ID value of stream switch slave port-Trace.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.
#define XAIETILE_STRSW_SPORT_WEST (   TileInstPtr,
  Idx 
)
Value:
((TileInstPtr)->TileType == XAIEGBL_TILE_TYPE_AIETILE)? \
(XAIETILE_TILESTRSW_SPORT_WEST_OFF + Idx): \
(XAIETILE_SHIMSTRSW_SPORT_WEST_OFF + Idx)

Macro to compute the ID value of stream switch slave port-West.

Parameters
TileInstPtr- Tile instance pointer.
Idx- Index value.
Returns
None.
Note
None.

Function Documentation

void XAieTile_ShimStrmDemuxConfig ( XAieGbl_Tile TileInstPtr,
u32  Port,
u32  Output 
)

This API sets up the mux configuraiton for Shim DMA.

Parameters
TileInstPtr- Pointer to the Tile instance.
Port,:Should be one of XAIETILE_SHIM_STRM_DEM_SOUTH2, XAIETILE_SHIM_STRM_DEM_SOUTH3, XAIETILE_SHIM_STRM_DEM_SOUTH4, or XAIETILE_SHIM_STRM_DEM_SOUTH5
Output,:Should be one of XAIETILE_SHIM_STRM_DEM_PL, XAIETILE_SHIM_STRM_DEM_DMA, or XAIETILE_SHIM_STRM_DEM_NOC.
Returns
None.
Note
None.

References XAieGbl_RegShimDemCfg::CtrlOff, XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegShimDemCfg::Port, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.

void XAieTile_ShimStrmMuxConfig ( XAieGbl_Tile TileInstPtr,
u32  Port,
u32  Input 
)

This API sets up the mux configuraiton for Shim.

Parameters
TileInstPtr- Pointer to the Tile instance.
Port,:Should be one of XAIETILE_SHIM_STRM_MUX_SOUTH2, XAIETILE_SHIM_STRM_MUX_SOUTH3, XAIETILE_SHIM_STRM_MUX_SOUTH6, or XAIETILE_SHIM_STRM_MUX_SOUTH7
Input,:Should be one of XAIETILE_SHIM_STRM_MUX_PL, XAIETILE_SHIM_STRM_MUX_DMA, or XAIETILE_SHIM_STRM_MUX_NOC.
Returns
None.
Note
None.

References XAieGbl_RegShimMuxCfg::CtrlOff, XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegShimMuxCfg::Port, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.

void XAieTile_StrmConfigMstr ( XAieGbl_Tile TileInstPtr,
u8  Master,
u8  Enable,
u8  PktEnable,
u8  Config 
)

This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters.

Parameters
TileInstPtr- Pointer to the Tile instance.
Master- Master port ID value.
Enable- Enable/Disable the master port (1-Enable,0-Disable).
PktEnable- Enable/Disable the packet switching mode (1-Enable,0-Disable).
Config- Config value to be used for circuit/packet sw. Applicable only when Enable==1. Bit encoding when PktEnable==1: 7-Drop header on packet, 6:3-Mask, 2:0-Arbiter Bit encoding when PktEnable==0: 7:5-Rsvd, 4:0-Slave port ID to which the master port need to connect to Use the macro "xaietile_strm.c::XAIETILE_STRSW_MPORT_CFGPKT()" to frame the 8-bit Config.
Returns
None.
Note
None.

References XAieGbl_RegStrmMstr::Config, XAieGbl_RegStrmMstr::DrpHdr, XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegStrmMstr::MstrEn, XAieGbl_RegStrmMstr::PktEn, XAieGbl_RegStrmMstr::RegOff, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.

Referenced by main(), and XAieTile_StrmConnectCct().

void XAieTile_StrmConfigSlv ( XAieGbl_Tile TileInstPtr,
u8  Slave,
u8  Enable,
u8  PktEnable 
)

This API is used to configure the selected slave port of the stream switch in the corresponding tile.

Parameters
TileInstPtr- Pointer to the Tile instance.
Slave- Slave port ID value.
Enable- Enable/Disable the slave port (1-Enable,0-Disable).
PktEnable- Enable/Disable the packet switching mode (1-Enable,0-Disable).
Returns
None.
Note
None.

References XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegStrmSlv::PktEn, XAieGbl_RegStrmSlv::RegOff, XAieGbl_RegStrmSlv::SlvEn, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.

Referenced by main(), and XAieTile_StrmConnectCct().

void XAieTile_StrmConfigSlvSlot ( XAieGbl_Tile TileInstPtr,
u8  Slave,
u8  Slot,
u8  Enable,
u32  RegVal 
)

This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile.

Parameters
TileInstPtr- Pointer to the Tile instance.
Slave- Slave port ID value.
Slot- Slave slot ID value, ranging from 0-3.
Enable- Enable/Disable the slave slot (1-Enable,0-Disable).
RegVal- Config value to be used for the slot. Applicable only when Enable==1, else set to 0. Bit encoding : 31:21-Rsvd, 28:24-Slot ID, 23:21-Rsvd, 20:16-ID mask, 15:6-Rsvd, 5:4-Master select/msel, 3-Rsvd, 2:0-Arbiter to use. Use the macro "xaietile_strm.c::XAIETILE_STRSW_SLVSLOT_CFG()" to frame the 32-bit RegVal.
Returns
None.
Note
None.

References XAieGbl_RegStrmSlot::En, XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegStrmSlot::RegOff, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.

Referenced by main().

void XAieTile_StrmConnectCct ( XAieGbl_Tile TileInstPtr,
u8  Slave,
u8  Master,
u8  SlvEnable 
)

This API is used to connect the selected master port to the specified slave port of the stream switch.

Parameters
TileInstPtr- Pointer to the Tile instance.
Slave- slave port ID value.
Master- Master port ID value.
SlvEnable- Enable/Disable the slave port (1-Enable,0-Disable).
Returns
None.
Note
None.

References XAieTile_StrmConfigMstr(), and XAieTile_StrmConfigSlv().

Referenced by main().

void XAieTile_StrmEventPortSelect ( XAieGbl_Tile TileInstPtr,
u8  Port,
u8  Master,
u8  Id 
)

This API sets up the event port in stream switch.

Parameters
TileInstPtr- Pointer to the Tile instance.
Port,:Port number. 0 to 7.
Master,:1 for master. 0 for slave.
Id,:Port ID for event generation
Returns
None.
Note
None.

References XAieGbl_RegFldAttr::Lsb, XAieGbl_RegFldAttr::Mask, XAieGbl_RegStrmEvtPort::MstrSlv, XAieGbl_RegStrmEvtPort::Port, XAieGbl_RegStrmEvtPort::RegOff, XAieGbl_Tile::TileAddr, and XAieGbl_Tile::TileType.