v_hdmiphy1
Xilinx SDK Drivers API Documentation
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a
b
c
d
e
h
i
l
m
n
p
q
r
t
u
x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
- a -
AxiLiteClkFreq :
XHdmiphy1_Config
- b -
BaseAddr :
XHdmiphy1_Config
- c -
Config :
XHdmiphy1
CpllParams :
XHdmiphy1_Channel
CpllRefClkSel :
XHdmiphy1_Channel
- d -
DataBuffer :
XHdmiphy1_Log
DeviceId :
XHdmiphy1_Config
DrpClkFreq :
XHdmiphy1_Config
DruIsPresent :
XHdmiphy1_Config
DruRefClkSel :
XHdmiphy1_Config
- e -
ErrIrq :
XHdmiphy1_Config
ErrorCallback :
XHdmiphy1
ErrorRef :
XHdmiphy1
- h -
HdmiFastSwitch :
XHdmiphy1_Config
HdmiIsQpllPresent :
XHdmiphy1
HdmiRxDruIsEnabled :
XHdmiphy1
HdmiRxInitCallback :
XHdmiphy1
HdmiRxInitRef :
XHdmiphy1
HdmiRxReadyCallback :
XHdmiphy1
HdmiRxReadyRef :
XHdmiphy1
HdmiRxRefClkHz :
XHdmiphy1
HdmiRxTmdsClockRatio :
XHdmiphy1
HdmiTxInitCallback :
XHdmiphy1
HdmiTxInitRef :
XHdmiphy1
HdmiTxReadyCallback :
XHdmiphy1
HdmiTxReadyRef :
XHdmiphy1
HdmiTxRefClkHz :
XHdmiphy1
HdmiTxSampleRate :
XHdmiphy1
HeadIndex :
XHdmiphy1_Log
- i -
IntrCpllLockCallbackRef :
XHdmiphy1
IntrCpllLockHandler :
XHdmiphy1
IntrQpll1LockCallbackRef :
XHdmiphy1
IntrQpll1LockHandler :
XHdmiphy1
IntrQpllLockCallbackRef :
XHdmiphy1
IntrQpllLockHandler :
XHdmiphy1
IntrRxClkDetFreqChangeCallbackRef :
XHdmiphy1
IntrRxClkDetFreqChangeHandler :
XHdmiphy1
IntrRxMmcmLockCallbackRef :
XHdmiphy1
IntrRxMmcmLockHandler :
XHdmiphy1
IntrRxResetDoneCallbackRef :
XHdmiphy1
IntrRxResetDoneHandler :
XHdmiphy1
IntrRxTmrTimeoutCallbackRef :
XHdmiphy1
IntrRxTmrTimeoutHandler :
XHdmiphy1
IntrTxAlignDoneCallbackRef :
XHdmiphy1
IntrTxAlignDoneHandler :
XHdmiphy1
IntrTxClkDetFreqChangeCallbackRef :
XHdmiphy1
IntrTxClkDetFreqChangeHandler :
XHdmiphy1
IntrTxMmcmLockCallbackRef :
XHdmiphy1
IntrTxMmcmLockHandler :
XHdmiphy1
IntrTxResetDoneCallbackRef :
XHdmiphy1
IntrTxResetDoneHandler :
XHdmiphy1
IntrTxTmrTimeoutCallbackRef :
XHdmiphy1
IntrTxTmrTimeoutHandler :
XHdmiphy1
IsEnabled :
XHdmiphy1_Hdmi21Cfg
IsReady :
XHdmiphy1
- l -
LineRate :
XHdmiphy1_Hdmi21Cfg
LineRateHz :
XHdmiphy1_Channel
Log :
XHdmiphy1
LogWriteCallback :
XHdmiphy1
LogWriteRef :
XHdmiphy1
- m -
Mmcm :
XHdmiphy1_Quad
- n -
NChannels :
XHdmiphy1_Hdmi21Cfg
- p -
PllLayoutErrorCallback :
XHdmiphy1
PllLayoutErrorRef :
XHdmiphy1
Ppc :
XHdmiphy1_Config
- q -
Quads :
XHdmiphy1
- r -
RxChannels :
XHdmiphy1_Config
RxDataRefClkSel :
XHdmiphy1_Channel
RxDataWidth :
XHdmiphy1_Channel
RxDelayBypass :
XHdmiphy1_Channel
RxFrlRefClkSel :
XHdmiphy1_Config
RxHdmi21Cfg :
XHdmiphy1
RxIntDataWidth :
XHdmiphy1_Channel
RxMmcm :
XHdmiphy1_Quad
RxOutClkSel :
XHdmiphy1_Channel
RxOutDiv :
XHdmiphy1_Channel
RxOutRefClkSel :
XHdmiphy1_Channel
RxProtocol :
XHdmiphy1_Config
,
XHdmiphy1_Channel
RxRefClkSel :
XHdmiphy1_Config
RxState :
XHdmiphy1_Channel
RxSysPllClkSel :
XHdmiphy1_Config
- t -
TailIndex :
XHdmiphy1_Log
TimeRecord :
XHdmiphy1_Log
TransceiverWidth :
XHdmiphy1_Config
TxBufferBypass :
XHdmiphy1_Config
TxChannels :
XHdmiphy1_Config
TxDataRefClkSel :
XHdmiphy1_Channel
TxDataWidth :
XHdmiphy1_Channel
TxDelayBypass :
XHdmiphy1_Channel
TxFrlRefClkSel :
XHdmiphy1_Config
TxHdmi21Cfg :
XHdmiphy1
TxIntDataWidth :
XHdmiphy1_Channel
TxMmcm :
XHdmiphy1_Quad
TxOutClkSel :
XHdmiphy1_Channel
TxOutDiv :
XHdmiphy1_Channel
TxOutRefClkSel :
XHdmiphy1_Channel
TxProtocol :
XHdmiphy1_Channel
,
XHdmiphy1_Config
TxRefClkSel :
XHdmiphy1_Config
TxState :
XHdmiphy1_Channel
TxSysPllClkSel :
XHdmiphy1_Config
- u -
UseGtAsTxTmdsClk :
XHdmiphy1_Config
UserTimerPtr :
XHdmiphy1
UserTimerWaitUs :
XHdmiphy1
- x -
XcvrType :
XHdmiphy1_Config
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