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v_hdmiphy1
Xilinx SDK Drivers API Documentation
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Contains a minimal set of functions for the XHdmiphy1 driver that allow access to all of the Video PHY core's functionality.
See xhdmiphy1.h for a detailed description of the driver.
MODIFICATION HISTORY:
Ver Who Date Changes
dd/mm/yy
1.0 gm 10/12/18 Initial release.
Functions | |
void | XHdmiphy1_CfgInitialize (XHdmiphy1 *InstancePtr, XHdmiphy1_Config *ConfigPtr, UINTPTR EffectiveAddr) |
This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure. More... | |
u32 | XHdmiphy1_PllInitialize (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_PllRefClkSelType QpllRefClkSel, XHdmiphy1_PllRefClkSelType CpllRefClkSel, XHdmiphy1_PllType TxPllSelect, XHdmiphy1_PllType RxPllSelect) |
This function will initialize the PLL selection for a given channel. More... | |
void | XHdmiphy1_WaitUs (XHdmiphy1 *InstancePtr, u32 MicroSeconds) |
This function is the delay/sleep function for the XHdmiphy1 driver. More... | |
u32 | XHdmiphy1_GetVersion (XHdmiphy1 *InstancePtr) |
This function will obtian the IP version. More... | |
u32 | XHdmiphy1_CfgLineRate (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u64 LineRateHz) |
Configure the channel's line rate. More... | |
XHdmiphy1_PllType | XHdmiphy1_GetPllType (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the channel's PLL reference clock selection. More... | |
u64 | XHdmiphy1_GetLineRateHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will return the line rate in Hz for a given channel / quad. More... | |
u32 | XHdmiphy1_ResetGtPll (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the GT's PLL logic. More... | |
u32 | XHdmiphy1_ResetGtTxRx (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the GT's TX/RX logic. More... | |
u32 | XHdmiphy1_SetPolarity (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Polarity) |
This function will set/clear the TX/RX polarity bit. More... | |
u32 | XHdmiphy1_SetPrbsSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, XHdmiphy1_PrbsPattern Pattern) |
This function will set the TX/RXPRBSEL of the GT. More... | |
u32 | XHdmiphy1_TxPrbsForceError (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 ForceErr) |
This function will set the TX/RXPRBSEL of the GT. More... | |
void | XHdmiphy1_SetTxVoltageSwing (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Vs) |
This function will set the TX voltage swing value for a given channel. More... | |
void | XHdmiphy1_SetTxPreEmphasis (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Pe) |
This function will set the TX pre-emphasis value for a given channel. More... | |
void | XHdmiphy1_SetTxPostCursor (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Pc) |
This function will set the TX post-curosr value for a given channel. More... | |
void | XHdmiphy1_SetRxLpm (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function will enable or disable the LPM logic in the Video PHY core. More... | |
u32 | XHdmiphy1_DrpWr (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u16 Addr, u16 Val) |
This function will initiate a write DRP transaction. More... | |
u16 | XHdmiphy1_DrpRd (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u16 Addr, u16 *RetVal) |
This function will initiate a read DRP transaction. More... | |
void | XHdmiphy1_MmcmPowerDown (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will power down the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmStart (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will start the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_IBufDsEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function enables the TX or RX IBUFDS peripheral. More... | |
void | XHdmiphy1_Clkout1OBufTdsEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function enables the TX or RX CLKOUT1 OBUFTDS peripheral. More... | |
void | XHdmiphy1_SetErrorCallback (XHdmiphy1 *InstancePtr, void *CallbackFunc, void *CallbackRef) |
This function installs a callback function for the HDMIPHY error conditions. More... | |
void | XHdmiphy1_SetLogCallback (XHdmiphy1 *InstancePtr, u64 *CallbackFunc, void *CallbackRef) |
This function installs an asynchronous callback function for the LogWrite API: More... | |
void | XHdmiphy1_RegisterDebug (XHdmiphy1 *InstancePtr) |
This function prints out Video PHY register and GT Channel and Common DRP register contents. More... | |