iomodule
Xilinx SDK Drivers API Documentation
xiomodule_l.h File Reference

Macros

#define XTC_DEVICE_TIMER_COUNT   4
 Defines the number of timer counters within a single hardware device. More...
 
#define XTC_TIMER_COUNTER_OFFSET   16
 Each timer counter consumes 16 bytes of address space. More...
 
#define XUL_RX_OFFSET   0x00000000
 Define the offsets from the base address for all the registers of the IO module, some registers may be optional in the hardware device. More...
 
#define XUL_TX_OFFSET   0x00000004
 UART Transmit Register - W. More...
 
#define XUL_STATUS_REG_OFFSET   0x00000008
 UART Status Register - R. More...
 
#define XUL_BAUDRATE_OFFSET   0x0000004C
 UART Baud Rate Register - W. More...
 
#define XIN_IMR_OFFSET   0x0000000C
 Intr Mode Register - W. More...
 
#define XGO_OUT_OFFSET   0x00000010
 General Purpose Output - W. More...
 
#define XGI_IN_OFFSET   0x00000020
 General Purpose Input - R. More...
 
#define XIN_ISR_OFFSET   0x00000030
 Intr Status Register - R. More...
 
#define XIN_IPR_OFFSET   0x00000034
 Intr Pending Register - R. More...
 
#define XIN_IER_OFFSET   0x00000038
 Intr Enable Register - W. More...
 
#define XIN_IAR_OFFSET   0x0000003C
 Intr Acknowledge Register - W. More...
 
#define XTC_TLR_OFFSET   0x00000040
 Timer Load register - W. More...
 
#define XTC_TCR_OFFSET   0x00000044
 Timer counter register - R. More...
 
#define XTC_TCSR_OFFSET   0x00000048
 Timer Control register - W. More...
 
#define XIN_IVAR_OFFSET   0x00000080
 Intr Vector Address Register, Interrupt 0 offset, present only for Fast Interrupt - W. More...
 
#define XIN_IVEAR_OFFSET   0x00000100
 Intr Extended Vector Address Register - W. More...
 
#define XUL_SR_PARITY_ERROR   0x80
 UART status register bit position masks. More...
 
#define XUL_SR_INTR_ENABLED   0x10
 UART Interrupt enabled. More...
 
#define XUL_SR_TX_FIFO_FULL   0x08
 UART Transmit FIFO full. More...
 
#define XUL_SR_RX_FIFO_VALID_DATA   0x01
 UART Data Register valid. More...
 
#define XUL_STOP_BITS   1
 UART stop bits are fixed at 1. More...
 
#define XUL_PARITY_NONE   0
 UART Parity definitions. More...
 
#define XIOModule_EnableIntr(BaseAddress, EnableMask)   XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
 Enable specific interrupt(s) in the interrupt controller. More...
 
#define XIOModule_DisableIntr(BaseAddress, DisableMask)   XIomodule_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
 Disable specific interrupt(s) in the interrupt controller. More...
 
#define XIOModule_AckIntr(BaseAddress, AckMask)   XIomodule_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
 Acknowledge specific interrupt(s) in the interrupt controller. More...
 
#define XIOModule_GetIntrStatus(BaseAddress)   (XIomodule_In32((BaseAddress) + XIN_IPR_OFFSET))
 Get the interrupt status from the interrupt controller which indicates which interrupts are active and enabled. More...
 
#define XIOModule_GetStatusReg(BaseAddress)   XIomodule_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
 Get the contents of the UART status register. More...
 
#define XIOModule_IsReceiveEmpty(BaseAddress)
 Check to see if the UART receiver has data. More...
 
#define XIOModule_IsTransmitFull(BaseAddress)
 Check to see if the transmitter is full. More...
 
#define XIOModule_WriteReg(BaseAddress, RegOffset, Data)   XIomodule_Out32((BaseAddress) + (RegOffset), (u32)(Data))
 Write a value to a GPO register. More...
 
#define XIOModule_ReadReg(BaseAddress, RegOffset)   XIomodule_In32((BaseAddress) + (RegOffset))
 Read a value from a GPI register. More...
 
#define XGPI_DEVICE_COUNT   4
 Defines the number of GPI and GPO within a single hardware device. More...
 
#define XGPI_CHAN_OFFSET   0x00004
 The following constants describe the offset of each GPI and GPO channel's data from the base address. More...
 
#define XIN_IOMODULE_GPI_4_INTERRUPT_INTR   14
 Interrupt register bit position masks. More...
 
Control Status Register Bit Definitions

Control Status Register bit masks Used to configure the timer counter device.

#define XTC_CSR_ENABLE_TMR_MASK   0x00000001
 Enables the timer. More...
 
#define XTC_CSR_AUTO_RELOAD_MASK   0x00000002
 In compare mode, configures the timer reload from the Load Register. More...
 

Functions

void XIOModule_SendByte (UINTPTR BaseAddress, u8 Data)
 This functions sends a single byte using the UART. More...
 
u8 XIOModule_RecvByte (UINTPTR BaseAddress)
 This functions receives a single byte using the UART. More...
 
void XIOModule_DeviceInterruptHandler (void *DeviceId)
 This is the interrupt handler for the driver interface provided in this file when there can be no argument passed to the handler. More...
 
void XIOModule_SetIntrSvcOption (UINTPTR BaseAddress, int Option)
 Set the interrupt service option, which can configure the driver so that it services only a single interrupt at a time when an interrupt occurs, or services all pending interrupts when an interrupt occurs. More...
 
void XIOModule_RegisterHandler (UINTPTR BaseAddress, int InterruptId, XInterruptHandler Handler, void *CallBackRef)
 Register a handler function for a specific interrupt ID. More...