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spdif
Xilinx SDK Drivers API Documentation
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Macros | |
#define | XSPDIF_SOFT_RESET_REGISTER_VALUE 0X0A |
Soft Reset Register value to reset. More... | |
#define | XSPDIF_CLK_4 4 |
Clock divide by 4. More... | |
#define | XSPDIF_CLK_8 8 |
Clock divide by 8. More... | |
#define | XSPDIF_CLK_16 16 |
Clock divide by 16. More... | |
#define | XSPDIF_CLK_24 24 |
Clock divide by 24. More... | |
#define | XSPDIF_CLK_32 32 |
Clock divide by 32. More... | |
#define | XSPDIF_CLK_48 48 |
Clock divide by 48. More... | |
#define | XSPDIF_CLK_64 64 |
Clock divide by 64. More... | |
Functions | |
int | XSpdif_CfgInitialize (XSpdif *InstancePtr, XSpdif_Config *CfgPtr, UINTPTR EffectiveAddr) |
This function initializes the XSpdif. More... | |
void | XSpdif_Enable (XSpdif *InstancePtr, u8 Enable) |
This function enables/disables the XSpdif. More... | |
void | XSpdif_SoftReset (XSpdif *InstancePtr) |
This function is used to soft reset the interrupt registers. More... | |
void | XSpdif_ResetFifo (XSpdif *InstancePtr) |
This function resets the Fifo. More... | |
void | XSpdif_SetClkConfig (XSpdif *InstancePtr, u8 Clk_DivNum) |
This function sets the clock configuration bits. More... | |
u32 | XSpdif_GetFs (XSpdif *InstancePtr, u32 AudClk) |
This function calculates the Sampling Frequency (Fs) and returns it's value. More... | |
void | XSpdif_Rx_GetChStat (XSpdif *InstancePtr, u8 *ChStatBuf) |
This function reads all the Channel Status registers and writes to a buffer. More... | |
void | XSpdif_Rx_GetChA_UserData (XSpdif *InstancePtr, u8 *ChA_UserDataBuf) |
This function reads the Channel A user data and writes to a buffer. More... | |
void | XSpdif_Rx_GetChB_UserData (XSpdif *InstancePtr, u8 *ChB_UserDataBuf) |
This function reads the Channel B user data and writes to a buffer. More... | |
void | XSpdif_IntrHandler (void *InstancePtr) |
This function is the interrupt handler for the XSpdif driver. More... | |
int | XSpdif_SetHandler (XSpdif *InstancePtr, XSpdif_HandlerType HandlerType, XSpdif_Callback FuncPtr, void *CallbackRef) |
This function installs an asynchronous callback function for the given HandlerType: More... | |
XSpdif_Config * | XSpdif_LookupConfig (u16 DeviceId) |
This function returns a reference to an XSpdif_Config structure based on the core id, DeviceId. More... | |
int | XSpdif_Initialize (XSpdif *InstancePtr, u16 DeviceId) |
Initializes a specific Xspdif instance such that the driver is ready to use. More... | |
AES Status and Register Masks and Shifts | |
For formats/line protocols check the AES Standard specifications document | |
#define | XSPDIF_AES_STS_USE_OF_CH_STS_BLK_SHIFT (0) |
Use of Channel Status Block bit shift. More... | |
#define | XSPDIF_AES_STS_USE_OF_CH_STS_BLK_MASK (1 << XSPDIF_AES_STS_USE_OF_CH_STS_BLK_SHIFT) |
Use of Channel Status Block mask. More... | |
#define | XSPDIF_AES_STS_LINEAR_PCM_ID_SHIFT (1) |
Linear PCM Identification bit shift. More... | |
#define | XSPDIF_AES_STS_LINEAR_PCM_ID_MASK (1 << XSPDIF_AES_STS_LINEAR_PCM_ID_SHIFT) |
Linear PCM Identification mask. More... | |
#define | XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT (2) |
Audio signal pre- emphasis bit shift. More... | |
#define | XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_MASK (0x7 << XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT) |
Audio signal pre-emphasis mask. More... | |
#define | XSPDIF_AES_STS_LOCK_INDICATION_SHIFT (5) |
lock indication bit shift More... | |
#define | XSPDIF_AES_STS_LOCK_INDICATION_MASK (1 << XSPDIF_AES_STS_LOCK_INDICATION_SHIFT) |
Lock indication mask. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_E_SHIFT (6) |
Sampling Frequency 0 bit shift. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_E_MASK (0x3 << XSPDIF_AES_STS_SAMPLING_FREQ_E_SHIFT) |
Sampling Frequency 0 mask. More... | |
#define | XSPDIF_AES_STS_CH_MODE_SHIFT (0) |
Channel mode bit shift. More... | |
#define | XSPDIF_AES_STS_CH_MODE_MASK (0xF << XSPDIF_AES_STS_CH_MODE_SHIFT) |
Channel mode mask. More... | |
#define | XSPDIF_AES_STS_USR_BITS_MGMT_SHIFT (4) |
User Bits Management bit shift. More... | |
#define | XSPDIF_AES_STS_USR_BITS_MGMT_MASK (0xF << XSPDIF_AES_STS_USR_BITS_MGMT_SHIFT) |
User Bits Management mask. More... | |
#define | XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT (0) |
Use of auxiliary sample bits bit shift. More... | |
#define | XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_MASK (0x7 << XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT) |
Use of Auxiliary sample bits mask. More... | |
#define | XSPDIF_AES_STS_SRC_WORD_LENGTH_SHIFT (3) |
Source word length bit shift. More... | |
#define | XSPDIF_AES_STS_SRC_WORD_LENGTH_MASK (0x7 << XSPDIF_AES_STS_SRC_WORD_LENGTH_SHIFT) |
Source word length mask. More... | |
#define | XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT (6) |
Indication of Alignment level bit shift. More... | |
#define | XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_MASK (0x3 << XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT) |
Indication of Alignment level mask. More... | |
#define | XSPDIF_AES_STS_CH_NUM0_SHIFT (0) |
Channel Number (0) bit shift. More... | |
#define | XSPDIF_AES_STS_CH_NUM0_MASK (0x7F << XSPDIF_AES_STS_CH_NUM0_SHIFT) |
Channel Number (0) mask. More... | |
#define | XSPDIF_AES_STS_MC_CH_MODE_SHIFT (7) |
Multichannel mode bit shift. More... | |
#define | XSPDIF_AES_STS_MC_CH_MODE_MASK (1 << XSPDIF_AES_STS_MC_CH_MODE_SHIFT) |
Multichannel mode mask. More... | |
#define | XSPDIF_AES_STS_CH_NUM1_SHIFT (0) |
Channel Number (1) bit shift. More... | |
#define | XSPDIF_AES_STS_CH_NUM1_MASK (0xF << XSPDIF_AES_STS_CH_NUM1_SHIFT) |
Channel Number (1) mask. More... | |
#define | XSPDIF_AES_STS_MC_CH_MODE_NUM_SHIFT (4) |
Multichannel mode number bit shift. More... | |
#define | XSPDIF_AES_STS_MC_CH_MODE_NUM_MASK (0x7 << XSPDIF_AES_STS_MC_CH_MODE_NUM_SHIFT) |
Multichannel mode number mask. More... | |
#define | XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT (0) |
Digital Reference Audio signal bit shift. More... | |
#define | XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK (0x3 << XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT) |
Digital Reference Audio signal mask. More... | |
#define | XSPDIF_AES_STS_RSVD_BUT_UNDEF0_SHIFT (2) |
Reserved but undefined (0) bit shift. More... | |
#define | XSPDIF_AES_STS_RSVD_BUT_UNDEF0_MASK (1 << XSPDIF_AES_STS_RSVD_BUT_UNDEF0_SHIFT) |
Reserved but undefined (0) mask. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_Q_SHIFT (3) |
Sampling Frequency (1) bit shift. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_Q_MASK (0xF << XSPDIF_AES_STS_SAMPLING_FREQ_Q_SHIFT) |
Sampling Frequency (1) mask. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT (7) |
Sampling Frequency scaling flag bit shift. More... | |
#define | XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK (1 << XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT) |
Sampling Frequency scaling flag mask. More... | |
#define | XSPDIF_AES_STS_RSVD_BUT_UNDEF1_SHIFT (0) |
Reserved but undefined (1) bit shift. More... | |
#define | XSPDIF_AES_STS_RSVD_BUT_UNDEF1_MASK (0xFF << XSPDIF_AES_STS_RSVD_BUT_UNDEF1_SHIFT) |
Reserved but undefined (1) mask. More... | |
#define | XSPDIF_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET (6) |
Alphanumeric channel origin data register(s) offset. More... | |
#define | XSPDIF_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET (10) |
Alphanumeric channel destination data bit shift. More... | |
#define | XSPDIF_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET (14) |
Local sample address code register(s) offset. More... | |
#define | XSPDIF_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET (18) |
Time-of-day sample address code register(s) offset. More... | |
#define | XSPDIF_AES_STS_RELIABLE_FLAGS_OFFSET (22) |
Reliability flags bit shift. More... | |
#define | XSPDIF_AES_STS_CRC_CHAR_OFFSET (23) |
Cyclic redundancy check character bit shift. More... | |
Register Map | |
Register offsets for the XSpdif device. | |
#define | XSPDIF_GLOBAL_INTERRUPT_ENABLE_OFFSET 0x1C |
Device Global interrupt enable register. More... | |
#define | XSPDIF_INTERRUPT_STATUS_REGISTER_OFFSET 0x20 |
IP Interrupt Status Register. More... | |
#define | XSPDIF_INTERRUPT_ENABLE_REGISTER_OFFSET 0x28 |
IP interrupt enable Register. More... | |
#define | XSPDIF_SOFT_RESET_REGISTER_OFFSET 0x40 |
Soft Reset Register. More... | |
#define | XSPDIF_CONTROL_REGISTER_OFFSET 0x44 |
Control Register. More... | |
#define | XSPDIF_STATUS_REGISTER_OFFSET 0x48 |
Status Register. More... | |
#define | XSPDIF_CHANNEL_STATUS_REGISTER0_OFFSET 0x4C |
Audio Channel Status bits 0 to 31. More... | |
#define | XSPDIF_CHANNEL_A_USER_DATA_REGISTER0_OFFSET 0x64 |
Channel A user data bits 0 to 31. More... | |
#define | XSPDIF_CHANNEL_B_USER_DATA_REGISTER0_OFFSET 0x7C |
Channel B user data bits 0 to 31. More... | |
Core Configuration Register masks and shifts | |
#define | XSPDIF_CORE_ENABLE_SHIFT (0) |
Is XSPDIF Core Enable bit shift. More... | |
#define | XSPDIF_CORE_ENABLE_MASK (1 << XSPDIF_CORE_ENABLE_SHIFT) |
Is XSPDIF Core Enable bit mask. More... | |
#define | XSPDIF_FIFO_FLUSH_SHIFT (1) |
Is XSPDIF Reset FIFO bit shift. More... | |
#define | XSPDIF_FIFO_FLUSH_MASK (1 << XSPDIF_FIFO_FLUSH_SHIFT) |
Is XSPDIF Reset FIFO bit mask. More... | |
#define | XSPDIF_CLOCK_CONFIG_BITS_SHIFT (2) |
Is XSPDIF clock configuration bits shift. More... | |
#define | XSPDIF_CLOCK_CONFIG_BITS_MASK ((0xF) << XSPDIF_CLOCK_CONFIG_BITS_SHIFT) |
Is XSPDIF clock configuration bits mask. More... | |
#define | XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT (0) |
XSPDIF sample clock count shift. More... | |
#define | XSPDIF_SAMPLE_CLOCK_COUNT_MASK ((0X3FF) << XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT) |
XSPDIF sample clock count mask. More... | |
Interrupt masks and shifts | |
#define | XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT (0) |
Transmitter or Receiver FIFO Full Interrupt bit shift. More... | |
#define | XSPDIF_TX_OR_RX_FIFO_FULL_MASK (1 << XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT) |
Transmitter or Receiver FIFO Full Interrupt bit mask. More... | |
#define | XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT (1) |
Transmitter or Receiver FIFO Empty Interrupt bit shift. More... | |
#define | XSPDIF_TX_OR_RX_FIFO_EMPTY_MASK (1 << XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT) |
Transmitter or Receiver FIFO Empty Interrupt bit mask. More... | |
#define | XSPDIF_START_OF_BLOCK_SHIFT (2) |
Start of Block Interrupt bit mask ( in Receive mode) More... | |
#define | XSPDIF_START_OF_BLOCK_MASK (1 << XSPDIF_START_OF_BLOCK_SHIFT) |
Transmitter or Receiver FIFO Full Interrupt bit shift. More... | |
#define | XSPDIF_BMC_ERROR_SHIFT (3) |
BMC Error Interrupt bit shift. More... | |
#define | XSPDIF_BMC_ERROR_MASK (1 << XSPDIF_BMC_ERROR_SHIFT) |
BMC Error Interrupt bit mask. More... | |
#define | XSPDIF_PREAMBLE_ERROR_SHIFT (4) |
Preamble error Interrupt bit shift. More... | |
#define | XSPDIF_PREAMBLE_ERROR_MASK (1 << XSPDIF_PREAMBLE_ERROR_SHIFT) |
Preamble error Interrupt bit mask. More... | |
#define | XSPDIF_GINTR_ENABLE_SHIFT (31) |
Global interrupt enable bit shift. More... | |
#define | XSPDIF_GINTR_ENABLE_MASK (1 << XSPDIF_GINTR_ENABLE_SHIFT) |
Global interrupt enable bit mask. More... | |
Register access macro definition | |
#define | XSpdif_In32 Xil_In32 |
Input Operations. More... | |
#define | XSpdif_Out32 Xil_Out32 |
Output Operations. More... | |
#define | XSpdif_ReadReg(BaseAddress, RegOffset) XSpdif_In32((BaseAddress) + ((u32)RegOffset)) |
This macro reads a value from a XSpdif register. More... | |
#define | XSpdif_WriteReg(BaseAddress, RegOffset, Data) XSpdif_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) |
This macro writes a value to a XSpdif register. More... | |
#define XSPDIF_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET (10) |
Alphanumeric channel destination data bit shift.
#define XSPDIF_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET (6) |
Alphanumeric channel origin data register(s) offset.
#define XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_MASK (0x7 << XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT) |
Audio signal pre-emphasis mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT (2) |
Audio signal pre- emphasis bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_CH_MODE_MASK (0xF << XSPDIF_AES_STS_CH_MODE_SHIFT) |
Channel mode mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_CH_MODE_SHIFT (0) |
Channel mode bit shift.
#define XSPDIF_AES_STS_CH_NUM0_MASK (0x7F << XSPDIF_AES_STS_CH_NUM0_SHIFT) |
Channel Number (0) mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_CH_NUM0_SHIFT (0) |
Channel Number (0) bit shift.
#define XSPDIF_AES_STS_CH_NUM1_MASK (0xF << XSPDIF_AES_STS_CH_NUM1_SHIFT) |
Channel Number (1) mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_CH_NUM1_SHIFT (0) |
Channel Number (1) bit shift.
#define XSPDIF_AES_STS_CRC_CHAR_OFFSET (23) |
Cyclic redundancy check character bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK (0x3 << XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT) |
Digital Reference Audio signal mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT (0) |
Digital Reference Audio signal bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_MASK (0x3 << XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT) |
Indication of Alignment level mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT (6) |
Indication of Alignment level bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_LINEAR_PCM_ID_MASK (1 << XSPDIF_AES_STS_LINEAR_PCM_ID_SHIFT) |
Linear PCM Identification mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_LINEAR_PCM_ID_SHIFT (1) |
Linear PCM Identification bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET (14) |
Local sample address code register(s) offset.
#define XSPDIF_AES_STS_LOCK_INDICATION_MASK (1 << XSPDIF_AES_STS_LOCK_INDICATION_SHIFT) |
Lock indication mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_LOCK_INDICATION_SHIFT (5) |
lock indication bit shift
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_MC_CH_MODE_MASK (1 << XSPDIF_AES_STS_MC_CH_MODE_SHIFT) |
Multichannel mode mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_MC_CH_MODE_NUM_MASK (0x7 << XSPDIF_AES_STS_MC_CH_MODE_NUM_SHIFT) |
Multichannel mode number mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_MC_CH_MODE_NUM_SHIFT (4) |
Multichannel mode number bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_MC_CH_MODE_SHIFT (7) |
Multichannel mode bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_RELIABLE_FLAGS_OFFSET (22) |
Reliability flags bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_RSVD_BUT_UNDEF0_MASK (1 << XSPDIF_AES_STS_RSVD_BUT_UNDEF0_SHIFT) |
Reserved but undefined (0) mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_RSVD_BUT_UNDEF0_SHIFT (2) |
Reserved but undefined (0) bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_RSVD_BUT_UNDEF1_MASK (0xFF << XSPDIF_AES_STS_RSVD_BUT_UNDEF1_SHIFT) |
Reserved but undefined (1) mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_RSVD_BUT_UNDEF1_SHIFT (0) |
Reserved but undefined (1) bit shift.
#define XSPDIF_AES_STS_SAMPLING_FREQ_E_MASK (0x3 << XSPDIF_AES_STS_SAMPLING_FREQ_E_SHIFT) |
Sampling Frequency 0 mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SAMPLING_FREQ_E_SHIFT (6) |
Sampling Frequency 0 bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SAMPLING_FREQ_Q_MASK (0xF << XSPDIF_AES_STS_SAMPLING_FREQ_Q_SHIFT) |
Sampling Frequency (1) mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SAMPLING_FREQ_Q_SHIFT (3) |
Sampling Frequency (1) bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK (1 << XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT) |
Sampling Frequency scaling flag mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT (7) |
Sampling Frequency scaling flag bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SRC_WORD_LENGTH_MASK (0x7 << XSPDIF_AES_STS_SRC_WORD_LENGTH_SHIFT) |
Source word length mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_SRC_WORD_LENGTH_SHIFT (3) |
Source word length bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET (18) |
Time-of-day sample address code register(s) offset.
#define XSPDIF_AES_STS_USE_OF_CH_STS_BLK_MASK (1 << XSPDIF_AES_STS_USE_OF_CH_STS_BLK_SHIFT) |
Use of Channel Status Block mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_USE_OF_CH_STS_BLK_SHIFT (0) |
Use of Channel Status Block bit shift.
#define XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_MASK (0x7 << XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT) |
Use of Auxiliary sample bits mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT (0) |
Use of auxiliary sample bits bit shift.
#define XSPDIF_AES_STS_USR_BITS_MGMT_MASK (0xF << XSPDIF_AES_STS_USR_BITS_MGMT_SHIFT) |
User Bits Management mask.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_AES_STS_USR_BITS_MGMT_SHIFT (4) |
User Bits Management bit shift.
Referenced by XSpdif_Decode_ChStat().
#define XSPDIF_BMC_ERROR_MASK (1 << XSPDIF_BMC_ERROR_SHIFT) |
BMC Error Interrupt bit mask.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_BMC_ERROR_SHIFT (3) |
BMC Error Interrupt bit shift.
#define XSPDIF_CHANNEL_A_USER_DATA_REGISTER0_OFFSET 0x64 |
Channel A user data bits 0 to 31.
Referenced by XSpdif_Rx_GetChA_UserData().
#define XSPDIF_CHANNEL_B_USER_DATA_REGISTER0_OFFSET 0x7C |
Channel B user data bits 0 to 31.
Referenced by XSpdif_Rx_GetChB_UserData().
#define XSPDIF_CHANNEL_STATUS_REGISTER0_OFFSET 0x4C |
Audio Channel Status bits 0 to 31.
Referenced by XSpdif_Rx_GetChStat().
#define XSPDIF_CLK_16 16 |
Clock divide by 16.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_24 24 |
Clock divide by 24.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_32 32 |
Clock divide by 32.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_4 4 |
Clock divide by 4.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_48 48 |
Clock divide by 48.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_64 64 |
Clock divide by 64.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLK_8 8 |
Clock divide by 8.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLOCK_CONFIG_BITS_MASK ((0xF) << XSPDIF_CLOCK_CONFIG_BITS_SHIFT) |
Is XSPDIF clock configuration bits mask.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CLOCK_CONFIG_BITS_SHIFT (2) |
Is XSPDIF clock configuration bits shift.
Referenced by XSpdif_SetClkConfig().
#define XSPDIF_CONTROL_REGISTER_OFFSET 0x44 |
Control Register.
Referenced by XSpdif_Enable(), XSpdif_ResetFifo(), and XSpdif_SetClkConfig().
#define XSPDIF_CORE_ENABLE_MASK (1 << XSPDIF_CORE_ENABLE_SHIFT) |
Is XSPDIF Core Enable bit mask.
Referenced by XSpdif_Enable(), and XSpdif_ResetFifo().
#define XSPDIF_CORE_ENABLE_SHIFT (0) |
Is XSPDIF Core Enable bit shift.
#define XSPDIF_FIFO_FLUSH_MASK (1 << XSPDIF_FIFO_FLUSH_SHIFT) |
Is XSPDIF Reset FIFO bit mask.
#define XSPDIF_FIFO_FLUSH_SHIFT (1) |
Is XSPDIF Reset FIFO bit shift.
#define XSPDIF_GINTR_ENABLE_MASK (1 << XSPDIF_GINTR_ENABLE_SHIFT) |
Global interrupt enable bit mask.
#define XSPDIF_GINTR_ENABLE_SHIFT (31) |
Global interrupt enable bit shift.
#define XSPDIF_GLOBAL_INTERRUPT_ENABLE_OFFSET 0x1C |
Device Global interrupt enable register.
#define XSpdif_In32 Xil_In32 |
Input Operations.
#define XSPDIF_INTERRUPT_ENABLE_REGISTER_OFFSET 0x28 |
IP interrupt enable Register.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_INTERRUPT_STATUS_REGISTER_OFFSET 0x20 |
IP Interrupt Status Register.
Referenced by XSpdif_IntrHandler().
#define XSpdif_Out32 Xil_Out32 |
Output Operations.
#define XSPDIF_PREAMBLE_ERROR_MASK (1 << XSPDIF_PREAMBLE_ERROR_SHIFT) |
Preamble error Interrupt bit mask.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_PREAMBLE_ERROR_SHIFT (4) |
Preamble error Interrupt bit shift.
#define XSpdif_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XSpdif_In32((BaseAddress) + ((u32)RegOffset)) |
This macro reads a value from a XSpdif register.
A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.
BaseAddress | is the base address of the XSpdif core instance. |
RegOffset | is the register offset of the register (defined at the top of this file). |
Referenced by XSpdif_Enable(), XSpdif_GetFs(), XSpdif_IntrHandler(), XSpdif_ResetFifo(), XSpdif_Rx_GetChA_UserData(), XSpdif_Rx_GetChB_UserData(), XSpdif_Rx_GetChStat(), and XSpdif_SetClkConfig().
#define XSPDIF_SAMPLE_CLOCK_COUNT_MASK ((0X3FF) << XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT) |
XSPDIF sample clock count mask.
Referenced by XSpdif_GetFs().
#define XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT (0) |
XSPDIF sample clock count shift.
#define XSPDIF_SOFT_RESET_REGISTER_OFFSET 0x40 |
Soft Reset Register.
Referenced by XSpdif_SoftReset().
#define XSPDIF_SOFT_RESET_REGISTER_VALUE 0X0A |
Soft Reset Register value to reset.
Referenced by XSpdif_SoftReset().
#define XSPDIF_START_OF_BLOCK_MASK (1 << XSPDIF_START_OF_BLOCK_SHIFT) |
Transmitter or Receiver FIFO Full Interrupt bit shift.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_START_OF_BLOCK_SHIFT (2) |
Start of Block Interrupt bit mask ( in Receive mode)
#define XSPDIF_STATUS_REGISTER_OFFSET 0x48 |
Status Register.
Referenced by XSpdif_GetFs().
#define XSPDIF_TX_OR_RX_FIFO_EMPTY_MASK (1 << XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT) |
Transmitter or Receiver FIFO Empty Interrupt bit mask.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT (1) |
Transmitter or Receiver FIFO Empty Interrupt bit shift.
#define XSPDIF_TX_OR_RX_FIFO_FULL_MASK (1 << XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT) |
Transmitter or Receiver FIFO Full Interrupt bit mask.
Referenced by XSpdif_IntrHandler().
#define XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT (0) |
Transmitter or Receiver FIFO Full Interrupt bit shift.
#define XSpdif_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
Data | |||
) | XSpdif_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) |
This macro writes a value to a XSpdif register.
A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.
BaseAddress | is the base address of the XSpdif core instance. |
RegOffset | is the register offset of the register (defined at the top of this file) to be written. |
Data | is the 32-bit value to write into the register. |
Referenced by XSpdif_Enable(), XSpdif_ResetFifo(), XSpdif_SetClkConfig(), and XSpdif_SoftReset().
int XSpdif_CfgInitialize | ( | XSpdif * | InstancePtr, |
XSpdif_Config * | CfgPtr, | ||
UINTPTR | EffectiveAddr | ||
) |
This function initializes the XSpdif.
This function must be called prior to using the core. Initialization of the XSpdif includes setting up the instance data, and ensuring the hardware is in a quiescent state.
InstancePtr | is a pointer to the XSpdif instance. |
CfgPtr | points to the configuration structure associated with the XSpdif. |
EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSpdif::IsReady, and XSpdif_Enable().
Referenced by SpdifSelfTestExample(), and XSpdif_Initialize().
void XSpdif_Enable | ( | XSpdif * | InstancePtr, |
u8 | Enable | ||
) |
This function enables/disables the XSpdif.
InstancePtr | is a pointer to the XSpdif instance. |
Enable | specifies TRUE/FALSE value to either enable or disable the XSpdif. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSpdif::IsStarted, XSPDIF_CONTROL_REGISTER_OFFSET, XSPDIF_CORE_ENABLE_MASK, XSpdif_ReadReg, and XSpdif_WriteReg.
Referenced by XSpdif_CfgInitialize().
u32 XSpdif_GetFs | ( | XSpdif * | InstancePtr, |
u32 | AudClk | ||
) |
This function calculates the Sampling Frequency (Fs) and returns it's value.
InstancePtr | is a pointer to the XSpdif instance. |
AudClk | is the audio clock frequency value in Hz. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSpdif_ReadReg, XSPDIF_SAMPLE_CLOCK_COUNT_MASK, and XSPDIF_STATUS_REGISTER_OFFSET.
int XSpdif_Initialize | ( | XSpdif * | InstancePtr, |
u16 | DeviceId | ||
) |
Initializes a specific Xspdif instance such that the driver is ready to use.
InstancePtr | is a pointer to the XSpdif instance to be worked on. |
DeviceId | is the unique id of the device controlled by this XSpdif instance. Passing in a device id associates the generic XSpdif instance to a specific device, as chosen by the caller or application developer. |
References XSpdif_Config::BaseAddress, XSpdif_CfgInitialize(), and XSpdif_LookupConfig().
void XSpdif_IntrHandler | ( | void * | InstancePtr | ) |
This function is the interrupt handler for the XSpdif driver.
This handler reads the pending interrupt from the XSpdif peripheral, determines the source of the interrupts, clears the interrupts and calls call backs accordingly.
InstancePtr | is a pointer to the XSpdif instance. |
References XSpdif_Config::BaseAddress, XSpdif::BmcErrHandler, XSpdif::BmcErrHandlerRef, XSpdif::Config, XSpdif::IsReady, XSpdif::PreambleErrHandler, XSpdif::PreambleErrHandlerRef, XSpdif::StartOfBlockHandler, XSpdif::StartOfBlockHandlerRef, XSpdif::TxOrRxFifoEmptyHandler, XSpdif::TxOrRxFifoEmptyHandlerRef, XSpdif::TxOrRxFifoFullHandler, XSpdif::TxOrRxFifoFullHandlerRef, XSPDIF_BMC_ERROR_MASK, XSPDIF_INTERRUPT_ENABLE_REGISTER_OFFSET, XSPDIF_INTERRUPT_STATUS_REGISTER_OFFSET, XSPDIF_PREAMBLE_ERROR_MASK, XSpdif_ReadReg, XSPDIF_START_OF_BLOCK_MASK, XSPDIF_TX_OR_RX_FIFO_EMPTY_MASK, and XSPDIF_TX_OR_RX_FIFO_FULL_MASK.
XSpdif_Config* XSpdif_LookupConfig | ( | u16 | DeviceId | ) |
This function returns a reference to an XSpdif_Config structure based on the core id, DeviceId.
The return value will refer to an entry in the device configuration table defined in the xspdif_g.c file.
DeviceId | is the unique core ID of the XSpdif core for the lookup operation. |
Referenced by SpdifSelfTestExample(), and XSpdif_Initialize().
void XSpdif_ResetFifo | ( | XSpdif * | InstancePtr | ) |
This function resets the Fifo.
InstancePtr | is a pointer to the XSpdif instance. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_CONTROL_REGISTER_OFFSET, XSPDIF_CORE_ENABLE_MASK, XSpdif_ReadReg, and XSpdif_WriteReg.
void XSpdif_Rx_GetChA_UserData | ( | XSpdif * | InstancePtr, |
u8 * | ChA_UserDataBuf | ||
) |
This function reads the Channel A user data and writes to a buffer.
InstancePtr | is a pointer to the XSPDIF instance. |
ChA_UserDataBuf | is a pointer to a buffer. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_CHANNEL_A_USER_DATA_REGISTER0_OFFSET, and XSpdif_ReadReg.
void XSpdif_Rx_GetChB_UserData | ( | XSpdif * | InstancePtr, |
u8 * | ChB_UserDataBuf | ||
) |
This function reads the Channel B user data and writes to a buffer.
InstancePtr | is a pointer to the XSPDIF instance. |
ChB_UserDataBuf | is a pointer to a buffer. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_CHANNEL_B_USER_DATA_REGISTER0_OFFSET, and XSpdif_ReadReg.
void XSpdif_Rx_GetChStat | ( | XSpdif * | InstancePtr, |
u8 * | ChStatBuf | ||
) |
This function reads all the Channel Status registers and writes to a buffer.
InstancePtr | is a pointer to the XSpdif instance. |
ChStatBuf | is a pointer to a buffer. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_CHANNEL_STATUS_REGISTER0_OFFSET, and XSpdif_ReadReg.
void XSpdif_SetClkConfig | ( | XSpdif * | InstancePtr, |
u8 | Clk_DivNum | ||
) |
This function sets the clock configuration bits.
InstancePtr | is a pointer to the Spdif instance. |
Clk_DivNum | is the clock division number. Clk_DivNum value can be only 4,8,16,24,32,48,or 64. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_CLK_16, XSPDIF_CLK_24, XSPDIF_CLK_32, XSPDIF_CLK_4, XSPDIF_CLK_48, XSPDIF_CLK_64, XSPDIF_CLK_8, XSPDIF_CLOCK_CONFIG_BITS_MASK, XSPDIF_CLOCK_CONFIG_BITS_SHIFT, XSPDIF_CONTROL_REGISTER_OFFSET, XSpdif_ReadReg, and XSpdif_WriteReg.
int XSpdif_SetHandler | ( | XSpdif * | InstancePtr, |
XSpdif_HandlerType | HandlerType, | ||
XSpdif_Callback | FuncPtr, | ||
void * | CallbackRef | ||
) |
This function installs an asynchronous callback function for the given HandlerType:
HandlerType Callback Function -------------------------------- ---------------------------------- (XSPDIF_HANDLER_START_OF_BLOCK) StartOfBlockHandler (XSPDIF_HANDLE_PREAMBLE_ERROR) PreambleErrHandler (XSPDIF_HANDLE_BMC_ERROR) BmcErrHandler (XSPDIF_HANDLER_TX_OR_RX_FIFO_EMPTY) TxOrRxFifoEmptyHandler (XSPDIF_HANDLER_TX_OR_RX_FIFO_FULL) TxOrRxFifoFullHandler
InstancePtr | is a pointer to the XSpdif core instance. |
HandlerType | specifies the type of handler. |
FuncPtr | is a pointer to the callback function. |
CallbackRef | is a reference pointer passed on actual calling of the callback function. |
References XSpdif::BmcErrHandler, XSpdif::BmcErrHandlerRef, XSpdif::PreambleErrHandler, XSpdif::PreambleErrHandlerRef, XSpdif::StartOfBlockHandler, XSpdif::StartOfBlockHandlerRef, XSpdif::TxOrRxFifoEmptyHandler, XSpdif::TxOrRxFifoEmptyHandlerRef, XSpdif::TxOrRxFifoFullHandler, XSpdif::TxOrRxFifoFullHandlerRef, XSPDIF_HANDLER_BMC_ERROR, XSPDIF_HANDLER_PREAMBLE_ERROR, XSPDIF_HANDLER_START_OF_BLOCK, XSPDIF_HANDLER_TX_OR_RX_FIFO_EMPTY, XSPDIF_HANDLER_TX_OR_RX_FIFO_FULL, and XSPDIF_NUM_HANDLERS.
void XSpdif_SoftReset | ( | XSpdif * | InstancePtr | ) |
This function is used to soft reset the interrupt registers.
InstancePtr | is a pointer to the XSPDIF instance. |
References XSpdif_Config::BaseAddress, XSpdif::Config, XSPDIF_SOFT_RESET_REGISTER_OFFSET, XSPDIF_SOFT_RESET_REGISTER_VALUE, and XSpdif_WriteReg.