v_hdmiphy1
Xilinx SDK Drivers API Documentation
XHdmiphy1_Channel Struct Reference

This typedef contains configuration information for PLL type and its reference clock. More...

Data Fields

u64 LineRateHz
 
     The line rate for the

channel. More...

 
u8 RxDataWidth
 In bits. More...
 
u8 RxIntDataWidth
 In bytes. More...
 
u8 TxDataWidth
 In bits. More...
 
u8 TxIntDataWidth
 In bytes. More...
 
XHdmiphy1_PllParam CpllParams
 Parameters for a CPLL. More...
 
XHdmiphy1_PllRefClkSelType CpllRefClkSel
 Multiplexer selection for the reference clock of the CPLL. More...
 
u8 RxOutDiv
 
     Output clock divider D for

the RX datapath. More...

 
u8 TxOutDiv
 
     Output clock divider D for

the TX datapath. More...

 
XHdmiphy1_GtState RxState
 Current state of RX GT. More...
 
XHdmiphy1_GtState TxState
 Current state of TX GT. More...
 
XHdmiphy1_ProtocolType RxProtocol
 The protocol which the RX path is used for. More...
 
XHdmiphy1_ProtocolType TxProtocol
 The protocol which the TX path is used for. More...
 
XHdmiphy1_SysClkDataSelType RxDataRefClkSel
 Multiplexer selection for the reference clock of the RX datapath. More...
 
XHdmiphy1_SysClkDataSelType TxDataRefClkSel
 Multiplexer selection for the reference clock of the TX datapath. More...
 
XHdmiphy1_SysClkOutSelType RxOutRefClkSel
 Multiplexer selection for the reference clock of the RX output clock. More...
 
XHdmiphy1_SysClkOutSelType TxOutRefClkSel
 Multiplexer selection for the reference clock of the TX output clock. More...
 
XHdmiphy1_OutClkSelType RxOutClkSel
 Multiplexer selection for which clock to use as the RX output clock. More...
 
XHdmiphy1_OutClkSelType TxOutClkSel
 Multiplexer selection for which clock to use as the TX output clock. More...
 
u8 RxDelayBypass
 
     Bypasses the delay

alignment block for the RX output clock. More...

 
u8 TxDelayBypass
 
     Bypasses the delay

alignment block for the TX output clock. More...

 

Detailed Description

This typedef contains configuration information for PLL type and its reference clock.

Field Documentation

XHdmiphy1_PllParam XHdmiphy1_Channel::CpllParams

Parameters for a CPLL.

XHdmiphy1_PllRefClkSelType XHdmiphy1_Channel::CpllRefClkSel

Multiplexer selection for the reference clock of the CPLL.

Referenced by XHdmiphy1_WriteCfgRefClkSelReg().

u64 XHdmiphy1_Channel::LineRateHz
XHdmiphy1_SysClkDataSelType XHdmiphy1_Channel::RxDataRefClkSel

Multiplexer selection for the reference clock of the RX datapath.

Referenced by XHdmiphy1_HdmiDebugInfo(), and XHdmiphy1_WriteCfgRefClkSelReg().

u8 XHdmiphy1_Channel::RxDataWidth

In bits.

Referenced by XHdmiphy1_HdmiQpllParam().

u8 XHdmiphy1_Channel::RxDelayBypass

     Bypasses the delay

alignment block for the RX output clock.

u8 XHdmiphy1_Channel::RxIntDataWidth

In bytes.

Referenced by XHdmiphy1_HdmiQpllParam().

XHdmiphy1_OutClkSelType XHdmiphy1_Channel::RxOutClkSel

Multiplexer selection for which clock to use as the RX output clock.

u8 XHdmiphy1_Channel::RxOutDiv

     Output clock divider D for

the RX datapath.

Referenced by XHdmiphy1_DruCalcCenterFreqHz(), and XHdmiphy1_HdmiDebugInfo().

XHdmiphy1_SysClkOutSelType XHdmiphy1_Channel::RxOutRefClkSel

Multiplexer selection for the reference clock of the RX output clock.

Referenced by XHdmiphy1_WriteCfgRefClkSelReg().

XHdmiphy1_ProtocolType XHdmiphy1_Channel::RxProtocol

The protocol which the RX path is used for.

XHdmiphy1_SysClkDataSelType XHdmiphy1_Channel::TxDataRefClkSel

Multiplexer selection for the reference clock of the TX datapath.

Referenced by XHdmiphy1_HdmiDebugInfo(), and XHdmiphy1_WriteCfgRefClkSelReg().

u8 XHdmiphy1_Channel::TxDataWidth

In bits.

u8 XHdmiphy1_Channel::TxDelayBypass

     Bypasses the delay

alignment block for the TX output clock.

u8 XHdmiphy1_Channel::TxIntDataWidth

In bytes.

XHdmiphy1_OutClkSelType XHdmiphy1_Channel::TxOutClkSel

Multiplexer selection for which clock to use as the TX output clock.

u8 XHdmiphy1_Channel::TxOutDiv

     Output clock divider D for

the TX datapath.

Referenced by XHdmiphy1_HdmiDebugInfo(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().

XHdmiphy1_SysClkOutSelType XHdmiphy1_Channel::TxOutRefClkSel

Multiplexer selection for the reference clock of the TX output clock.

Referenced by XHdmiphy1_WriteCfgRefClkSelReg().

XHdmiphy1_ProtocolType XHdmiphy1_Channel::TxProtocol

The protocol which the TX path is used for.