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csi2tx
Xilinx SDK Drivers API Documentation
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The configuration structure for CSI Controller. More...
Data Fields | |
u32 | DeviceId |
Device Id. More... | |
UINTPTR | BaseAddr |
Base address of CSI2 Rx Controller. More... | |
u32 | MaxLanesPresent |
Max value of Lanes. More... | |
u32 | ActiveLanes |
Number of Lanes configured. More... | |
u32 | FEGenEnabled |
Frame End generation enabled. More... | |
The configuration structure for CSI Controller.
This structure passes the hardware building information to the driver
u32 XCsi2Tx_Config::ActiveLanes |
Number of Lanes configured.
Range 0 - 3
UINTPTR XCsi2Tx_Config::BaseAddr |
Base address of CSI2 Rx Controller.
Referenced by Csi2TxSelfTestExample(), XCsi2Tx_CfgInitialize(), XCsi2Tx_Configure(), XCsi2Tx_GetIntrEnable(), XCsi2Tx_GetIntrStatus(), XCsi2Tx_GetLineCountForVC(), XCsi2Tx_GetShortPacket(), XCsi2Tx_InterruptClear(), XCsi2Tx_IntrDisable(), XCsi2Tx_IntrEnable(), XCsi2Tx_SelfTest(), and XCsi2Tx_SetLineCountForVC().
u32 XCsi2Tx_Config::DeviceId |
Device Id.
u32 XCsi2Tx_Config::FEGenEnabled |
Frame End generation enabled.
Referenced by XCsi2Tx_GetLineCountForVC(), XCsi2Tx_InterruptClear(), XCsi2Tx_IntrDisable(), XCsi2Tx_IntrEnable(), XCsi2Tx_IntrHandler(), and XCsi2Tx_SetLineCountForVC().
u32 XCsi2Tx_Config::MaxLanesPresent |
Max value of Lanes.
Range 0 - 3
Referenced by XCsi2Tx_IsActiveLaneCountValid(), and XCsi2Tx_SelfTest().