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v_hdmiphy1
Xilinx SDK Drivers API Documentation
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Contains generic APIs that are locally called or used within the HDMIPHY driver.
MODIFICATION HISTORY:
Ver Who Date Changes
dd/mm/yy
1.0 gm 10/12/18 Initial release.
Functions | |
void | XHdmiphy1_Ch2Ids (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 *Id0, u8 *Id1) |
This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More... | |
u32 | XHdmiphy1_DirReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function will set the current RX/TX configuration over DRP. More... | |
u32 | XHdmiphy1_WriteCfgRefClkSelReg (XHdmiphy1 *InstancePtr, u8 QuadId) |
This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels. More... | |
void | XHdmiphy1_CfgPllRefClkSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_PllRefClkSelType RefClkSel) |
Configure the PLL reference clock selection for the specified channel(s). More... | |
void | XHdmiphy1_CfgSysClkDataSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_SysClkDataSelType SysClkDataSel) |
Configure the SYSCLKDATA reference clock selection for the direction. More... | |
void | XHdmiphy1_CfgSysClkOutSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_SysClkOutSelType SysClkOutSel) |
Configure the SYSCLKOUT reference clock selection for the direction. More... | |
XHdmiphy1_ChannelId | XHdmiphy1_GetRcfgChId (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_PllType PllType) |
Obtain the reconfiguration channel ID for given PLL type. More... | |
u32 | XHdmiphy1_IsPllLocked (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will check the status of a PLL lock on the specified channel. More... | |
u32 | XHdmiphy1_GetQuadRefClkFreq (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_PllRefClkSelType RefClkType) |
Obtain the current reference clock frequency for the quad based on the reference clock type. More... | |
XHdmiphy1_SysClkDataSelType | XHdmiphy1_GetSysClkDataSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the current [RT]XSYSCLKSEL[0] configuration. More... | |
XHdmiphy1_SysClkOutSelType | XHdmiphy1_GetSysClkOutSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the current [RT]XSYSCLKSEL[1] configuration. More... | |
u32 | XHdmiphy1_GtUserRdyEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset and enable the Video PHY's user core logic. More... | |
void | XHdmiphy1_MmcmReset (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmLockedMaskEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function will reset the mixed-mode clock manager (MMCM) core. More... | |
u8 | XHdmiphy1_MmcmLocked (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will get the lock status of the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmSetClkinsel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_MmcmClkinsel Sel) |
This function will set the CLKINSEL port of the MMCM. More... | |
void | XHdmiphy1_SetBufgGtDiv (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Div) |
This function obtains the divider value of the BUFG_GT peripheral. More... | |
u32 | XHdmiphy1_PowerDownGtPll (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Hold) |
This function will power down the specified GT PLL. More... | |
u32 | XHdmiphy1_ClkCalcParams (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More... | |
u32 | XHdmiphy1_OutDivReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function will set the current output divider configuration over DRP. More... | |
u32 | XHdmiphy1_ClkReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance. More... | |
XHdmiphy1_SysClkDataSelType | Pll2SysClkData (XHdmiphy1_PllType PllSelect) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkDataSelType. More... | |
XHdmiphy1_SysClkOutSelType | Pll2SysClkOut (XHdmiphy1_PllType PllSelect) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkOutSelType. More... | |
u32 | XHdmiphy1_PllCalculator (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More... | |
u64 | XHdmiphy1_GetPllVcoFreqHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function calculates the PLL VCO operating frequency. More... | |
u8 | XHdmiphy1_GetRefClkSourcesCount (XHdmiphy1 *InstancePtr) |
This function returns the number of active reference clock sources based in the CFG. More... | |
u8 | XHdmiphy1_IsHDMI (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function checks if Instance is HDMI 2.0 or HDMI 2.1. More... | |
void | XHdmiphy1_ErrorHandler (XHdmiphy1 *InstancePtr) |
This function is the error condition handler. More... | |