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i2stx
Xilinx SDK Drivers API Documentation
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Macros | |
#define | XI2s_Tx_GetMaxChannels(InstancePtr) |
This macro reads the maximum number of I2S channels available. More... | |
#define | XI2s_Tx_IsI2sMaster(InstancePtr) |
This macro returns the I2S operating mode. More... | |
Functions | |
void | XI2s_Tx_ReslveAesChStat (u8 I2stx_SrcBuf[]) |
This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them. More... | |
int | XI2s_Tx_SelfTest (XI2s_Tx *InstancePtr) |
Runs a self-test on the driver/device. More... | |
XI2stx_Config * | XI2s_Tx_LookupConfig (u16 DeviceId) |
This function returns a reference to an XI2stx_Config structure based on the core id, DeviceId. More... | |
Register Map | |
#define | XI2S_TX_CORE_VER_OFFSET 0x00 |
Core Version Register. More... | |
#define | XI2S_TX_CORE_CFG_OFFSET 0x04 |
Core Configuration Register. More... | |
#define | XI2S_TX_CORE_CTRL_OFFSET 0x08 |
Core Control Register. More... | |
#define | XI2S_TX_IRQCTRL_OFFSET 0x10 |
Interrupt Control Register. More... | |
#define | XI2S_TX_IRQSTS_OFFSET 0x14 |
Interrupt Status Register. More... | |
#define | XI2S_TX_TMR_CTRL_OFFSET 0x20 |
I2S Timing Control Register. More... | |
#define | XI2S_TX_CH01_OFFSET 0x30 |
Audio Channel 0/1 Control Register. More... | |
#define | XI2S_TX_CH23_OFFSET 0x34 |
Audio Channel 2/3 Control Register. More... | |
#define | XI2S_TX_CH45_OFFSET 0x38 |
Audio Channel 4/5 Control Register. More... | |
#define | XI2S_TX_CH67_OFFSET 0x3C |
Audio Channel 6/7 Control Register. More... | |
#define | XI2S_TX_AES_CHSTS0_OFFSET 0x50 |
AES Channel Status 0 Register. More... | |
#define | XI2S_TX_AES_CHSTS1_OFFSET 0x54 |
AES Channel Status 1 Register. More... | |
#define | XI2S_TX_AES_CHSTS2_OFFSET 0x58 |
AES Channel Status 2 Register. More... | |
#define | XI2S_TX_AES_CHSTS3_OFFSET 0x5C |
AES Channel Status 3 Register. More... | |
#define | XI2S_TX_AES_CHSTS4_OFFSET 0x60 |
AES Channel Status 4 Register. More... | |
#define | XI2S_TX_AES_CHSTS5_OFFSET 0x64 |
AES Channel Status 5 Register. More... | |
Core Configuration Register masks and shifts | |
#define | XI2S_TX_REG_CFG_MSTR_SHIFT (0) |
Is I2S Master bit shift. More... | |
#define | XI2S_TX_REG_CFG_MSTR_MASK (1 << XI2S_TX_REG_CFG_MSTR_SHIFT) |
Is I2S Master mask. More... | |
#define | XI2S_TX_REG_CFG_NUM_CH_SHIFT (8) |
Maximum number of channels bit shift. More... | |
#define | XI2S_TX_REG_CFG_NUM_CH_MASK (0xF << XI2S_TX_REG_CFG_NUM_CH_SHIFT) |
Maximum number of channels mask. More... | |
#define | XI2S_TX_REG_CFG_DWDTH_SHIFT (16) |
I2S Data Width bit shift. More... | |
#define | XI2S_TX_REG_CFG_DWDTH_MASK (1 << XI2S_TX_REG_CFG_DWDTH_SHIFT) |
I2S Data Width mask. More... | |
Core Control Register masks and shifts | |
#define | XI2S_TX_REG_CTRL_EN_SHIFT (0) |
Module Enable bit shift. More... | |
#define | XI2S_TX_REG_CTRL_EN_MASK (1 << XI2S_TX_REG_CTRL_EN_SHIFT) |
Module Enable mask. More... | |
#define | XI2S_TX_REG_CTRL_JFE_SHIFT (1) |
Justification Enable or Disable shift. More... | |
#define | XI2S_TX_REG_CTRL_JFE_MASK (1 << XI2S_TX_REG_CTRL_JFE_SHIFT) |
Justification Enable or Disable mask. More... | |
#define | XI2S_TX_REG_CTRL_LORJF_SHIFT (2) |
Left or Right Justification shift. More... | |
#define | XI2S_TX_REG_CTRL_LORJF_MASK (1 << XI2S_TX_REG_CTRL_LORJF_SHIFT) |
Left or Right Justification mask. More... | |
Interrupt masks and shifts | |
#define | XI2S_TX_INTR_AES_BLKCMPLT_SHIFT (0) |
AES Block Complete Interrupt bit shift. More... | |
#define | XI2S_TX_INTR_AES_BLKCMPLT_MASK (1 << XI2S_TX_INTR_AES_BLKCMPLT_SHIFT) |
AES Block Complete Interrupt mask. More... | |
#define | XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT (1) |
AES Block Synchronization Error Interrupt bit shift. More... | |
#define | XI2S_TX_INTR_AES_BLKSYNCERR_MASK (1 << XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT) |
AES Block Synchronization Error Interrupt mask. More... | |
#define | XI2S_TX_INTR_AES_CHSTSUPD_SHIFT (2) |
AES Channel Status Updated Interrupt bit shift. More... | |
#define | XI2S_TX_INTR_AES_CHSTSUPD_MASK (1 << XI2S_TX_INTR_AES_CHSTSUPD_SHIFT) |
AES Channel Status Updated Interrupt mask. More... | |
#define | XI2S_TX_INTR_AUDUNDRFLW_SHIFT (3) |
Audio Underflow Detected Interrupt bit shift. More... | |
#define | XI2S_TX_INTR_AUDUNDRFLW_MASK (1 << XI2S_TX_INTR_AUDUNDRFLW_SHIFT) |
Audio Underflow Detected Interrupt mask. More... | |
#define | XI2S_TX_GINTR_EN_SHIFT (31) |
Global Interrupt Enable bit shift. More... | |
#define | XI2S_TX_GINTR_EN_MASK (1 << XI2S_TX_GINTR_EN_SHIFT) |
Global Interrupt Enable mask. More... | |
I2S Timing Control Register masks and shifts | |
#define | XI2S_TX_REG_TMR_SCLKDIV_SHIFT (0) |
SClk Divider bit shift. More... | |
#define | XI2S_TX_REG_TMR_SCLKDIV_MASK (0xF << XI2S_TX_REG_TMR_SCLKDIV_SHIFT) |
SClk Divider mask. More... | |
Audio Channel Control Register masks and shifts | |
#define | XI2S_TX_REG_CHCTRL_CHMUX_SHIFT (0) |
Channel MUX bit shift. More... | |
#define | XI2S_TX_REG_CHCTRL_CHMUX_MASK (0x7 << XI2S_TX_REG_CHCTRL_CHMUX_SHIFT) |
Channel MUX mask. More... | |
Register access macro definition | |
#define | XI2s_Tx_In32 Xil_In32 |
Input Operations. More... | |
#define | XI2s_Tx_Out32 Xil_Out32 |
Output Operations. More... | |
#define | XI2s_Tx_ReadReg(BaseAddress, RegOffset) XI2s_Tx_In32((BaseAddress) + ((u32)RegOffset)) |
This macro reads a value from a I2S Transmitter register. More... | |
#define | XI2s_Tx_WriteReg(BaseAddress, RegOffset, Data) XI2s_Tx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) |
This macro writes a value to a I2S Transmitter register. More... | |
#define XI2S_TX_AES_CHSTS0_OFFSET 0x50 |
AES Channel Status 0 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs(), and XI2s_Tx_GetAesChStatus().
#define XI2S_TX_AES_CHSTS1_OFFSET 0x54 |
AES Channel Status 1 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs().
#define XI2S_TX_AES_CHSTS2_OFFSET 0x58 |
AES Channel Status 2 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs().
#define XI2S_TX_AES_CHSTS3_OFFSET 0x5C |
AES Channel Status 3 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs().
#define XI2S_TX_AES_CHSTS4_OFFSET 0x60 |
AES Channel Status 4 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs().
#define XI2S_TX_AES_CHSTS5_OFFSET 0x64 |
AES Channel Status 5 Register.
Referenced by XI2s_Tx_ClrAesChStatRegs().
#define XI2S_TX_CH01_OFFSET 0x30 |
Audio Channel 0/1 Control Register.
Referenced by XI2s_Tx_SetChMux().
#define XI2S_TX_CH23_OFFSET 0x34 |
Audio Channel 2/3 Control Register.
#define XI2S_TX_CH45_OFFSET 0x38 |
Audio Channel 4/5 Control Register.
#define XI2S_TX_CH67_OFFSET 0x3C |
Audio Channel 6/7 Control Register.
#define XI2S_TX_CORE_CFG_OFFSET 0x04 |
Core Configuration Register.
#define XI2S_TX_CORE_CTRL_OFFSET 0x08 |
Core Control Register.
Referenced by XI2s_Tx_Enable(), XI2s_Tx_Justify(), and XI2s_Tx_JustifyEnable().
#define XI2S_TX_CORE_VER_OFFSET 0x00 |
Core Version Register.
#define XI2s_Tx_GetMaxChannels | ( | InstancePtr | ) |
This macro reads the maximum number of I2S channels available.
InstancePtr | is a pointer to the XI2s_Tx core instance. |
Referenced by XI2s_Tx_SelfTest().
#define XI2S_TX_GINTR_EN_MASK (1 << XI2S_TX_GINTR_EN_SHIFT) |
Global Interrupt Enable mask.
Referenced by I2sTxIntrExample().
#define XI2S_TX_GINTR_EN_SHIFT (31) |
Global Interrupt Enable bit shift.
#define XI2s_Tx_In32 Xil_In32 |
Input Operations.
#define XI2S_TX_INTR_AES_BLKCMPLT_MASK (1 << XI2S_TX_INTR_AES_BLKCMPLT_SHIFT) |
AES Block Complete Interrupt mask.
Referenced by I2sTxIntrExample(), and XI2s_Tx_IntrHandler().
#define XI2S_TX_INTR_AES_BLKCMPLT_SHIFT (0) |
AES Block Complete Interrupt bit shift.
#define XI2S_TX_INTR_AES_BLKSYNCERR_MASK (1 << XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT) |
AES Block Synchronization Error Interrupt mask.
Referenced by XI2s_Tx_IntrHandler().
#define XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT (1) |
AES Block Synchronization Error Interrupt bit shift.
#define XI2S_TX_INTR_AES_CHSTSUPD_MASK (1 << XI2S_TX_INTR_AES_CHSTSUPD_SHIFT) |
AES Channel Status Updated Interrupt mask.
Referenced by XI2s_Tx_IntrHandler().
#define XI2S_TX_INTR_AES_CHSTSUPD_SHIFT (2) |
AES Channel Status Updated Interrupt bit shift.
#define XI2S_TX_INTR_AUDUNDRFLW_MASK (1 << XI2S_TX_INTR_AUDUNDRFLW_SHIFT) |
Audio Underflow Detected Interrupt mask.
Referenced by I2sTxIntrExample(), and XI2s_Tx_IntrHandler().
#define XI2S_TX_INTR_AUDUNDRFLW_SHIFT (3) |
Audio Underflow Detected Interrupt bit shift.
#define XI2S_TX_IRQCTRL_OFFSET 0x10 |
Interrupt Control Register.
Referenced by XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), and XI2s_Tx_IntrHandler().
#define XI2S_TX_IRQSTS_OFFSET 0x14 |
Interrupt Status Register.
Referenced by XI2s_Tx_IntrHandler().
#define XI2s_Tx_IsI2sMaster | ( | InstancePtr | ) |
This macro returns the I2S operating mode.
InstancePtr | is a pointer to the XI2s_Tx core instance. |
Referenced by XI2s_Tx_SelfTest().
#define XI2s_Tx_Out32 Xil_Out32 |
Output Operations.
#define XI2s_Tx_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XI2s_Tx_In32((BaseAddress) + ((u32)RegOffset)) |
This macro reads a value from a I2S Transmitter register.
A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.
BaseAddress | is the base address of the I2S Transmitter core instance. |
RegOffset | is the register offset of the register (defined at the top of this file). |
Referenced by XI2s_Tx_Enable(), XI2s_Tx_GetAesChStatus(), XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), XI2s_Tx_IntrHandler(), XI2s_Tx_Justify(), and XI2s_Tx_JustifyEnable().
#define XI2S_TX_REG_CFG_DWDTH_MASK (1 << XI2S_TX_REG_CFG_DWDTH_SHIFT) |
I2S Data Width mask.
#define XI2S_TX_REG_CFG_DWDTH_SHIFT (16) |
I2S Data Width bit shift.
#define XI2S_TX_REG_CFG_MSTR_MASK (1 << XI2S_TX_REG_CFG_MSTR_SHIFT) |
Is I2S Master mask.
#define XI2S_TX_REG_CFG_MSTR_SHIFT (0) |
Is I2S Master bit shift.
#define XI2S_TX_REG_CFG_NUM_CH_MASK (0xF << XI2S_TX_REG_CFG_NUM_CH_SHIFT) |
Maximum number of channels mask.
#define XI2S_TX_REG_CFG_NUM_CH_SHIFT (8) |
Maximum number of channels bit shift.
#define XI2S_TX_REG_CHCTRL_CHMUX_MASK (0x7 << XI2S_TX_REG_CHCTRL_CHMUX_SHIFT) |
Channel MUX mask.
#define XI2S_TX_REG_CHCTRL_CHMUX_SHIFT (0) |
Channel MUX bit shift.
#define XI2S_TX_REG_CTRL_EN_MASK (1 << XI2S_TX_REG_CTRL_EN_SHIFT) |
Module Enable mask.
Referenced by XI2s_Tx_Enable().
#define XI2S_TX_REG_CTRL_EN_SHIFT (0) |
Module Enable bit shift.
#define XI2S_TX_REG_CTRL_JFE_MASK (1 << XI2S_TX_REG_CTRL_JFE_SHIFT) |
Justification Enable or Disable mask.
Referenced by XI2s_Tx_JustifyEnable().
#define XI2S_TX_REG_CTRL_JFE_SHIFT (1) |
Justification Enable or Disable shift.
#define XI2S_TX_REG_CTRL_LORJF_MASK (1 << XI2S_TX_REG_CTRL_LORJF_SHIFT) |
Left or Right Justification mask.
Referenced by XI2s_Tx_Justify().
#define XI2S_TX_REG_CTRL_LORJF_SHIFT (2) |
Left or Right Justification shift.
#define XI2S_TX_REG_TMR_SCLKDIV_MASK (0xF << XI2S_TX_REG_TMR_SCLKDIV_SHIFT) |
SClk Divider mask.
#define XI2S_TX_REG_TMR_SCLKDIV_SHIFT (0) |
SClk Divider bit shift.
#define XI2S_TX_TMR_CTRL_OFFSET 0x20 |
I2S Timing Control Register.
Referenced by XI2s_Tx_SetSclkOutDiv().
#define XI2s_Tx_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
Data | |||
) | XI2s_Tx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data)) |
This macro writes a value to a I2S Transmitter register.
A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.
BaseAddress | is the base address of the I2S Transmitter core instance. |
RegOffset | is the register offset of the register (defined at the top of this file) to be written. |
Data | is the 32-bit value to write into the register. |
Referenced by XI2s_Tx_ClrAesChStatRegs(), XI2s_Tx_Enable(), XI2s_Tx_IntrDisable(), XI2s_Tx_IntrEnable(), XI2s_Tx_Justify(), XI2s_Tx_JustifyEnable(), XI2s_Tx_SetChMux(), and XI2s_Tx_SetSclkOutDiv().
XI2stx_Config* XI2s_Tx_LookupConfig | ( | u16 | DeviceId | ) |
This function returns a reference to an XI2stx_Config structure based on the core id, DeviceId.
The return value will refer to an entry in the device configuration table defined in the xi2stx_g.c file.
DeviceId | is the unique core ID of the I2S Transmitter core for the lookup operation. |
Referenced by I2sSelfTestExample(), and I2sTxIntrExample().
void XI2s_Tx_ReslveAesChStat | ( | u8 | I2stx_SrcBuf[] | ) |
This function reads the array I2stx_SrcBuf which has the values of all the I2S Transmitter AES status registers, extracts the required bits and prints them.
Before calling this API, Call API XI2s_Tx_GetAesChStatus.
I2stx_SrcBuf | is an array that contains the values of all the the AES Status registers. |
< use of channel status block
< linear PCM identification
< audio signal Pre-emphasis
< lock indication
< sampling frequency
< channel mode
< user bits management
< use of auxiliary sample bits
< source word length
< indication of alignment level
< channel mode
< Channel number 0
< Channel number 1
< multi channel1 mode number
< digital audio reference signal
< reserved but undefined
< sampling frequency
< sampling frequency scaling flag
< reserved but undefined
< Alphanumeric channel origin data
< Alphanumeric channel destination data
< Local sample address code
< Time-of-day sample address code
< Reliability flags
< Cyclic redundancy check character
References XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK, XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT, XI2S_TX_AES_STS_CH_MODE_MASK, XI2S_TX_AES_STS_CH_NUM0_MASK, XI2S_TX_AES_STS_CH_NUM1_MASK, XI2S_TX_AES_STS_CRC_CHAR_OFFSET, XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK, XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT, XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK, XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT, XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK, XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT, XI2S_TX_AES_STS_LOCK_INDICATION_MASK, XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT, XI2S_TX_AES_STS_MC_CH_MODE_MASK, XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK, XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT, XI2S_TX_AES_STS_MC_CH_MODE_SHIFT, XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET, XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK, XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT, XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT, XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT, XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK, XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT, XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK, XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT, XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK, XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK, XI2S_TX_AES_STS_USR_BITS_MGMT_MASK, and XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT.
int XI2s_Tx_SelfTest | ( | XI2s_Tx * | InstancePtr | ) |
Runs a self-test on the driver/device.
The self-test is reads the version register, configuration registers and verifies the values
InstancePtr | is a pointer to the XI2s_Tx instance. |
References XI2s_Tx_GetMaxChannels, and XI2s_Tx_IsI2sMaster.
Referenced by I2sSelfTestExample(), I2sTxIntrExample(), and XI2s_Tx_CfgInitialize().