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v_hdmiphy1
Xilinx SDK Drivers API Documentation
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This typedef contains configuration information for the Video PHY core. More...
Data Fields | |
u16 | DeviceId |
Device instance ID. More... | |
UINTPTR | BaseAddr |
The base address of the core instance. More... | |
XHdmiphy1_GtType | XcvrType |
HDMIPHY Transceiver Type. More... | |
u8 | TxChannels |
No. More... | |
u8 | RxChannels |
No. More... | |
XHdmiphy1_ProtocolType | TxProtocol |
Protocol which TX is used for. More... | |
XHdmiphy1_ProtocolType | RxProtocol |
Protocol which RX is used for. More... | |
XHdmiphy1_PllRefClkSelType | TxRefClkSel |
TX REFCLK selection. More... | |
XHdmiphy1_PllRefClkSelType | RxRefClkSel |
RX REFCLK selection. More... | |
XHdmiphy1_PllRefClkSelType | TxFrlRefClkSel |
TX FRL REFCLK selection. More... | |
XHdmiphy1_PllRefClkSelType | RxFrlRefClkSel |
RX FRL REFCLK selection. More... | |
XHdmiphy1_SysClkDataSelType | TxSysPllClkSel |
TX SYSCLK selection. More... | |
XHdmiphy1_SysClkDataSelType | RxSysPllClkSel |
RX SYSCLK selectino. More... | |
u8 | DruIsPresent |
A data recovery unit (DRU) exists in the design . More... | |
XHdmiphy1_PllRefClkSelType | DruRefClkSel |
DRU REFCLK selection. More... | |
XVidC_PixelsPerClock | Ppc |
Number of input pixels per clock. More... | |
u8 | TxBufferBypass |
TX Buffer Bypass is enabled in the design. More... | |
u8 | HdmiFastSwitch |
HDMI fast switching is enabled in the design. More... | |
u8 | TransceiverWidth |
Transceiver Width seeting in the design. More... | |
u32 | ErrIrq |
Error IRQ is enalbed in design. More... | |
u32 | AxiLiteClkFreq |
AXI Lite Clock Frequency in Hz. More... | |
u32 | DrpClkFreq |
DRP Clock Frequency in Hz. More... | |
u8 | UseGtAsTxTmdsClk |
Use 4th GT channel as TX TMDS clock. More... | |
This typedef contains configuration information for the Video PHY core.
u32 XHdmiphy1_Config::AxiLiteClkFreq |
AXI Lite Clock Frequency in Hz.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
UINTPTR XHdmiphy1_Config::BaseAddr |
The base address of the core instance.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_ClkDetCheckFreqZero(), XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetFreqReset(), XHdmiphy1_ClkDetGetRefClkFreqHz(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetSetFreqTimeout(), XHdmiphy1_ClkDetTimerClear(), XHdmiphy1_ClkDetTimerLoad(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_DruEnable(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_DruGetVersion(), XHdmiphy1_DruReset(), XHdmiphy1_DruSetCenterFreqHz(), XHdmiphy1_GetSysClkDataSel(), XHdmiphy1_GetSysClkOutSel(), XHdmiphy1_GetVersion(), XHdmiphy1_GtUserRdyEnable(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiDebugInfo(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxMmcmLockHandler(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_InterruptHandler(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_IsPllLocked(), XHdmiphy1_MmcmLocked(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmPowerDown(), XHdmiphy1_MmcmReset(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_PatgenEnable(), XHdmiphy1_PatgenSetRatio(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_RegisterDebug(), XHdmiphy1_ResetGtPll(), XHdmiphy1_ResetGtTxRx(), XHdmiphy1_SelfTest(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetPolarity(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), XHdmiphy1_TxAlignReset(), XHdmiphy1_TxAlignStart(), XHdmiphy1_TxPrbsForceError(), and XHdmiphy1_WriteCfgRefClkSelReg().
u16 XHdmiphy1_Config::DeviceId |
Device instance ID.
u32 XHdmiphy1_Config::DrpClkFreq |
DRP Clock Frequency in Hz.
u8 XHdmiphy1_Config::DruIsPresent |
A data recovery unit (DRU) exists in the design .
Referenced by XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiDebugInfo(), XHdmiphy1_HdmiQpllParam(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_IBufDsEnable().
XHdmiphy1_PllRefClkSelType XHdmiphy1_Config::DruRefClkSel |
DRU REFCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_IBufDsEnable().
u32 XHdmiphy1_Config::ErrIrq |
Error IRQ is enalbed in design.
u8 XHdmiphy1_Config::HdmiFastSwitch |
HDMI fast switching is enabled in the design.
XVidC_PixelsPerClock XHdmiphy1_Config::Ppc |
Number of input pixels per clock.
Referenced by XHdmiphy1_Hdmi21Config(), and XHdmiphy1_SetHdmiTxParam().
u8 XHdmiphy1_Config::RxChannels |
XHdmiphy1_PllRefClkSelType XHdmiphy1_Config::RxFrlRefClkSel |
RX FRL REFCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiRxTimerTimeoutHandler().
XHdmiphy1_ProtocolType XHdmiphy1_Config::RxProtocol |
Protocol which RX is used for.
Referenced by XHdmiphy1_GetRefClkSourcesCount(), and XHdmiphy1_IsHDMI().
XHdmiphy1_PllRefClkSelType XHdmiphy1_Config::RxRefClkSel |
RX REFCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_IBufDsEnable().
XHdmiphy1_SysClkDataSelType XHdmiphy1_Config::RxSysPllClkSel |
RX SYSCLK selectino.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetPllType(), and XHdmiphy1_HdmiUpdateClockSelection().
u8 XHdmiphy1_Config::TransceiverWidth |
Transceiver Width seeting in the design.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiCfgCalcMmcmParam(), XHdmiphy1_HdmiCpllParam(), and XHdmiphy1_HdmiQpllParam().
u8 XHdmiphy1_Config::TxBufferBypass |
TX Buffer Bypass is enabled in the design.
u8 XHdmiphy1_Config::TxChannels |
XHdmiphy1_PllRefClkSelType XHdmiphy1_Config::TxFrlRefClkSel |
TX FRL REFCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_Hdmi21Config(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
XHdmiphy1_ProtocolType XHdmiphy1_Config::TxProtocol |
Protocol which TX is used for.
Referenced by XHdmiphy1_GetRefClkSourcesCount(), and XHdmiphy1_IsHDMI().
XHdmiphy1_PllRefClkSelType XHdmiphy1_Config::TxRefClkSel |
TX REFCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetRefClkSourcesCount(), XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), and XHdmiphy1_IBufDsEnable().
XHdmiphy1_SysClkDataSelType XHdmiphy1_Config::TxSysPllClkSel |
TX SYSCLK selection.
Referenced by XHdmiphy1_CfgInitialize(), XHdmiphy1_GetPllType(), and XHdmiphy1_HdmiUpdateClockSelection().
u8 XHdmiphy1_Config::UseGtAsTxTmdsClk |
Use 4th GT channel as TX TMDS clock.
Referenced by XHdmiphy1_Ch2Ids(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
XHdmiphy1_GtType XHdmiphy1_Config::XcvrType |
HDMIPHY Transceiver Type.
Referenced by XHdmiphy1_Ch2Ids(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_GetSysClkDataSel(), XHdmiphy1_GetSysClkOutSel(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_SetTxVoltageSwing(), and XHdmiphy1_WriteCfgRefClkSelReg().