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v_hdmiphy1
Xilinx SDK Drivers API Documentation
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Data Structures | |
struct | XHdmiphy1_PllParam |
This typedef contains configuration information for CPLL/QPLL programming. More... | |
struct | XHdmiphy1_Channel |
This typedef contains configuration information for PLL type and its reference clock. More... | |
struct | XHdmiphy1_Mmcm |
This typedef contains configuration information for MMCM programming. More... | |
struct | XHdmiphy1_Quad |
This typedef represents a GT quad. More... | |
struct | XHdmiphy1_Log |
This typedef contains the logging mechanism for debug. More... | |
struct | XHdmiphy1_Hdmi21Cfg |
This typedef contains the HDMI 2.1 FRL configurations. More... | |
struct | XHdmiphy1_Config |
This typedef contains configuration information for the Video PHY core. More... | |
struct | XHdmiphy1 |
The XHdmiphy1 driver instance data. More... | |
Macros | |
#define | XHdmiphy1_ReadReg(BaseAddress, RegOffset) XHdmiphy1_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register. More... | |
#define | XHdmiphy1_WriteReg(BaseAddress, RegOffset, Data) XHdmiphy1_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register. More... | |
Typedefs | |
typedef void(* | XHdmiphy1_IntrHandler )(void *InstancePtr) |
Callback type which represents the handler for interrupts. More... | |
typedef void(* | XHdmiphy1_TimerHandler )(void *InstancePtr, u32 MicroSeconds) |
Callback type which represents a custom timer wait handler. More... | |
typedef void(* | XHdmiphy1_Callback )(void *CallbackRef) |
Generic callback type. More... | |
typedef u64(* | XHdmiphy1_LogCallback )(void *CallbackRef) |
Generic callback type. More... | |
typedef void(* | XHdmiphy1_ErrorCallback )(void *CallbackRef) |
Error callback type. More... | |
Functions | |
void | XHdmiphy1_CfgInitialize (XHdmiphy1 *InstancePtr, XHdmiphy1_Config *ConfigPtr, UINTPTR EffectiveAddr) |
This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure. More... | |
u32 | XHdmiphy1_PllInitialize (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_PllRefClkSelType QpllRefClkSel, XHdmiphy1_PllRefClkSelType CpllxRefClkSel, XHdmiphy1_PllType TxPllSelect, XHdmiphy1_PllType RxPllSelect) |
This function will initialize the PLL selection for a given channel. More... | |
u32 | XHdmiphy1_GetVersion (XHdmiphy1 *InstancePtr) |
This function will obtian the IP version. More... | |
void | XHdmiphy1_WaitUs (XHdmiphy1 *InstancePtr, u32 MicroSeconds) |
This function is the delay/sleep function for the XHdmiphy1 driver. More... | |
u32 | XHdmiphy1_CfgLineRate (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u64 LineRateHz) |
Configure the channel's line rate. More... | |
XHdmiphy1_PllType | XHdmiphy1_GetPllType (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the channel's PLL reference clock selection. More... | |
u64 | XHdmiphy1_GetLineRateHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will return the line rate in Hz for a given channel / quad. More... | |
u32 | XHdmiphy1_ResetGtPll (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the GT's PLL logic. More... | |
u32 | XHdmiphy1_ResetGtTxRx (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the GT's TX/RX logic. More... | |
u32 | XHdmiphy1_SetPolarity (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Polarity) |
This function will set/clear the TX/RX polarity bit. More... | |
u32 | XHdmiphy1_SetPrbsSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, XHdmiphy1_PrbsPattern Pattern) |
This function will set the TX/RXPRBSEL of the GT. More... | |
u32 | XHdmiphy1_TxPrbsForceError (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 ForceErr) |
This function will set the TX/RXPRBSEL of the GT. More... | |
void | XHdmiphy1_SetTxVoltageSwing (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Vs) |
This function will set the TX voltage swing value for a given channel. More... | |
void | XHdmiphy1_SetTxPreEmphasis (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Pe) |
This function will set the TX pre-emphasis value for a given channel. More... | |
void | XHdmiphy1_SetTxPostCursor (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Pc) |
This function will set the TX post-curosr value for a given channel. More... | |
void | XHdmiphy1_SetRxLpm (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function will enable or disable the LPM logic in the Video PHY core. More... | |
u32 | XHdmiphy1_DrpWr (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u16 Addr, u16 Val) |
This function will initiate a write DRP transaction. More... | |
u16 | XHdmiphy1_DrpRd (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u16 Addr, u16 *RetVal) |
This function will initiate a read DRP transaction. More... | |
void | XHdmiphy1_MmcmPowerDown (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will power down the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmStart (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will start the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_IBufDsEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function enables the TX or RX IBUFDS peripheral. More... | |
void | XHdmiphy1_Clkout1OBufTdsEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function enables the TX or RX CLKOUT1 OBUFTDS peripheral. More... | |
void | XHdmiphy1_SetErrorCallback (XHdmiphy1 *InstancePtr, void *CallbackFunc, void *CallbackRef) |
This function installs a callback function for the HDMIPHY error conditions. More... | |
void | XHdmiphy1_SetLogCallback (XHdmiphy1 *InstancePtr, u64 *CallbackFunc, void *CallbackRef) |
This function installs an asynchronous callback function for the LogWrite API: More... | |
void | XHdmiphy1_LogDisplay (XHdmiphy1 *InstancePtr) |
This function will print the entire log. More... | |
void | XHdmiphy1_LogReset (XHdmiphy1 *InstancePtr) |
This function will reset the driver's logginc mechanism. More... | |
u16 | XHdmiphy1_LogRead (XHdmiphy1 *InstancePtr) |
This function will read the last event from the log. More... | |
void | XHdmiphy1_LogWrite (XHdmiphy1 *InstancePtr, XHdmiphy1_LogEvent Evt, u8 Data) |
This function will insert an event in the driver's logginc mechanism. More... | |
void | XHdmiphy1_InterruptHandler (XHdmiphy1 *InstancePtr) |
This function is the interrupt handler for the XHdmiphy1 driver. More... | |
u32 | XHdmiphy1_SelfTest (XHdmiphy1 *InstancePtr) |
This function runs a self-test on the XHdmiphy1 driver/device. More... | |
XHdmiphy1_Config * | XHdmiphy1_LookupConfig (u16 DeviceId) |
This function looks for the device configuration based on the unique device ID. More... | |
u32 | XHdmiphy1_Hdmi_CfgInitialize (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_Config *CfgPtr) |
This function initializes the Video PHY for HDMI. More... | |
u32 | XHdmiphy1_SetHdmiTxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc, XVidC_ColorFormat ColorFormat) |
This function update/set the HDMI TX parameter. More... | |
u32 | XHdmiphy1_SetHdmiRxParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function update/set the HDMI RX parameter. More... | |
u32 | XHdmiphy1_HdmiCfgCalcMmcmParam (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, XVidC_PixelsPerClock Ppc, XVidC_ColorDepth Bpc) |
This function calculates the HDMI MMCM parameters. More... | |
void | XHdmiphy1_HdmiUpdateClockSelection (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_SysClkDataSelType TxSysPllClkSel, XHdmiphy1_SysClkDataSelType RxSysPllClkSel) |
This function Updates the HDMIPHY clocking. More... | |
void | XHdmiphy1_ClkDetFreqReset (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function resets clock detector TX/RX frequency. More... | |
u32 | XHdmiphy1_ClkDetGetRefClkFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral. More... | |
u32 | XHdmiphy1_DruGetRefClkFreqHz (XHdmiphy1 *InstancePtr) |
This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral. More... | |
void | XHdmiphy1_HdmiDebugInfo (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function prints Video PHY debug information related to HDMI. More... | |
void | XHdmiphy1_SetHdmiCallback (XHdmiphy1 *InstancePtr, XHdmiphy1_HdmiHandlerType HandlerType, void *CallbackFunc, void *CallbackRef) |
This function installs an HDMI callback function for the specified handler type. More... | |
u32 | XHdmiphy1_Hdmi20Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will configure the HDMIPHY to HDMI 2.0 mode. More... | |
u32 | XHdmiphy1_Hdmi21Config (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels) |
This function will configure the GT for HDMI 2.1 operation. More... | |
void | XHdmiphy1_RegisterDebug (XHdmiphy1 *InstancePtr) |
This function prints out Video PHY register and GT Channel and Common DRP register contents. More... | |
void | XHdmiphy1_ClkDetEnable (XHdmiphy1 *InstancePtr, u8 Enable) |
This function enables the HDMIPHY's detector peripheral. More... | |
void | XHdmiphy1_ClkDetTimerClear (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function clears the clock detector TX/RX timer. More... | |
void | XHdmiphy1_ClkDetSetFreqLockThreshold (XHdmiphy1 *InstancePtr, u16 ThresholdVal) |
This function sets the clock detector frequency lock counter threshold value. More... | |
u8 | XHdmiphy1_ClkDetCheckFreqZero (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function checks clock detector RX/TX frequency zero indicator bit. More... | |
void | XHdmiphy1_ClkDetSetFreqTimeout (XHdmiphy1 *InstancePtr, u32 TimeoutVal) |
This function sets clock detector frequency lock counter threshold value. More... | |
void | XHdmiphy1_ClkDetTimerLoad (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u32 TimeoutVal) |
This function loads the timer to TX/RX in the clock detector. More... | |
void | XHdmiphy1_DruReset (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Reset) |
This function resets the DRU in the HDMIPHY. More... | |
void | XHdmiphy1_DruEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 Enable) |
This function enabled/disables the DRU in the HDMIPHY. More... | |
u16 | XHdmiphy1_DruGetVersion (XHdmiphy1 *InstancePtr) |
This function gets the DRU version. More... | |
void | XHdmiphy1_DruSetCenterFreqHz (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u64 CenterFreqHz) |
This function sets the DRU center frequency. More... | |
u64 | XHdmiphy1_DruCalcCenterFreqHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function calculates the center frequency value for the DRU. More... | |
void | XHdmiphy1_HdmiGtDruModeEnable (XHdmiphy1 *InstancePtr, u8 Enable) |
This function sets the GT RX CDR and Equalization for DRU mode. More... | |
void | XHdmiphy1_PatgenSetRatio (XHdmiphy1 *InstancePtr, u8 QuadId, u64 TxLineRate) |
This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock. More... | |
void | XHdmiphy1_PatgenEnable (XHdmiphy1 *InstancePtr, u8 QuadId, u8 Enable) |
This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock. More... | |
void | XHdmiphy1_HdmiIntrHandlerCallbackInit (XHdmiphy1 *InstancePtr) |
This function sets the appropriate HDMI interupt handlers. More... | |
void | XHdmiphy1_Ch2Ids (XHdmiphy1 *InstancePtr, XHdmiphy1_ChannelId ChId, u8 *Id0, u8 *Id1) |
This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More... | |
u32 | XHdmiphy1_DirReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function will set the current RX/TX configuration over DRP. More... | |
XHdmiphy1_SysClkDataSelType | Pll2SysClkData (XHdmiphy1_PllType PllSelect) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkDataSelType. More... | |
XHdmiphy1_SysClkOutSelType | Pll2SysClkOut (XHdmiphy1_PllType PllSelect) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkOutSelType. More... | |
u32 | XHdmiphy1_PllCalculator (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More... | |
u32 | XHdmiphy1_WriteCfgRefClkSelReg (XHdmiphy1 *InstancePtr, u8 QuadId) |
This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels. More... | |
void | XHdmiphy1_CfgPllRefClkSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_PllRefClkSelType RefClkSel) |
Configure the PLL reference clock selection for the specified channel(s). More... | |
void | XHdmiphy1_CfgSysClkDataSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_SysClkDataSelType SysClkDataSel) |
Configure the SYSCLKDATA reference clock selection for the direction. More... | |
void | XHdmiphy1_CfgSysClkOutSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_SysClkOutSelType SysClkOutSel) |
Configure the SYSCLKOUT reference clock selection for the direction. More... | |
u32 | XHdmiphy1_ClkCalcParams (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u32 PllClkInFreqHz) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More... | |
u32 | XHdmiphy1_OutDivReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function will set the current output divider configuration over DRP. More... | |
u32 | XHdmiphy1_ClkReconfig (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance. More... | |
XHdmiphy1_ChannelId | XHdmiphy1_GetRcfgChId (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_PllType PllType) |
Obtain the reconfiguration channel ID for given PLL type. More... | |
u32 | XHdmiphy1_IsPllLocked (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId) |
This function will check the status of a PLL lock on the specified channel. More... | |
u32 | XHdmiphy1_GetQuadRefClkFreq (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_PllRefClkSelType RefClkType) |
Obtain the current reference clock frequency for the quad based on the reference clock type. More... | |
XHdmiphy1_SysClkDataSelType | XHdmiphy1_GetSysClkDataSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the current [RT]XSYSCLKSEL[0] configuration. More... | |
XHdmiphy1_SysClkOutSelType | XHdmiphy1_GetSysClkOutSel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId) |
Obtain the current [RT]XSYSCLKSEL[1] configuration. More... | |
u32 | XHdmiphy1_GtUserRdyEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset and enable the Video PHY's user core logic. More... | |
void | XHdmiphy1_MmcmReset (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Hold) |
This function will reset the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmLockedMaskEnable (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, u8 Enable) |
This function will reset the mixed-mode clock manager (MMCM) core. More... | |
u8 | XHdmiphy1_MmcmLocked (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir) |
This function will get the lock status of the mixed-mode clock manager (MMCM) core. More... | |
void | XHdmiphy1_MmcmSetClkinsel (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_DirectionType Dir, XHdmiphy1_MmcmClkinsel Sel) |
This function will set the CLKINSEL port of the MMCM. More... | |
void | XHdmiphy1_SetBufgGtDiv (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir, u8 Div) |
This function obtains the divider value of the BUFG_GT peripheral. More... | |
u32 | XHdmiphy1_PowerDownGtPll (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, u8 Hold) |
This function will power down the specified GT PLL. More... | |
void | XHdmiphy1_SetIntrHandler (XHdmiphy1 *InstancePtr, XHdmiphy1_IntrHandlerType HandlerType, XHdmiphy1_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for the specified handler type. More... | |
void | XHdmiphy1_IntrEnable (XHdmiphy1 *InstancePtr, XHdmiphy1_IntrHandlerType Intr) |
This function enables interrupts associated with the specified interrupt type. More... | |
void | XHdmiphy1_IntrDisable (XHdmiphy1 *InstancePtr, XHdmiphy1_IntrHandlerType Intr) |
This function disabled interrupts associated with the specified interrupt type. More... | |
u64 | XHdmiphy1_GetPllVcoFreqHz (XHdmiphy1 *InstancePtr, u8 QuadId, XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir) |
This function calculates the PLL VCO operating frequency. More... | |
u8 | XHdmiphy1_GetRefClkSourcesCount (XHdmiphy1 *InstancePtr) |
This function returns the number of active reference clock sources based in the CFG. More... | |
u8 | XHdmiphy1_IsHDMI (XHdmiphy1 *InstancePtr, XHdmiphy1_DirectionType Dir) |
This function checks if Instance is HDMI 2.0 or HDMI 2.1. More... | |
void | XHdmiphy1_HdmiTxTimerTimeoutHandler (XHdmiphy1 *InstancePtr) |
This function is the handler for TX timer timeout events. More... | |
void | XHdmiphy1_HdmiRxTimerTimeoutHandler (XHdmiphy1 *InstancePtr) |
This function is the handler for RX timer timeout events. More... | |
void | XHdmiphy1_ErrorHandler (XHdmiphy1 *InstancePtr) |
This function is the error condition handler. More... | |
HDMIPHY core registers: CPLL Calibration registers. | |
#define | XHDMIPHY1_CPLL_CAL_PERIOD_REG 0x068 |
#define | XHDMIPHY1_CPLL_CAL_TOL_REG 0x06C |
HDMIPHY core registers: GT Debug INTF registers. | |
#define | XHDMIPHY1_GT_DBG_GPI_REG 0x068 |
#define | XHDMIPHY1_GT_DBG_GPO_REG 0x06C |
HDMIPHY core registers: Interrupt registers. | |
#define | XHDMIPHY1_INTR_EN_REG 0x110 |
#define | XHDMIPHY1_INTR_DIS_REG 0x114 |
#define | XHDMIPHY1_INTR_MASK_REG 0x118 |
#define | XHDMIPHY1_INTR_STS_REG 0x11C |
TMDS Clock Pattern Generator registers (HDMI). | |
#define | XHDMIPHY1_PATGEN_CTRL_REG 0x0340 |
HDMIPHY core masks, shifts, and register values. | |
#define | XHDMIPHY1_VERSION_INTER_REV_MASK 0x000000FF |
Internal revision. More... | |
#define | XHDMIPHY1_VERSION_CORE_PATCH_MASK 0x00000F00 |
Core patch details. More... | |
#define | XHDMIPHY1_VERSION_CORE_PATCH_SHIFT 8 |
Shift bits for core patch details. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_REV_MASK 0x0000F000 |
Core version revision. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_REV_SHIFT 12 |
Shift bits for core version revision. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_MNR_MASK 0x00FF0000 |
Core minor version. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_MNR_SHIFT 16 |
Shift bits for core minor version. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_MJR_MASK 0xFF000000 |
Core major version. More... | |
#define | XHDMIPHY1_VERSION_CORE_VER_MJR_SHIFT 24 |
Shift bits for core major version. More... | |
#define | XHDMIPHY1_BANK_SELECT_TX_MASK 0x00F |
#define | XHDMIPHY1_BANK_SELECT_RX_MASK 0xF00 |
#define | XHDMIPHY1_BANK_SELECT_RX_SHIFT 8 |
#define | XHDMIPHY1_REF_CLK_SEL_QPLL0_MASK 0x0000000F |
#define | XHDMIPHY1_REF_CLK_SEL_CPLL_MASK 0x000000F0 |
#define | XHDMIPHY1_REF_CLK_SEL_CPLL_SHIFT 4 |
#define | XHDMIPHY1_REF_CLK_SEL_QPLL1_MASK 0x00000F00 |
#define | XHDMIPHY1_REF_CLK_SEL_QPLL1_SHIFT 8 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK0 1 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK1 2 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK0 3 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK1 4 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0 5 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1 6 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK0 3 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK1 4 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK0 5 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK1 6 |
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTGREFCLK 7 |
#define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_MASK 0x0F000000 |
#define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_SHIFT 24 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0 0 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1 1 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL 0 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL 1 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0 3 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1 2 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH 0 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN 1 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0 2 |
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1 3 |
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G) |
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G) |
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G) |
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G) |
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G) |
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G) |
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G) |
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G) |
#define | XHDMIPHY1_PLL_RESET_CPLL_MASK 0x1 |
#define | XHDMIPHY1_PLL_RESET_QPLL0_MASK 0x2 |
#define | XHDMIPHY1_PLL_RESET_QPLL1_MASK 0x4 |
#define | XHDMIPHY1_GTWIZ_RESET_ALL_MASK 0x1 |
#define | XHDMIPHY1_PCIERST_ALL_CH_MASK 0x2 |
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_MASK(Ch) (0x01 << (Ch - 1)) |
#define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL0_MASK 0x10 |
#define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL1_MASK 0x20 |
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_ALL_MASK |
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_HDMI_MASK |
#define | XHDMIPHY1_PLL_LOCK_STATUS_RPLL_MASK 0xC0 |
#define | XHDMIPHY1_PLL_LOCK_STATUS_LCPLL_MASK 0x300 |
#define | XHDMIPHY1_TXRX_INIT_GTRESET_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_PMARESET_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_PCSRESET_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_INIT_USERRDY_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_LNKRDY_SB_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_MSTRESET_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_INIT_USERRDY_MASK(Ch) (0x40 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK(Ch) (0x80 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_GTRESET_ALL_MASK |
#define | XHDMIPHY1_TXRX_LNKRDY_SB_ALL_MASK |
#define | XHDMIPHY1_TXRX_MSTRESET_ALL_MASK |
#define | XHDMIPHY1_TX_INIT_USERRDY_ALL_MASK |
#define | XHDMIPHY1_RX_INIT_USERRDY_ALL_MASK |
#define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK |
#define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_ALL_MASK |
#define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK |
#define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK 0x1 |
#define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK 0x2 |
#define | XHDMIPHY1_POWERDOWN_CONTROL_CPLLPD_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_MASK(Ch) (0x18 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_SHIFT(Ch) (3 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_MASK(Ch) (0x60 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_SHIFT(Ch) (5 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_LOOPBACK_CONTROL_CH_MASK(Ch) (0x03 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_LOOPBACK_CONTROL_CH_SHIFT(Ch) (8 * (Ch - 1)) |
#define | XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK 0x00000FFF |
#define | XHDMIPHY1_DRP_CONTROL_DRPEN_MASK 0x00001000 |
#define | XHDMIPHY1_DRP_CONTROL_DRPWE_MASK 0x00002000 |
#define | XHDMIPHY1_DRP_CONTROL_DRPRESET_MASK 0x00004000 |
#define | XHDMIPHY1_DRP_CONTROL_DRPDI_MASK 0xFFFF0000 |
#define | XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT 16 |
#define | XHDMIPHY1_DRP_STATUS_DRPO_MASK 0x0FFFF |
#define | XHDMIPHY1_DRP_STATUS_DRPRDY_MASK 0x10000 |
#define | XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK 0x20000 |
#define | XHDMIPHY1_CPLL_CAL_PERIOD_MASK 0x3FFFF |
#define | XHDMIPHY1_CPLL_CAL_TOL_MASK 0x3FFFF |
#define | XHDMIPHY1_TX_GPI_MASK(Ch) (0x01 << (Ch - 1)) |
#define | XHDMIPHY1_RX_GPI_MASK(Ch) (0x10 << (Ch - 1)) |
#define | XHDMIPHY1_TX_GPO_MASK(Ch) (0x01 << (Ch - 1)) |
#define | XHDMIPHY1_RX_GPO_MASK(Ch) (0x10 << (Ch - 1)) |
#define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_ALL_MASK |
#define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_ALL_MASK |
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK(Ch) (0x5C << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK |
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT(Ch) (2 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_ALL_MASK |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYRESET_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGNEN_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYPD_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHINIT_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYRESET_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYBYPASS_MASK(Ch) (0x40 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYEN_MASK(Ch) (0x80 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_STATUS_TXPHALIGNDONE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_STATUS_TXPHINITDONE_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_STATUS_TXDLYRESETDONE_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_MASK(Ch) (0x18 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_SHIFT(Ch) (3 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_MASK(Ch) (0x000F << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
#define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_MASK(Ch) (0x0010 << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_SHIFT(Ch) (4 + (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_MASK(Ch) (0x0020 << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_SHIFT(Ch) (5 + (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_MASK(Ch) (0x07C0 << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_SHIFT(Ch) (6 + (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_MASK(Ch) (0xF800 << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_SHIFT(Ch) (11 + (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_MASK(Ch) (0x0001 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_SHIFT(Ch) (8 * (Ch - 1)) |
#define | XHDMIPHY1_TX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_TX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
#define | XHDMIPHY1_RX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2))) |
#define | XHDMIPHY1_RX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
#define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_ALL_MASK |
#define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_ALL_MASK |
#define | XHDMIPHY1_RX_CONTROL_RXPRBSCNTRESET_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK(Ch) (0xF0 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK |
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT(Ch) (4 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXCDRLOCK_MASK(Ch) (0x1 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_MASK(Ch) (0xE << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_SHIFT(Ch) (1 + (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RXLPMEN_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXCDRHOLD_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXOSOVRDEN_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXLPMLFKLOVRDEN_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_STATUS_RXLPMHFOVRDEN_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_RX_CONTROL_RXLPMEN_ALL_MASK |
#define | XHDMIPHY1_INTR_TXRESETDONE_MASK 0x00000001 |
#define | XHDMIPHY1_INTR_RXRESETDONE_MASK 0x00000002 |
#define | XHDMIPHY1_INTR_CPLL_LOCK_MASK 0x00000004 |
#define | XHDMIPHY1_INTR_QPLL0_LOCK_MASK 0x00000008 |
#define | XHDMIPHY1_INTR_LCPLL_LOCK_MASK 0x00000008 |
#define | XHDMIPHY1_INTR_TXALIGNDONE_MASK 0x00000010 |
#define | XHDMIPHY1_INTR_QPLL1_LOCK_MASK 0x00000020 |
#define | XHDMIPHY1_INTR_RPLL_LOCK_MASK 0x00000020 |
#define | XHDMIPHY1_INTR_TXCLKDETFREQCHANGE_MASK 0x00000040 |
#define | XHDMIPHY1_INTR_RXCLKDETFREQCHANGE_MASK 0x00000080 |
#define | XHDMIPHY1_INTR_TXMMCMUSRCLK_LOCK_MASK 0x00000200 |
#define | XHDMIPHY1_INTR_RXMMCMUSRCLK_LOCK_MASK 0x00000400 |
#define | XHDMIPHY1_INTR_TXGPO_RE_MASK 0x00000800 |
#define | XHDMIPHY1_INTR_RXGPO_RE_MASK 0x00001000 |
#define | XHDMIPHY1_INTR_TXTMRTIMEOUT_MASK 0x40000000 |
#define | XHDMIPHY1_INTR_RXTMRTIMEOUT_MASK 0x80000000 |
#define | XHDMIPHY1_INTR_QPLL_LOCK_MASK XHDMIPHY1_INTR_QPLL0_LOCK_MASK |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_NEW_MASK 0x01 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_RST_MASK 0x02 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK 0x200 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800 |
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CLKINSEL_MASK 0x1000 |
#define | XHDMIPHY1_MMCM_USRCLK_REG1_DIVCLK_MASK 0x00000FF |
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_MASK 0x000FF00 |
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_SHIFT 8 |
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_MASK 0x3FF0000 |
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_SHIFT 16 |
#define | XHDMIPHY1_MMCM_USRCLK_REG2_DIVCLK_MASK 0x00000FF |
#define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_MASK 0x3FF0000 |
#define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_SHIFT 16 |
#define | XHDMIPHY1_MMCM_USRCLK_REG34_DIVCLK_MASK 0x00000FF |
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_CLR_MASK 0x1 |
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_MASK 0xE |
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_SHIFT 1 |
#define | XHDMIPHY1_MISC_XXUSRCLK_CKOUT1_OEN_MASK 0x1 |
#define | XHDMIPHY1_MISC_XXUSRCLK_REFCLK_CEB_MASK 0x2 |
#define | XHDMIPHY1_CLKDET_CTRL_RUN_MASK 0x1 |
#define | XHDMIPHY1_CLKDET_CTRL_TX_TMR_CLR_MASK 0x2 |
#define | XHDMIPHY1_CLKDET_CTRL_RX_TMR_CLR_MASK 0x4 |
#define | XHDMIPHY1_CLKDET_CTRL_TX_FREQ_RST_MASK 0x8 |
#define | XHDMIPHY1_CLKDET_CTRL_RX_FREQ_RST_MASK 0x10 |
#define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_MASK 0x1FE0 |
#define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_SHIFT 5 |
#define | XHDMIPHY1_CLKDET_STAT_TX_FREQ_ZERO_MASK 0x1 |
#define | XHDMIPHY1_CLKDET_STAT_RX_FREQ_ZERO_MASK 0x2 |
#define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_MASK 0x3 |
#define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_CAP_MASK 0x4 |
#define | XHDMIPHY1_DRU_CTRL_RST_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_DRU_CTRL_EN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_DRU_STAT_ACTIVE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
#define | XHDMIPHY1_DRU_STAT_VERSION_MASK 0xFF000000 |
#define | XHDMIPHY1_DRU_STAT_VERSION_SHIFT 24 |
#define | XHDMIPHY1_DRU_CFREQ_H_MASK 0x1F |
#define | XHDMIPHY1_DRU_GAIN_G1_MASK 0x00001F |
#define | XHDMIPHY1_DRU_GAIN_G1_SHIFT 0 |
#define | XHDMIPHY1_DRU_GAIN_G1_P_MASK 0x001F00 |
#define | XHDMIPHY1_DRU_GAIN_G1_P_SHIFT 8 |
#define | XHDMIPHY1_DRU_GAIN_G2_MASK 0x1F0000 |
#define | XHDMIPHY1_DRU_GAIN_G2_SHIFT 16 |
#define | XHDMIPHY1_PATGEN_CTRL_ENABLE_MASK 0x80000000 |
#define | XHDMIPHY1_PATGEN_CTRL_ENABLE_SHIFT 31 |
#define | XHDMIPHY1_PATGEN_CTRL_RATIO_MASK 0x7 |
#define | XHDMIPHY1_PATGEN_CTRL_RATIO_SHIFT 0 |
Register access macro definitions. | |
#define | XHdmiphy1_In32 Xil_In32 |
#define | XHdmiphy1_Out32 Xil_Out32 |
#define XHdmiphy1_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XHdmiphy1_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register.
BaseAddress | is the base address of the device. |
RegOffset | is the register offset to be read from. |
Referenced by XHdmiphy1_ClkDetCheckFreqZero(), XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetFreqReset(), XHdmiphy1_ClkDetGetRefClkFreqHz(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetTimerClear(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_DruEnable(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_DruGetVersion(), XHdmiphy1_DruReset(), XHdmiphy1_GetSysClkDataSel(), XHdmiphy1_GetSysClkOutSel(), XHdmiphy1_GetVersion(), XHdmiphy1_GtUserRdyEnable(), XHdmiphy1_HdmiDebugInfo(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxMmcmLockHandler(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_InterruptHandler(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_IsPllLocked(), XHdmiphy1_MmcmLocked(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmPowerDown(), XHdmiphy1_MmcmReset(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_PatgenEnable(), XHdmiphy1_PatgenSetRatio(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_RegisterDebug(), XHdmiphy1_ResetGtPll(), XHdmiphy1_ResetGtTxRx(), XHdmiphy1_SelfTest(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetPolarity(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), XHdmiphy1_TxAlignReset(), XHdmiphy1_TxAlignStart(), and XHdmiphy1_TxPrbsForceError().
#define XHDMIPHY1_VERSION_CORE_PATCH_MASK 0x00000F00 |
Core patch details.
#define XHDMIPHY1_VERSION_CORE_PATCH_SHIFT 8 |
Shift bits for core patch details.
#define XHDMIPHY1_VERSION_CORE_VER_MJR_MASK 0xFF000000 |
Core major version.
#define XHDMIPHY1_VERSION_CORE_VER_MJR_SHIFT 24 |
Shift bits for core major version.
#define XHDMIPHY1_VERSION_CORE_VER_MNR_MASK 0x00FF0000 |
Core minor version.
#define XHDMIPHY1_VERSION_CORE_VER_MNR_SHIFT 16 |
Shift bits for core minor version.
#define XHDMIPHY1_VERSION_CORE_VER_REV_MASK 0x0000F000 |
Core version revision.
#define XHDMIPHY1_VERSION_CORE_VER_REV_SHIFT 12 |
Shift bits for core version revision.
#define XHDMIPHY1_VERSION_INTER_REV_MASK 0x000000FF |
Internal revision.
#define XHdmiphy1_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
Data | |||
) | XHdmiphy1_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register.
BaseAddress | is the base address of the device. |
RegOffset | is the register offset to write to. |
Data | is the 32-bit data to write to the specified register. |
Referenced by XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetFreqReset(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetSetFreqTimeout(), XHdmiphy1_ClkDetTimerClear(), XHdmiphy1_ClkDetTimerLoad(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_DruEnable(), XHdmiphy1_DruReset(), XHdmiphy1_DruSetCenterFreqHz(), XHdmiphy1_GtUserRdyEnable(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxMmcmLockHandler(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmPowerDown(), XHdmiphy1_MmcmReset(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_PatgenEnable(), XHdmiphy1_PatgenSetRatio(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_ResetGtPll(), XHdmiphy1_ResetGtTxRx(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetPolarity(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), XHdmiphy1_TxAlignReset(), XHdmiphy1_TxAlignStart(), XHdmiphy1_TxPrbsForceError(), and XHdmiphy1_WriteCfgRefClkSelReg().
typedef void(* XHdmiphy1_Callback)(void *CallbackRef) |
Generic callback type.
CallbackRef | is a pointer to the callback reference. |
typedef void(* XHdmiphy1_ErrorCallback)(void *CallbackRef) |
Error callback type.
CallbackRef | is a pointer to the callback reference. |
typedef void(* XHdmiphy1_IntrHandler)(void *InstancePtr) |
Callback type which represents the handler for interrupts.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
typedef u64(* XHdmiphy1_LogCallback)(void *CallbackRef) |
Generic callback type.
CallbackRef | is a pointer to the callback reference. |
typedef void(* XHdmiphy1_TimerHandler)(void *InstancePtr, u32 MicroSeconds) |
Callback type which represents a custom timer wait handler.
This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
MicroSeconds | is the number of microseconds to be passed to the timer function. |
enum XHdmiphy1_ChannelId |
This typedef enumerates the available channels.
enum XHdmiphy1_GtState |
This typedef enumerates the list of available hdmi handler types.
The values are used as parameters to the XHdmiphy1_SetHdmiCallback function.
This typedef enumerates the list of available interrupt handler types.
The values are used as parameters to the XHdmiphy1_SetIntrHandler function.
enum XHdmiphy1_LogEvent |
This typedef enumerates the available clocks that are used as multiplexer input selections for the RX/TX output clock.
This typedef enumerates the available reference clocks for the PLL clock selection multiplexer.
enum XHdmiphy1_PllType |
This typedef enumerates the different PLL types for a given GT channel.
This typedef enumerates the available PRBS patterns available from the.
This typedef enumerates the various protocols handled by the Video PHY controller (HDMIPHY).
This typedef enumerates the available reference clocks used to drive the RX/TX datapaths.
This typedef enumerates the available reference clocks used to drive the RX/TX output clocks.
XHdmiphy1_SysClkDataSelType Pll2SysClkData | ( | XHdmiphy1_PllType | PllSelect | ) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkDataSelType.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Referenced by XHdmiphy1_PllInitialize().
XHdmiphy1_SysClkOutSelType Pll2SysClkOut | ( | XHdmiphy1_PllType | PllSelect | ) |
This function will translate from XHdmiphy1_PllType to XHdmiphy1_SysClkOutSelType.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Referenced by XHdmiphy1_PllInitialize().
void XHdmiphy1_CfgInitialize | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_Config * | ConfigPtr, | ||
UINTPTR | EffectiveAddr | ||
) |
This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. |
EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::DruRefClkSel, XHdmiphy1::IsReady, XHdmiphy1_Config::RxFrlRefClkSel, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1_Config::RxSysPllClkSel, XHdmiphy1_Config::TxFrlRefClkSel, XHdmiphy1_Config::TxRefClkSel, and XHdmiphy1_Config::TxSysPllClkSel.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
u32 XHdmiphy1_CfgLineRate | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u64 | LineRateHz | ||
) |
Configure the channel's line rate.
This is a software only configuration and this value is used in the PLL calculator.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
LineRate | is the line rate to configure software. |
References XHdmiphy1_Channel::LineRateHz, XHdmiphy1::Quads, and XHdmiphy1_Ch2Ids().
Referenced by XHdmiphy1_HdmiCpllParam(), and XHdmiphy1_HdmiQpllParam().
void XHdmiphy1_CfgPllRefClkSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_PllRefClkSelType | RefClkSel | ||
) |
Configure the PLL reference clock selection for the specified channel(s).
This is applied to both direction to the software configuration only.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
SysClkDataSel | is the reference clock selection to configure. |
References XHdmiphy1::Quads, and XHdmiphy1_Ch2Ids().
Referenced by XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_PllInitialize().
void XHdmiphy1_CfgSysClkDataSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_SysClkDataSelType | SysClkDataSel | ||
) |
Configure the SYSCLKDATA reference clock selection for the direction.
Same configuration applies to all channels in the quad. This is applied to the software configuration only.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
SysClkDataSel | is the reference clock selection to configure. |
References XHdmiphy1::Quads, and XHdmiphy1_Ch2Ids().
Referenced by XHdmiphy1_HdmiQpllParam(), and XHdmiphy1_PllInitialize().
void XHdmiphy1_CfgSysClkOutSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_SysClkOutSelType | SysClkOutSel | ||
) |
Configure the SYSCLKOUT reference clock selection for the direction.
Same configuration applies to all channels in the quad. This is applied to the software configuration only.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
SysClkOutSel | is the reference clock selection to configure. |
References XHdmiphy1::Quads, and XHdmiphy1_Ch2Ids().
Referenced by XHdmiphy1_HdmiQpllParam(), and XHdmiphy1_PllInitialize().
void XHdmiphy1_Ch2Ids | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 * | Id0, | ||
u8 * | Id1 | ||
) |
This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.
HDMI uses 3 channels; This ID translation is done to allow other functions to operate iteratively over multiple channels.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID used to determine the indices. |
Id0 | is a pointer to the start channel ID to set. |
Id1 | is a pointer to the end channel ID to set. |
References XHdmiphy1::Config, XHdmiphy1_Config::RxChannels, XHdmiphy1_Config::TxChannels, XHdmiphy1_Config::UseGtAsTxTmdsClk, XHdmiphy1_Config::XcvrType, and XHdmiphy1_IsHDMI().
u32 XHdmiphy1_ClkCalcParams | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u32 | PllClkInFreqHz | ||
) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.
This will be done for all channels specified by ChId. This function is a wrapper for XHdmiphy1_PllCalculator.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to calculate the PLL values for. |
ChId | is the channel ID to calculate the PLL values for. |
Dir | is an indicator for TX or RX. |
PllClkInFreqHz | is the PLL input frequency on which to base the calculations on. A value of 0 indicates to use the currently configured quad PLL reference clock. A non-zero value indicates to ignore what is currently configured in SW, and use a custom frequency instead. |
References XHdmiphy1_Ch2Ids(), and XHdmiphy1_PllCalculator().
Referenced by XHdmiphy1_HdmiCpllParam(), and XHdmiphy1_HdmiQpllParam().
u8 XHdmiphy1_ClkDetCheckFreqZero | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_DirectionType | Dir | ||
) |
This function checks clock detector RX/TX frequency zero indicator bit.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
void XHdmiphy1_ClkDetEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | Enable | ||
) |
This function enables the HDMIPHY's detector peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Enable | specifies TRUE/FALSE value to either enable or disable the clock detector respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_ClkDetFreqReset | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function resets clock detector TX/RX frequency.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
u32 XHdmiphy1_ClkDetGetRefClkFreqHz | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_DirectionType | Dir | ||
) |
This function returns the frequency of the RX/TX reference clock as measured by the clock detector peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_DruCalcCenterFreqHz(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
void XHdmiphy1_ClkDetSetFreqLockThreshold | ( | XHdmiphy1 * | InstancePtr, |
u16 | ThresholdVal | ||
) |
This function sets the clock detector frequency lock counter threshold value.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ThresholdVal | is the threshold value to be set. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_ClkDetSetFreqTimeout | ( | XHdmiphy1 * | InstancePtr, |
u32 | TimeoutVal | ||
) |
This function sets clock detector frequency lock counter threshold value.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
TimeoutVal | is the timeout value and is normally the system clock frequency. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_ClkDetTimerClear | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function clears the clock detector TX/RX timer.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
void XHdmiphy1_ClkDetTimerLoad | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u32 | TimeoutVal | ||
) |
This function loads the timer to TX/RX in the clock detector.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for RX or TX. |
TimeoutVal | is the timeout value to store in the clock detector. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
void XHdmiphy1_Clkout1OBufTdsEnable | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_DirectionType | Dir, | ||
u8 | Enable | ||
) |
This function enables the TX or RX CLKOUT1 OBUFTDS peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Dir | is an indicator for TX or RX. |
Enable | specifies TRUE/FALSE value to either enable or disable the OBUFTDS, respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi21Config().
u32 XHdmiphy1_ClkReconfig | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID for which to write the settings for. |
References XHdmiphy1::HdmiIsQpllPresent, XHdmiphy1_Ch2Ids(), XHdmiphy1_ErrorHandler(), XHdmiphy1_IsHDMI(), XHDMIPHY1_LOG_EVT_CPLL_RECONFIG, XHDMIPHY1_LOG_EVT_NO_QPLL_ERR, XHDMIPHY1_LOG_EVT_QPLL_RECONFIG, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
u32 XHdmiphy1_DirReconfig | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function will set the current RX/TX configuration over DRP.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID for which to write the settings for. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Ch2Ids(), XHDMIPHY1_LOG_EVT_GT_RX_RECONFIG, XHDMIPHY1_LOG_EVT_GT_TX_RECONFIG, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
u16 XHdmiphy1_DrpRd | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u16 | Addr, | ||
u16 * | RetVal | ||
) |
This function will initiate a read DRP transaction.
It is a wrapper around XHdmiphy1_DrpAccess.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID on which to direct the DRP access. |
Addr | is the DRP address to issue the DRP access to. |
RetVal | is the DRP read_value returned implicitly. |
Referenced by XHdmiphy1_RegisterDebug().
u32 XHdmiphy1_DrpWr | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u16 | Addr, | ||
u16 | Val | ||
) |
This function will initiate a write DRP transaction.
It is a wrapper around XHdmiphy1_DrpAccess.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID on which to direct the DRP access. |
Addr | is the DRP address to issue the DRP access to. |
Val | is the value to write to the DRP address. |
u64 XHdmiphy1_DruCalcCenterFreqHz | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function calculates the center frequency value for the DRU.
InstancePtr | is a pointer to the XHdmiphy1 GT core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
References XHdmiphy1::Quads, XHdmiphy1_Channel::RxOutDiv, XHdmiphy1_ClkDetGetRefClkFreqHz(), and XHdmiphy1_DruGetRefClkFreqHz().
Referenced by XHdmiphy1_SetHdmiRxParam().
void XHdmiphy1_DruEnable | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 | Enable | ||
) |
This function enabled/disables the DRU in the HDMIPHY.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID to operate on. |
Enable | specifies TRUE/FALSE value to either enable or disable the DRU, respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiRxTimerTimeoutHandler().
u32 XHdmiphy1_DruGetRefClkFreqHz | ( | XHdmiphy1 * | InstancePtr | ) |
This function returns the frequency of the DRU reference clock as measured by the clock detector peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::XcvrType, and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_DruCalcCenterFreqHz(), XHdmiphy1_GetPllVcoFreqHz(), XHdmiphy1_HdmiCpllParam(), and XHdmiphy1_HdmiQpllParam().
u16 XHdmiphy1_DruGetVersion | ( | XHdmiphy1 * | InstancePtr | ) |
This function gets the DRU version.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_HdmiDebugInfo().
void XHdmiphy1_DruReset | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u8 | Reset | ||
) |
This function resets the DRU in the HDMIPHY.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | is the channel ID to operate on. |
Reset | specifies TRUE/FALSE value to either enable or disable the DRU respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), and XHdmiphy1_HdmiRxClkDetFreqChangeHandler().
void XHdmiphy1_DruSetCenterFreqHz | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_ChannelId | ChId, | ||
u64 | CenterFreqHz | ||
) |
This function sets the DRU center frequency.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
ChId | specifies the channel ID. |
CenterFreqHz | is the frequency value to set. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_SetHdmiRxParam().
void XHdmiphy1_ErrorHandler | ( | XHdmiphy1 * | InstancePtr | ) |
This function is the error condition handler.
InstancePtr | is a pointer to the HDMIPHY instance. |
ErrIrqType | is the error type |
References XHdmiphy1::ErrorCallback, and XHdmiphy1::ErrorRef.
Referenced by XHdmiphy1_ClkReconfig(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiCfgCalcMmcmParam(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiQpllParam(), and XHdmiphy1_SetHdmiTxParam().
u64 XHdmiphy1_GetLineRateHz | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function will return the line rate in Hz for a given channel / quad.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to check. |
ChId | is the channel ID for which to retrieve the line rate. |
References XHdmiphy1_Channel::LineRateHz, and XHdmiphy1::Quads.
Referenced by XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), and XHdmiphy1_HdmiQpllParam().
XHdmiphy1_PllType XHdmiphy1_GetPllType | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
Obtain the channel's PLL reference clock selection.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
ChId | is the channel ID which to operate on. |
References XHdmiphy1::Config, XHdmiphy1_Config::RxSysPllClkSel, XHdmiphy1_Config::TxSysPllClkSel, XHdmiphy1_GetSysClkDataSel(), and XHdmiphy1_GetSysClkOutSel().
Referenced by XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiCfgCalcMmcmParam(), XHdmiphy1_HdmiCpllLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiQpllLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_IsPllLocked(), and XHdmiphy1_SetHdmiRxParam().
u64 XHdmiphy1_GetPllVcoFreqHz | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function calculates the PLL VCO operating frequency.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
References XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1::HdmiRxRefClkHz, XHdmiphy1::HdmiTxRefClkHz, XHdmiphy1::Quads, XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_GetQuadRefClkFreq(), and XHdmiphy1_IsHDMI().
u32 XHdmiphy1_GetQuadRefClkFreq | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_PllRefClkSelType | RefClkType | ||
) |
Obtain the current reference clock frequency for the quad based on the reference clock type.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
RefClkType | is the type to obtain the clock selection for. |
References XHdmiphy1::Quads.
Referenced by XHdmiphy1_GetPllVcoFreqHz(), and XHdmiphy1_PllCalculator().
XHdmiphy1_ChannelId XHdmiphy1_GetRcfgChId | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_PllType | PllType | ||
) |
Obtain the reconfiguration channel ID for given PLL type.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
PllType | is the PLL type being used by the channel. |
Referenced by XHdmiphy1_HdmiCpllLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiQpllLockHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), and XHdmiphy1_SetHdmiRxParam().
u8 XHdmiphy1_GetRefClkSourcesCount | ( | XHdmiphy1 * | InstancePtr | ) |
This function returns the number of active reference clock sources based in the CFG.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1_Config::DruRefClkSel, XHdmiphy1_Config::RxFrlRefClkSel, XHdmiphy1_Config::RxProtocol, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1_Config::TxFrlRefClkSel, XHdmiphy1_Config::TxProtocol, and XHdmiphy1_Config::TxRefClkSel.
XHdmiphy1_SysClkDataSelType XHdmiphy1_GetSysClkDataSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
Obtain the current [RT]XSYSCLKSEL[0] configuration.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
ChId | is the channel ID which to operate on. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::XcvrType, and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_GetPllType().
XHdmiphy1_SysClkOutSelType XHdmiphy1_GetSysClkOutSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
Obtain the current [RT]XSYSCLKSEL[1] configuration.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
ChId | is the channel ID which to operate on. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::XcvrType, and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_GetPllType().
u32 XHdmiphy1_GetVersion | ( | XHdmiphy1 * | InstancePtr | ) |
This function will obtian the IP version.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
u32 XHdmiphy1_GtUserRdyEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Hold | ||
) |
This function will reset and enable the Video PHY's user core logic.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
u32 XHdmiphy1_Hdmi20Config | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function will configure the HDMIPHY to HDMI 2.0 mode.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1::Config, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1_Hdmi21Cfg::LineRate, XHdmiphy1_Hdmi21Cfg::NChannels, XHdmiphy1::RxHdmi21Cfg, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_Config::TxRefClkSel, XHdmiphy1_CfgPllRefClkSel(), XHdmiphy1_GetPllType(), XHdmiphy1_IntrEnable(), XHDMIPHY1_LOG_EVT_TMDS_RECONFIG, XHdmiphy1_LogWrite(), XHdmiphy1_MmcmSetClkinsel(), and XHdmiphy1_WriteCfgRefClkSelReg().
u32 XHdmiphy1_Hdmi21Config | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u64 | LineRate, | ||
u8 | NChannels | ||
) |
This function will configure the GT for HDMI 2.1 operation.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1::Config, XHdmiphy1::HdmiRxRefClkHz, XHdmiphy1::HdmiTxRefClkHz, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1_Hdmi21Cfg::LineRate, XHdmiphy1_Hdmi21Cfg::NChannels, XHdmiphy1_Config::Ppc, XHdmiphy1::Quads, XHdmiphy1_Config::RxFrlRefClkSel, XHdmiphy1::RxHdmi21Cfg, XHdmiphy1_Quad::RxMmcm, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1_Config::TxFrlRefClkSel, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_Config::TxRefClkSel, XHdmiphy1_CfgPllRefClkSel(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_ErrorHandler(), XHdmiphy1_GetPllType(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_IntrDisable(), XHDMIPHY1_LOG_EVT_FRL_RECONFIG, XHDMIPHY1_LOG_EVT_SPDGRDE_ERR, XHdmiphy1_LogWrite(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_MmcmStart(), XHdmiphy1_SetHdmiTxParam(), and XHdmiphy1_WriteCfgRefClkSelReg().
u32 XHdmiphy1_Hdmi_CfgInitialize | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_Config * | CfgPtr | ||
) |
This function initializes the Video PHY for HDMI.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
CfgPtr | is a pointer to the configuration structure that will be used to copy the settings from. |
References XHdmiphy1_Config::AxiLiteClkFreq, XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1::HdmiIsQpllPresent, XHdmiphy1::IsReady, XHdmiphy1::Quads, XHdmiphy1_Channel::RxState, XHdmiphy1_Config::TransceiverWidth, XHdmiphy1_Channel::TxState, XHdmiphy1_Config::XcvrType, XHdmiphy1_CfgInitialize(), XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetSetFreqTimeout(), XHdmiphy1_DruEnable(), XHdmiphy1_DruReset(), XHDMIPHY1_GT_STATE_IDLE, XHdmiphy1_HdmiIntrHandlerCallbackInit(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_IsHDMI(), XHDMIPHY1_LOG_EVT_INIT, XHdmiphy1_LogReset(), XHdmiphy1_LogWrite(), XHdmiphy1_MmcmReset(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_ResetGtPll(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), and XHdmiphy1_WriteReg.
u32 XHdmiphy1_HdmiCfgCalcMmcmParam | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XVidC_PixelsPerClock | Ppc, | ||
XVidC_ColorDepth | Bpc | ||
) |
This function calculates the HDMI MMCM parameters.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for RX or TX. |
Ppc | specifies the total number of pixels per clock.
|
Bpc | specifies the color depth/bits per color component.
|
References XHdmiphy1::Config, XHdmiphy1::HdmiRxRefClkHz, XHdmiphy1::HdmiRxTmdsClockRatio, XHdmiphy1::HdmiTxRefClkHz, XHdmiphy1::HdmiTxSampleRate, XHdmiphy1_Channel::LineRateHz, XHdmiphy1::Quads, XHdmiphy1_Quad::RxMmcm, XHdmiphy1_Config::TransceiverWidth, XHdmiphy1_Quad::TxMmcm, XHdmiphy1_ErrorHandler(), XHdmiphy1_GetPllType(), XHDMIPHY1_LOG_EVT_1PPC_ERR, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_SetHdmiTxParam().
void XHdmiphy1_HdmiDebugInfo | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function prints Video PHY debug information related to HDMI.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1::Quads, XHdmiphy1_Channel::RxDataRefClkSel, XHdmiphy1_Quad::RxMmcm, XHdmiphy1_Channel::RxOutDiv, XHdmiphy1_Channel::TxDataRefClkSel, XHdmiphy1_Quad::TxMmcm, XHdmiphy1_Channel::TxOutDiv, XHdmiphy1_DruGetVersion(), XHDMIPHY1_GT_STATE_ALIGN, XHDMIPHY1_GT_STATE_GPO_RE, XHDMIPHY1_GT_STATE_IDLE, XHDMIPHY1_GT_STATE_LOCK, XHDMIPHY1_GT_STATE_READY, XHDMIPHY1_GT_STATE_RESET, XHdmiphy1_IsHDMI(), and XHdmiphy1_ReadReg.
void XHdmiphy1_HdmiGtDruModeEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | Enable | ||
) |
This function sets the GT RX CDR and Equalization for DRU mode.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Enable | enables the DRU logic (when 1), or disables (when 0). |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHDMIPHY1_LOG_EVT_DRU_EN, XHdmiphy1_LogWrite(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiRxTimerTimeoutHandler().
void XHdmiphy1_HdmiIntrHandlerCallbackInit | ( | XHdmiphy1 * | InstancePtr | ) |
This function sets the appropriate HDMI interupt handlers.
InstancePtr | is a pointer to the HDMIPHY instance. |
References XHdmiphy1_SetIntrHandler().
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_HdmiRxTimerTimeoutHandler | ( | XHdmiphy1 * | InstancePtr | ) |
This function is the handler for RX timer timeout events.
InstancePtr | is a pointer to the HDMIPHY instance. |
References XHdmiphy1::Config, XHdmiphy1_Config::DruRefClkSel, XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1::Quads, XHdmiphy1_Config::RxFrlRefClkSel, XHdmiphy1::RxHdmi21Cfg, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1_Channel::RxState, XHdmiphy1_CfgPllRefClkSel(), XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkReconfig(), XHdmiphy1_DirReconfig(), XHdmiphy1_DruEnable(), XHdmiphy1_GetPllType(), XHdmiphy1_GetRcfgChId(), XHDMIPHY1_GT_STATE_GPO_RE, XHDMIPHY1_GT_STATE_IDLE, XHdmiphy1_HdmiGtDruModeEnable(), XHDMIPHY1_LOG_EVT_RX_TMR, XHdmiphy1_LogWrite(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_MmcmStart(), XHdmiphy1_OutDivReconfig(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_ResetGtPll(), XHdmiphy1_SetHdmiRxParam(), and XHdmiphy1_WriteCfgRefClkSelReg().
Referenced by XHdmiphy1_Hdmi21Config().
void XHdmiphy1_HdmiTxTimerTimeoutHandler | ( | XHdmiphy1 * | InstancePtr | ) |
This function is the handler for TX timer timeout events.
InstancePtr | is a pointer to the HDMIPHY instance. |
References XHdmiphy1::Config, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1::Quads, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_Channel::TxOutDiv, XHdmiphy1_Channel::TxState, XHdmiphy1_Config::XcvrType, XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkReconfig(), XHdmiphy1_DirReconfig(), XHdmiphy1_GetPllType(), XHdmiphy1_GetRcfgChId(), XHDMIPHY1_GT_STATE_GPO_RE, XHDMIPHY1_GT_STATE_LOCK, XHDMIPHY1_LOG_EVT_TX_TMR, XHdmiphy1_LogWrite(), XHdmiphy1_MmcmStart(), XHdmiphy1_OutDivReconfig(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_ResetGtPll(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_TxAlignStart(), and XHdmiphy1_WriteCfgRefClkSelReg().
Referenced by XHdmiphy1_Hdmi21Config().
void XHdmiphy1_HdmiUpdateClockSelection | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_SysClkDataSelType | TxSysPllClkSel, | ||
XHdmiphy1_SysClkDataSelType | RxSysPllClkSel | ||
) |
This function Updates the HDMIPHY clocking.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
TxSysPllClkSel | is the SYSCLKDATA selection for TX. |
RxSysPllClkSel | is the SYSCLKDATA selection for RX. |
References XHdmiphy1::Config, XHdmiphy1::Quads, XHdmiphy1_Channel::RxState, XHdmiphy1_Config::RxSysPllClkSel, XHdmiphy1_Channel::TxState, XHdmiphy1_Config::TxSysPllClkSel, XHdmiphy1_Ch2Ids(), XHDMIPHY1_GT_STATE_IDLE, and XHdmiphy1_ResetGtPll().
void XHdmiphy1_IBufDsEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Enable | ||
) |
This function enables the TX or RX IBUFDS peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Dir | is an indicator for TX or RX. |
Enable | specifies TRUE/FALSE value to either enable or disable the IBUFDS, respectively. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::DruIsPresent, XHdmiphy1_Config::DruRefClkSel, XHdmiphy1_Config::RxRefClkSel, XHdmiphy1_Config::TxRefClkSel, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_InterruptHandler | ( | XHdmiphy1 * | InstancePtr | ) |
This function is the interrupt handler for the XHdmiphy1 driver.
It will detect what kind of interrupt has happened, and will invoke the appropriate callback function.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1::IntrCpllLockCallbackRef, XHdmiphy1::IntrCpllLockHandler, XHdmiphy1::IntrQpll1LockCallbackRef, XHdmiphy1::IntrQpll1LockHandler, XHdmiphy1::IntrQpllLockCallbackRef, XHdmiphy1::IntrQpllLockHandler, XHdmiphy1::IntrRxClkDetFreqChangeCallbackRef, XHdmiphy1::IntrRxClkDetFreqChangeHandler, XHdmiphy1::IntrRxMmcmLockCallbackRef, XHdmiphy1::IntrRxMmcmLockHandler, XHdmiphy1::IntrRxResetDoneCallbackRef, XHdmiphy1::IntrRxResetDoneHandler, XHdmiphy1::IntrRxTmrTimeoutCallbackRef, XHdmiphy1::IntrRxTmrTimeoutHandler, XHdmiphy1::IntrTxAlignDoneCallbackRef, XHdmiphy1::IntrTxAlignDoneHandler, XHdmiphy1::IntrTxClkDetFreqChangeCallbackRef, XHdmiphy1::IntrTxClkDetFreqChangeHandler, XHdmiphy1::IntrTxMmcmLockCallbackRef, XHdmiphy1::IntrTxMmcmLockHandler, XHdmiphy1::IntrTxResetDoneCallbackRef, XHdmiphy1::IntrTxResetDoneHandler, XHdmiphy1::IntrTxTmrTimeoutCallbackRef, XHdmiphy1::IntrTxTmrTimeoutHandler, XHdmiphy1::IsReady, and XHdmiphy1_ReadReg.
void XHdmiphy1_IntrDisable | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_IntrHandlerType | Intr | ||
) |
This function disabled interrupts associated with the specified interrupt type.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
Intr | is the interrupt type/mask to disable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi21Config(), and XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_IntrEnable | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_IntrHandlerType | Intr | ||
) |
This function enables interrupts associated with the specified interrupt type.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
Intr | is the interrupt type/mask to enable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi20Config(), and XHdmiphy1_Hdmi_CfgInitialize().
u8 XHdmiphy1_IsHDMI | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_DirectionType | Dir | ||
) |
This function checks if Instance is HDMI 2.0 or HDMI 2.1.
InstancePtr | is a pointer to the HDMIPHY instance. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1::Config, XHdmiphy1_Config::RxProtocol, and XHdmiphy1_Config::TxProtocol.
Referenced by XHdmiphy1_Ch2Ids(), XHdmiphy1_ClkReconfig(), XHdmiphy1_GetPllVcoFreqHz(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiDebugInfo(), and XHdmiphy1_IsPllLocked().
u32 XHdmiphy1_IsPllLocked | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function will check the status of a PLL lock on the specified channel.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_GetPllType(), XHdmiphy1_IsHDMI(), and XHdmiphy1_ReadReg.
Referenced by XHdmiphy1_HdmiCpllLockHandler(), and XHdmiphy1_HdmiQpllLockHandler().
void XHdmiphy1_LogDisplay | ( | XHdmiphy1 * | InstancePtr | ) |
This function will print the entire log.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1::Log, XHdmiphy1::LogWriteCallback, XHdmiphy1_Log::TailIndex, XHdmiphy1_Log::TimeRecord, XHDMIPHY1_LOG_EVT_1PPC_ERR, XHDMIPHY1_LOG_EVT_CPLL_EN, XHDMIPHY1_LOG_EVT_CPLL_LOCK, XHDMIPHY1_LOG_EVT_CPLL_RECONFIG, XHDMIPHY1_LOG_EVT_CPLL_RST, XHDMIPHY1_LOG_EVT_DRU_CLK_ERR, XHDMIPHY1_LOG_EVT_DRU_EN, XHDMIPHY1_LOG_EVT_FRL_RECONFIG, XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_GT_LCPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_GT_QPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_GT_RECONFIG, XHDMIPHY1_LOG_EVT_GT_RPLL_CFG_ERR, XHDMIPHY1_LOG_EVT_GT_RX_RECONFIG, XHDMIPHY1_LOG_EVT_GT_TX_RECONFIG, XHDMIPHY1_LOG_EVT_GTRX_RST, XHDMIPHY1_LOG_EVT_GTTX_RST, XHDMIPHY1_LOG_EVT_HDMI20_ERR, XHDMIPHY1_LOG_EVT_INIT, XHDMIPHY1_LOG_EVT_LCPLL_LOCK, XHDMIPHY1_LOG_EVT_MMCM_ERR, XHDMIPHY1_LOG_EVT_NO_DRU, XHDMIPHY1_LOG_EVT_NO_QPLL_ERR, XHDMIPHY1_LOG_EVT_NONE, XHDMIPHY1_LOG_EVT_PPC_MSMTCH_ERR, XHDMIPHY1_LOG_EVT_QPLL_EN, XHDMIPHY1_LOG_EVT_QPLL_LOCK, XHDMIPHY1_LOG_EVT_QPLL_RECONFIG, XHDMIPHY1_LOG_EVT_QPLL_RST, XHDMIPHY1_LOG_EVT_RPLL_LOCK, XHDMIPHY1_LOG_EVT_RX_FREQ, XHDMIPHY1_LOG_EVT_RX_RST_DONE, XHDMIPHY1_LOG_EVT_RX_TMR, XHDMIPHY1_LOG_EVT_RXGPO_RE, XHDMIPHY1_LOG_EVT_RXPLL_EN, XHDMIPHY1_LOG_EVT_RXPLL_LOCK, XHDMIPHY1_LOG_EVT_RXPLL_RECONFIG, XHDMIPHY1_LOG_EVT_RXPLL_RST, XHDMIPHY1_LOG_EVT_SPDGRDE_ERR, XHDMIPHY1_LOG_EVT_TMDS_RECONFIG, XHDMIPHY1_LOG_EVT_TX_ALIGN, XHDMIPHY1_LOG_EVT_TX_ALIGN_TMOUT, XHDMIPHY1_LOG_EVT_TX_FREQ, XHDMIPHY1_LOG_EVT_TX_RST_DONE, XHDMIPHY1_LOG_EVT_TX_TMR, XHDMIPHY1_LOG_EVT_TXGPO_RE, XHDMIPHY1_LOG_EVT_TXPLL_EN, XHDMIPHY1_LOG_EVT_TXPLL_LOCK, XHDMIPHY1_LOG_EVT_TXPLL_RECONFIG, XHDMIPHY1_LOG_EVT_TXPLL_RST, XHDMIPHY1_LOG_EVT_USRCLK_ERR, XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR, XHDMIPHY1_LOG_EVT_VDCLK_HIGH_ERR, XHDMIPHY1_LOG_EVT_VID_RX_RST, XHDMIPHY1_LOG_EVT_VID_TX_RST, and XHdmiphy1_LogRead().
u16 XHdmiphy1_LogRead | ( | XHdmiphy1 * | InstancePtr | ) |
This function will read the last event from the log.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1_Log::DataBuffer, XHdmiphy1_Log::HeadIndex, XHdmiphy1::Log, and XHdmiphy1_Log::TailIndex.
Referenced by XHdmiphy1_LogDisplay().
void XHdmiphy1_LogReset | ( | XHdmiphy1 * | InstancePtr | ) |
This function will reset the driver's logginc mechanism.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
References XHdmiphy1_Log::HeadIndex, XHdmiphy1::Log, and XHdmiphy1_Log::TailIndex.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_LogWrite | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_LogEvent | Evt, | ||
u8 | Data | ||
) |
This function will insert an event in the driver's logginc mechanism.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Evt | is the event type to log. |
Data | is the associated data for the event. |
References XHdmiphy1_Log::DataBuffer, XHdmiphy1_Log::HeadIndex, XHdmiphy1::Log, XHdmiphy1::LogWriteCallback, XHdmiphy1::LogWriteRef, XHdmiphy1_Log::TailIndex, XHdmiphy1_Log::TimeRecord, and XHDMIPHY1_LOG_EVT_DUMMY.
Referenced by XHdmiphy1_ClkReconfig(), XHdmiphy1_DirReconfig(), XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiCfgCalcMmcmParam(), XHdmiphy1_HdmiCpllLockHandler(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxAlignDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiQpllLockHandler(), XHdmiphy1_HdmiQpllParam(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxMmcmLockHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxMmcmLockHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_MmcmStart(), XHdmiphy1_OutDivReconfig(), and XHdmiphy1_SetHdmiTxParam().
XHdmiphy1_Config* XHdmiphy1_LookupConfig | ( | u16 | DeviceId | ) |
This function looks for the device configuration based on the unique device ID.
The table XHdmiphy1_ConfigTable[] contains the configuration information for each device in the system.
DeviceId | is the unique device ID of the device being looked up. |
u8 XHdmiphy1_MmcmLocked | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function will get the lock status of the mixed-mode clock manager (MMCM) core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
void XHdmiphy1_MmcmLockedMaskEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Enable | ||
) |
This function will reset the mixed-mode clock manager (MMCM) core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
Enable | is an indicator whether to "Enable" the locked mask if set to 1. If set to 0: reset, then disable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), and XHdmiphy1_MmcmStart().
void XHdmiphy1_MmcmPowerDown | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Hold | ||
) |
This function will power down the mixed-mode clock manager (MMCM) core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
void XHdmiphy1_MmcmReset | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Hold | ||
) |
This function will reset the mixed-mode clock manager (MMCM) core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), and XHdmiphy1_MmcmStart().
void XHdmiphy1_MmcmSetClkinsel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_MmcmClkinsel | Sel | ||
) |
This function will set the CLKINSEL port of the MMCM.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
Sel | CLKINSEL value 0 - CLKIN1 1 - CLKIN2 |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), and XHdmiphy1_HdmiRxTimerTimeoutHandler().
void XHdmiphy1_MmcmStart | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function will start the mixed-mode clock manager (MMCM) core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Dir | is an indicator for TX or RX. |
References XHdmiphy1::Quads, XHdmiphy1_Quad::RxMmcm, XHdmiphy1_Quad::TxMmcm, XHDMIPHY1_LOG_EVT_RXPLL_RECONFIG, XHDMIPHY1_LOG_EVT_TXPLL_RECONFIG, XHdmiphy1_LogWrite(), XHdmiphy1_MmcmLockedMaskEnable(), and XHdmiphy1_MmcmReset().
Referenced by XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
u32 XHdmiphy1_OutDivReconfig | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir | ||
) |
This function will set the current output divider configuration over DRP.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID for which to write the settings for. |
Dir | is an indicator for RX or TX. |
References XHdmiphy1_Ch2Ids(), XHDMIPHY1_LOG_EVT_GT_RX_RECONFIG, XHDMIPHY1_LOG_EVT_GT_TX_RECONFIG, and XHdmiphy1_LogWrite().
Referenced by XHdmiphy1_HdmiRxTimerTimeoutHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
void XHdmiphy1_PatgenEnable | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
u8 | Enable | ||
) |
This function enables or disables the Pattern Generator for the GT Channel 4 when it isused to generate the TX TMDS Clock.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
Enable | TRUE/FALSE |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler(), and XHdmiphy1_HdmiTxClkDetFreqChangeHandler().
void XHdmiphy1_PatgenSetRatio | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
u64 | TxLineRate | ||
) |
This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
TxLineRate | in Mbps. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1::HdmiTxSampleRate, XHDMIPHY1_Patgen_Ratio_40, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiGtTxResetDoneLockHandler().
u32 XHdmiphy1_PllCalculator | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u32 | PllClkInFreqHz | ||
) |
This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to calculate the PLL values for. |
ChId | is the channel ID to calculate the PLL values for. |
Dir | is an indicator for TX or RX. |
PllClkInFreqHz | is the PLL input frequency on which to base the calculations on. A value of 0 indicates to use the currently configured quad PLL reference clock. A non-zero value indicates to ignore what is currently configured in SW, and use a custom frequency instead. |
References XHdmiphy1_Channel::LineRateHz, XHdmiphy1::Quads, XHdmiphy1_Ch2Ids(), and XHdmiphy1_GetQuadRefClkFreq().
Referenced by XHdmiphy1_ClkCalcParams().
u32 XHdmiphy1_PllInitialize | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_PllRefClkSelType | QpllRefClkSel, | ||
XHdmiphy1_PllRefClkSelType | CpllRefClkSel, | ||
XHdmiphy1_PllType | TxPllSelect, | ||
XHdmiphy1_PllType | RxPllSelect | ||
) |
This function will initialize the PLL selection for a given channel.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
QpllRefClkSel | is the QPLL reference clock selection for the quad. |
CpllRefClkSel | is the CPLL reference clock selection for the quad. |
TxPllSelect | is the reference clock selection for the quad's TX PLL dividers. |
RxPllSelect | is the reference clock selection for the quad's RX PLL dividers. |
References Pll2SysClkData(), Pll2SysClkOut(), XHdmiphy1_CfgPllRefClkSel(), XHdmiphy1_CfgSysClkDataSel(), XHdmiphy1_CfgSysClkOutSel(), and XHdmiphy1_WriteCfgRefClkSelReg().
u32 XHdmiphy1_PowerDownGtPll | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u8 | Hold | ||
) |
This function will power down the specified GT PLL.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to power down the PLL for. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
void XHdmiphy1_RegisterDebug | ( | XHdmiphy1 * | InstancePtr | ) |
This function prints out Video PHY register and GT Channel and Common DRP register contents.
InstancePtr | is a pointer to the Hdmiphy core instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1::HdmiIsQpllPresent, XHdmiphy1_Config::RxChannels, XHdmiphy1_Config::TxChannels, XHdmiphy1_DrpRd(), and XHdmiphy1_ReadReg.
u32 XHdmiphy1_ResetGtPll | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Hold | ||
) |
This function will reset the GT's PLL logic.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), and XHdmiphy1_HdmiUpdateClockSelection().
u32 XHdmiphy1_ResetGtTxRx | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Hold | ||
) |
This function will reset the GT's TX/RX logic.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_HdmiCpllLockHandler(), and XHdmiphy1_HdmiQpllLockHandler().
u32 XHdmiphy1_SelfTest | ( | XHdmiphy1 * | InstancePtr | ) |
This function runs a self-test on the XHdmiphy1 driver/device.
The sanity test checks whether or not all tested registers hold their default reset values.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, and XHdmiphy1_ReadReg.
void XHdmiphy1_SetBufgGtDiv | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_DirectionType | Dir, | ||
u8 | Div | ||
) |
This function obtains the divider value of the BUFG_GT peripheral.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
Dir | is an indicator for TX or RX |
Div | 3-bit divider value |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize(), and XHdmiphy1_HdmiTxTimerTimeoutHandler().
void XHdmiphy1_SetErrorCallback | ( | XHdmiphy1 * | InstancePtr, |
void * | CallbackFunc, | ||
void * | CallbackRef | ||
) |
This function installs a callback function for the HDMIPHY error conditions.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
Sample Function Call: CallbackFunc(CallbackRef, XHdmiphy1_ErrType);
References XHdmiphy1::ErrorCallback, and XHdmiphy1::ErrorRef.
void XHdmiphy1_SetHdmiCallback | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_HdmiHandlerType | HandlerType, | ||
void * | CallbackFunc, | ||
void * | CallbackRef | ||
) |
This function installs an HDMI callback function for the specified handler type.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
HandlerType | is the interrupt handler type which specifies which interrupt event to attach the callback for. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XHdmiphy1::HdmiRxInitCallback, XHdmiphy1::HdmiRxInitRef, XHdmiphy1::HdmiRxReadyCallback, XHdmiphy1::HdmiRxReadyRef, XHdmiphy1::HdmiTxInitCallback, XHdmiphy1::HdmiTxInitRef, XHdmiphy1::HdmiTxReadyCallback, XHdmiphy1::HdmiTxReadyRef, XHDMIPHY1_HDMI_HANDLER_RXINIT, XHDMIPHY1_HDMI_HANDLER_RXREADY, XHDMIPHY1_HDMI_HANDLER_TXINIT, and XHDMIPHY1_HDMI_HANDLER_TXREADY.
u32 XHdmiphy1_SetHdmiRxParam | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId | ||
) |
This function update/set the HDMI RX parameter.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
References XHdmiphy1::HdmiRxDruIsEnabled, XHdmiphy1_DruCalcCenterFreqHz(), XHdmiphy1_DruSetCenterFreqHz(), XHdmiphy1_GetPllType(), XHdmiphy1_GetRcfgChId(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiQpllParam(), and XHdmiphy1_WriteCfgRefClkSelReg().
Referenced by XHdmiphy1_HdmiRxTimerTimeoutHandler().
u32 XHdmiphy1_SetHdmiTxParam | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XVidC_PixelsPerClock | Ppc, | ||
XVidC_ColorDepth | Bpc, | ||
XVidC_ColorFormat | ColorFormat | ||
) |
This function update/set the HDMI TX parameter.
InstancePtr | is a pointer to the Hdmiphy core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Ppc | is the pixels per clock to set. |
Bpc | is the bits per color to set. |
ColorFormat | is the color format to set. |
References XHdmiphy1::Config, XHdmiphy1_Hdmi21Cfg::IsEnabled, XHdmiphy1_Config::Ppc, XHdmiphy1::Quads, XHdmiphy1::TxHdmi21Cfg, XHdmiphy1_Quad::TxMmcm, XHdmiphy1_ErrorHandler(), XHdmiphy1_HdmiCfgCalcMmcmParam(), XHdmiphy1_HdmiCpllParam(), XHdmiphy1_HdmiQpllParam(), XHDMIPHY1_LOG_EVT_PPC_MSMTCH_ERR, XHdmiphy1_LogWrite(), and XHdmiphy1_WriteCfgRefClkSelReg().
Referenced by XHdmiphy1_Hdmi21Config().
void XHdmiphy1_SetIntrHandler | ( | XHdmiphy1 * | InstancePtr, |
XHdmiphy1_IntrHandlerType | HandlerType, | ||
XHdmiphy1_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
This function installs a callback function for the specified handler type.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
HandlerType | is the interrupt handler type which specifies which interrupt event to attach the callback for. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XHdmiphy1::IntrCpllLockCallbackRef, XHdmiphy1::IntrCpllLockHandler, XHdmiphy1::IntrQpll1LockCallbackRef, XHdmiphy1::IntrQpll1LockHandler, XHdmiphy1::IntrQpllLockCallbackRef, XHdmiphy1::IntrQpllLockHandler, XHdmiphy1::IntrRxClkDetFreqChangeCallbackRef, XHdmiphy1::IntrRxClkDetFreqChangeHandler, XHdmiphy1::IntrRxMmcmLockCallbackRef, XHdmiphy1::IntrRxMmcmLockHandler, XHdmiphy1::IntrRxResetDoneCallbackRef, XHdmiphy1::IntrRxResetDoneHandler, XHdmiphy1::IntrRxTmrTimeoutCallbackRef, XHdmiphy1::IntrRxTmrTimeoutHandler, XHdmiphy1::IntrTxAlignDoneCallbackRef, XHdmiphy1::IntrTxAlignDoneHandler, XHdmiphy1::IntrTxClkDetFreqChangeCallbackRef, XHdmiphy1::IntrTxClkDetFreqChangeHandler, XHdmiphy1::IntrTxMmcmLockCallbackRef, XHdmiphy1::IntrTxMmcmLockHandler, XHdmiphy1::IntrTxResetDoneCallbackRef, XHdmiphy1::IntrTxResetDoneHandler, XHdmiphy1::IntrTxTmrTimeoutCallbackRef, and XHdmiphy1::IntrTxTmrTimeoutHandler.
Referenced by XHdmiphy1_HdmiIntrHandlerCallbackInit().
void XHdmiphy1_SetLogCallback | ( | XHdmiphy1 * | InstancePtr, |
u64 * | CallbackFunc, | ||
void * | CallbackRef | ||
) |
This function installs an asynchronous callback function for the LogWrite API:
InstancePtr | is a pointer to the XHdmiphy1 instance. |
CallbackFunc | is the address of the callback function. |
CallbackRef | is a user data item that will be passed to the callback function when it is invoked. |
References XHdmiphy1::LogWriteCallback, and XHdmiphy1::LogWriteRef.
u32 XHdmiphy1_SetPolarity | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Polarity | ||
) |
This function will set/clear the TX/RX polarity bit.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
Polarity | 0-Not inverted 1-Inverted |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
u32 XHdmiphy1_SetPrbsSel | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
XHdmiphy1_PrbsPattern | Pattern | ||
) |
This function will set the TX/RXPRBSEL of the GT.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
Pattern | is the pattern XHdmiphy1_PrbsPattern |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Ch2Ids(), XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
void XHdmiphy1_SetRxLpm | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
XHdmiphy1_DirectionType | Dir, | ||
u8 | Enable | ||
) |
This function will enable or disable the LPM logic in the Video PHY core.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Dir | is an indicator for TX or RX. |
Enable | will enable (if 1) or disable (if 0) the LPM logic. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_SetTxPostCursor | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u8 | Pc | ||
) |
This function will set the TX post-curosr value for a given channel.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Pe | is the pre-emphasis value to write. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_SetTxPreEmphasis | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u8 | Pe | ||
) |
This function will set the TX pre-emphasis value for a given channel.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Pe | is the pre-emphasis value to write. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
void XHdmiphy1_SetTxVoltageSwing | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u8 | Vs | ||
) |
This function will set the TX voltage swing value for a given channel.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID to operate on. |
Vs | is the voltage swing value to write. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Config::XcvrType, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi_CfgInitialize().
u32 XHdmiphy1_TxPrbsForceError | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId, | ||
XHdmiphy1_ChannelId | ChId, | ||
u8 | ForceErr | ||
) |
This function will set the TX/RXPRBSEL of the GT.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
ChId | is the channel ID which to operate on. |
Dir | is an indicator for TX or RX. |
ForceErr | 0-No Error 1-Force Error |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_ReadReg, and XHdmiphy1_WriteReg.
void XHdmiphy1_WaitUs | ( | XHdmiphy1 * | InstancePtr, |
u32 | MicroSeconds | ||
) |
This function is the delay/sleep function for the XHdmiphy1 driver.
For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
InstancePtr | is a pointer to the XHdmiphy1 instance. |
MicroSeconds | is the number of microseconds to delay/sleep for. |
References XHdmiphy1::IsReady, and XHdmiphy1::UserTimerWaitUs.
u32 XHdmiphy1_WriteCfgRefClkSelReg | ( | XHdmiphy1 * | InstancePtr, |
u8 | QuadId | ||
) |
This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels.
InstancePtr | is a pointer to the XHdmiphy1 core instance. |
QuadId | is the GT quad ID to operate on. |
References XHdmiphy1_Config::BaseAddr, XHdmiphy1::Config, XHdmiphy1_Channel::CpllRefClkSel, XHdmiphy1::Quads, XHdmiphy1_Channel::RxDataRefClkSel, XHdmiphy1_Channel::RxOutRefClkSel, XHdmiphy1_Channel::TxDataRefClkSel, XHdmiphy1_Channel::TxOutRefClkSel, XHdmiphy1_Config::XcvrType, and XHdmiphy1_WriteReg.
Referenced by XHdmiphy1_Hdmi20Config(), XHdmiphy1_Hdmi21Config(), XHdmiphy1_HdmiRxTimerTimeoutHandler(), XHdmiphy1_HdmiTxTimerTimeoutHandler(), XHdmiphy1_PllInitialize(), XHdmiphy1_SetHdmiRxParam(), and XHdmiphy1_SetHdmiTxParam().