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wdttb
Xilinx SDK Drivers API Documentation
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Macros | |
#define | XWDTTB_HW_H_ |
Prevent circular inclusions by using protection macros. More... | |
Register offsets for the WWDT core with Generic & windowing | |
feature with basic mode. Each register is 32 bits. | |
#define | XWT_MWR_OFFSET 0x0000U |
Master Write Control Register Offset. More... | |
#define | XWT_ESR_OFFSET 0x0004U |
Enable & Status Register Offset. More... | |
#define | XWT_FCR_OFFSET 0x0008U |
Function Control Register Register Offset. More... | |
#define | XWT_FWR_OFFSET 0x000CU |
First Window Configuration Register Offset. More... | |
#define | XWT_SWR_OFFSET 0x0010U |
Second Window Configuration Register Offset. More... | |
#define | XWT_TSR0_WWDT_OFFSET 0x0018U |
Task Signature Register 0 Offset for WWDT. More... | |
#define | XWT_TSR1_WWDT_OFFSET 0x001CU |
Task Signature Register 1 Offset for WWDT. More... | |
#define | XWT_STR_WWDT_OFFSET 0x0020U |
Second Sequence Timer Register Offset for WWDT. More... | |
#define | XWT_TSR0_OFFSET 0x0014U |
Task Signature Register 0 Offset. More... | |
#define | XWT_TSR1_OFFSET 0x0018U |
Task Signature Register 1 Offset. More... | |
#define | XWT_STR_OFFSET 0x001CU |
Second Sequence Timer Register Offset. More... | |
#define | XWT_SSTWR_OFFSET 0x0014U |
Second Sequence Timer Window Configuration Register Offset. More... | |
#define | XWT_TFR_OFFSET 0x0024U |
Token Feedback Register Offset. More... | |
#define | XWT_TRR_OFFSET 0x0028U |
Token Response Register offset. More... | |
#define | XWT_IENR_OFFSET 0x002CU |
Interrupt Enable Register Offset. More... | |
#define | XWT_IDR_OFFSET 0x0030U |
Interrupt Disable Register Offset. More... | |
#define | XWT_IMR_OFFSET 0x0034U |
Interrupt Mask Register Offset. More... | |
#define | XWT_GWRR_OFFSET 0x1000U |
Generic Watchdog Refresh Register Offset. More... | |
#define | XWT_GWCSR_OFFSET 0x2000U |
Generic Watchdog Control and Status Register Offset. More... | |
#define | XWT_GWOR_OFFSET 0x2008U |
Generic Watchdog Offset Register Offset. More... | |
#define | XWT_GWCVR0_OFFSET 0x2010U |
Generic Watchdog Compare Value Register 0 Offset. More... | |
#define | XWT_GWCVR1_OFFSET 0x2014U |
Generic Watchdog Compare Value Register 1 Offset. More... | |
#define | XWT_GW_WR_OFFSET 0x2FD0U |
Generic Watchdog Warm Reset Register Offset. More... | |
Register offsets for the AXI Timebase WDT core. Each register is 32 | |
bits. | |
#define | XWT_TWCSR0_OFFSET 0x00U |
Control/Status Register 0 Offset. More... | |
#define | XWT_TWCSR1_OFFSET 0x04U |
Control/Status Register 1 Offset. More... | |
#define | XWT_TBR_OFFSET 0x08U |
Timebase Register Offset. More... | |
Control/Status Register 0 bits | |
#define | XWT_CSR0_WRS_MASK 0x00000008U |
Reset status Mask. More... | |
#define | XWT_CSR0_WDS_MASK 0x00000004U |
Timer state Mask. More... | |
#define | XWT_CSR0_EWDT1_MASK 0x00000002U |
Enable bit 1 Mask. More... | |
Control/Status Register 0/1 bits | |
#define | XWT_CSRX_EWDT2_MASK 0x00000001U |
Enable bit 2 Mask. More... | |
Master Write Control bits | |
#define | XWT_MWR_AEN_MASK 0x00000002U |
Always Enable Mask. More... | |
#define | XWT_MWR_MWC_MASK 0x00000001U |
Master Write Control Mask. More... | |
Enable & Status Register bits | |
#define | XWT_ESR_LBE_MASK 0x07000000U |
Last Bad Event Mask. More... | |
#define | XWT_ESR_FCV_MASK 0x00700000U |
Fail Counter Value Mask. More... | |
#define | XWT_ESR_WRP_MASK 0x00020000U |
Watchdog Reset Pending Mask. More... | |
#define | XWT_ESR_WINT_MASK 0x00010000U |
Watchdog Interrupt Mask. More... | |
#define | XWT_ESR_WSW_MASK 0x00000100U |
Watchdog Second Window Mask. More... | |
#define | XWT_ESR_WCFG_MASK 0x00000002U |
Wrong Configuration Mask. More... | |
#define | XWT_ESR_WEN_MASK 0x00000001U |
Window WDT Enable Mask. More... | |
#define | XWT_ESR_LBE_SHIFT 24U |
Last Bad Event Shift. More... | |
#define | XWT_ESR_FCV_SHIFT 20U |
Fail Counter Value Shift. More... | |
#define | XWT_ESR_WRP_SHIFT 17U |
Watchdog Reset Pending Shift. More... | |
#define | XWT_ESR_WINT_SHIFT 16U |
Watchdog Interrupt Shift. More... | |
#define | XWT_ESR_WSW_SHIFT 8U |
Watchdog Second Window Shift. More... | |
#define | XWT_ESR_WCFG_SHIFT 1U |
Wrong Configuration Shift. More... | |
Function Control Register bits | |
#define | XWT_FCR_SBC_MASK 0x0000FF00U |
Selected Byte Count Mask. More... | |
#define | XWT_FCR_BSS_MASK 0x000000C0U |
Byte Segment Selection Mask. More... | |
#define | XWT_FCR_SSTE_MASK 0x00000010U |
Second Sequence Timer Enable Mask. More... | |
#define | XWT_FCR_PSME_MASK 0x00000008U |
Program Sequence Monitor Enable Mask. More... | |
#define | XWT_FCR_FCE_MASK 0x00000004U |
Fail Counter Enable Mask. More... | |
#define | XWT_FCR_WM_MASK 0x00000002U |
Window WDT Mode Mask. More... | |
#define | XWT_FCR_WDP_MASK 0x00000001U |
Window WDT Disable Protection Mask. More... | |
#define | XWT_FCR_SBC_SHIFT 8U |
Selected Byte Count Shift. More... | |
#define | XWT_FCR_BSS_SHIFT 6U |
Byte Segment Selection Shift. More... | |
#define | XWT_FCR_SSTE_SHIFT 4U |
Second Sequence Timer Enable Shift. More... | |
#define | XWT_FCR_WM_SHIFT 1U |
Window WDT Mode Shift. More... | |
Generic Watchdog Control and Status Register bits | |
#define | XWT_GWCSR_GWEN_MASK 0x00000001U |
Watchdog enable bit. More... | |
#define | XWT_GWCSR_GWS1_MASK 0x00000002U |
Generic_wdt_interrupt bit. More... | |
#define | XWT_GWCSR_GWS2_MASK 0x00000004U |
Generic_wdt_reset bit. More... | |
Register access macro definition | |
#define | XWdtTb_In32 Xil_In32 |
Input Operations. More... | |
#define | XWdtTb_Out32 Xil_Out32 |
Output Operations. More... | |
#define | XWdtTb_ReadReg(BaseAddress, RegOffset) XWdtTb_In32((BaseAddress) + ((u32)RegOffset)) |
Read from the specified WdtTb core's register. More... | |
#define | XWdtTb_WriteReg(BaseAddress, RegOffset, RegisterValue) XWdtTb_Out32((BaseAddress) + ((u32)RegOffset), (u32)(RegisterValue)) |
Write to the specified WdtTb core's register. More... | |