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aiengine
Xilinx SDK Drivers API Documentation
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This file contains the global initialization functions for the Tile.
This is applicable for both the AIE tiles and Shim tiles.
MODIFICATION HISTORY:
Ver Who Date Changes
1.0 Naresh 03/14/2018 Initial creation 1.1 Naresh 04/12/2018 Code changed to fix CR#999685 1.2 Naresh 05/23/2018 Updated code to fix CR#999693 1.3 Naresh 07/11/2018 Updated copyright info 1.4 Nishad 12/05/2018 Renamed ME attributes to AIE 1.5 Jubaer 05/24/2019 Add PL type on TileType attribute 1.6 Nishad 07/31/2019 Add support for RPU baremetal
XAieGbl_Config | XAieGbl_ConfigTable [] |
XAIE_BASE_ARRAY_ADDR_OFFSET macro defines the AI Engine's base address offset value. More... | |
void | XAieGbl_CfgInitialize (XAieGbl *InstancePtr, XAieGbl_Tile *TileInstPtr, XAieGbl_Config *ConfigPtr) |
This is the global initialization function for all the tiles of the AIE array and also for the Shim tiles. More... | |
void | XAieGbl_HwInit (XAieGbl_HwCfg *CfgPtr) |
This is the routine to initialize the HW configuration. More... | |
void XAieGbl_CfgInitialize | ( | XAieGbl * | InstancePtr, |
XAieGbl_Tile * | TileInstPtr, | ||
XAieGbl_Config * | ConfigPtr | ||
) |
This is the global initialization function for all the tiles of the AIE array and also for the Shim tiles.
The initialization involves programming the Tile instance data structure with the required parameters of the tile, like base addresses for Core module/Memory module/NoC module/Pl module, Stream switch configuration, Lock configuration etc.
InstancePtr | - Global AIE instance structure. |
ConfigPtr | - Global AIE configuration pointer. |
References XAieGbl_Config::ArrOffset, XAieGbl_Tile::ColId, XAieGbl::Config, XAieGbl_Tile::CoreModAddr, XAieGbl_Tile::IsReady, XAieGbl::IsReady, XAieGbl_Tile::LockAddr, XAieGbl_Tile::MemModAddr, XAieGbl_Tile::NocModAddr, XAieGbl_Config::NumCols, XAieGbl_Config::NumRows, XAieGbl_Tile::PlModAddr, XAieGbl_Tile::RowId, XAieGbl_Tile::StrmSwAddr, XAieGbl_Tile::TileAddr, XAieGbl_Tile::TileType, XAieLib_InitDev(), and XAieLib_InitTile().
Referenced by main().
void XAieGbl_HwInit | ( | XAieGbl_HwCfg * | CfgPtr | ) |
This is the routine to initialize the HW configuration.
CfgPtr,: | Pointer to the HW configuration data structure. |
References XAieGbl_HwCfg::ArrayOff, XAieGbl_Config::ArrOffset, XAieGbl_Config::NumCols, XAieGbl_HwCfg::NumCols, XAieGbl_Config::NumRows, and XAieGbl_HwCfg::NumRows.
Referenced by main().
XAieGbl_Config XAieGbl_ConfigTable[] |
XAIE_BASE_ARRAY_ADDR_OFFSET macro defines the AI Engine's base address offset value.
This value is left-shift by 30-bits to obtain the complete physical address of AIE.
FIXME: The Makefile used to compile AIE application for ARM Cortex-R5, by default, adds 'ARMR5' compiler flag. Since the XSA file generated using the latest tool hides the remapped address of AIE for R5, this compiler flag can be leveraged to hardcode the value of XAIE_BASE_ARRAY_ADDR_OFFSET. When AIE adress is available in RPU address map, the aiengine.tcl file for BareMetal and XAieIO_Init API for Linux flow must be modified to remove the hardcoded value. For BareMetal applications, the XAIE_BASE_ARRAY_ADDR_OFFSET value needs to be parsed by the TCL script from the XSA file. On the other hand, for the Linux application, this value needs to be parsed from the device tree.
XAIE_BASE_ARRAY_ADDR_OFFSET macro defines the AI Engine's base address offset value.