spdif
Xilinx SDK Drivers API Documentation
xspdif_hw.h File Reference

Macros

#define XSPDIF_CLK_4   4
 Clock divide by 4. More...
 
#define XSPDIF_CLK_8   8
 Clock divide by 8. More...
 
#define XSPDIF_CLK_16   16
 Clock divide by 16. More...
 
#define XSPDIF_CLK_24   24
 Clock divide by 24. More...
 
#define XSPDIF_CLK_32   32
 Clock divide by 32. More...
 
#define XSPDIF_CLK_48   48
 Clock divide by 48. More...
 
#define XSPDIF_CLK_64   64
 Clock divide by 64. More...
 
Register Map

Register offsets for the XSpdif device.

#define XSPDIF_GLOBAL_INTERRUPT_ENABLE_OFFSET   0x1C
 Device Global interrupt enable register. More...
 
#define XSPDIF_INTERRUPT_STATUS_REGISTER_OFFSET   0x20
 IP Interrupt Status Register. More...
 
#define XSPDIF_INTERRUPT_ENABLE_REGISTER_OFFSET   0x28
 IP interrupt enable Register. More...
 
#define XSPDIF_SOFT_RESET_REGISTER_OFFSET   0x40
 Soft Reset Register. More...
 
#define XSPDIF_CONTROL_REGISTER_OFFSET   0x44
 Control Register. More...
 
#define XSPDIF_STATUS_REGISTER_OFFSET   0x48
 Status Register. More...
 
#define XSPDIF_CHANNEL_STATUS_REGISTER0_OFFSET   0x4C
 Audio Channel Status bits 0 to 31. More...
 
#define XSPDIF_CHANNEL_A_USER_DATA_REGISTER0_OFFSET   0x64
 Channel A user data bits 0 to 31. More...
 
#define XSPDIF_CHANNEL_B_USER_DATA_REGISTER0_OFFSET   0x7C
 Channel B user data bits 0 to 31. More...
 
Core Configuration Register masks and shifts
#define XSPDIF_CORE_ENABLE_SHIFT   (0)
 Is XSPDIF Core Enable bit shift. More...
 
#define XSPDIF_CORE_ENABLE_MASK   (1 << XSPDIF_CORE_ENABLE_SHIFT)
 Is XSPDIF Core Enable bit mask. More...
 
#define XSPDIF_FIFO_FLUSH_SHIFT   (1)
 Is XSPDIF Reset FIFO bit shift. More...
 
#define XSPDIF_FIFO_FLUSH_MASK   (1 << XSPDIF_FIFO_FLUSH_SHIFT)
 Is XSPDIF Reset FIFO bit mask. More...
 
#define XSPDIF_CLOCK_CONFIG_BITS_SHIFT   (2)
 Is XSPDIF clock configuration bits shift. More...
 
#define XSPDIF_CLOCK_CONFIG_BITS_MASK   ((0xF) << XSPDIF_CLOCK_CONFIG_BITS_SHIFT)
 Is XSPDIF clock configuration bits mask. More...
 
#define XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT   (0)
 XSPDIF sample clock count shift. More...
 
#define XSPDIF_SAMPLE_CLOCK_COUNT_MASK   ((0X3FF) << XSPDIF_SAMPLE_CLOCK_COUNT_SHIFT)
 XSPDIF sample clock count mask. More...
 
Interrupt masks and shifts
#define XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT   (0)
 Transmitter or Receiver FIFO Full Interrupt bit shift. More...
 
#define XSPDIF_TX_OR_RX_FIFO_FULL_MASK   (1 << XSPDIF_TX_OR_RX_FIFO_FULL_SHIFT)
 Transmitter or Receiver FIFO Full Interrupt bit mask. More...
 
#define XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT   (1)
 Transmitter or Receiver FIFO Empty Interrupt bit shift. More...
 
#define XSPDIF_TX_OR_RX_FIFO_EMPTY_MASK   (1 << XSPDIF_TX_OR_RX_FIFO_EMPTY_SHIFT)
 Transmitter or Receiver FIFO Empty Interrupt bit mask. More...
 
#define XSPDIF_START_OF_BLOCK_SHIFT   (2)
 Start of Block Interrupt bit mask ( in Receive mode) More...
 
#define XSPDIF_START_OF_BLOCK_MASK   (1 << XSPDIF_START_OF_BLOCK_SHIFT)
 Transmitter or Receiver FIFO Full Interrupt bit shift. More...
 
#define XSPDIF_BMC_ERROR_SHIFT   (3)
 BMC Error Interrupt bit shift. More...
 
#define XSPDIF_BMC_ERROR_MASK   (1 << XSPDIF_BMC_ERROR_SHIFT)
 BMC Error Interrupt bit mask. More...
 
#define XSPDIF_PREAMBLE_ERROR_SHIFT   (4)
 Preamble error Interrupt bit shift. More...
 
#define XSPDIF_PREAMBLE_ERROR_MASK   (1 << XSPDIF_PREAMBLE_ERROR_SHIFT)
 Preamble error Interrupt bit mask. More...
 
#define XSPDIF_GINTR_ENABLE_SHIFT   (31)
 Global interrupt enable bit shift. More...
 
#define XSPDIF_GINTR_ENABLE_MASK   (1 << XSPDIF_GINTR_ENABLE_SHIFT)
 Global interrupt enable bit mask. More...
 
Register access macro definition
#define XSpdif_In32   Xil_In32
 Input Operations. More...
 
#define XSpdif_Out32   Xil_Out32
 Output Operations. More...
 
#define XSpdif_ReadReg(BaseAddress, RegOffset)   XSpdif_In32((BaseAddress) + ((u32)RegOffset))
 This macro reads a value from a XSpdif register. More...
 
#define XSpdif_WriteReg(BaseAddress, RegOffset, Data)   XSpdif_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
 This macro writes a value to a XSpdif register. More...