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axidma
Xilinx SDK Drivers API Documentation
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This file demonstrates how to use the xaxidma driver on the Xilinx AXI DMA core (AXIDMA) to transfer packets in interrupt mode when the AXIDMA core is configured in Scatter Gather Mode.
This example demonstrates how to use cyclic DMA mode feature. This program will recycle the NUMBER_OF_BDS_TO_TRANSFER buffer descriptors to specified number of cyclic transfers defined in "NUMBER_OF_CYCLIC_TRANSFERS".
This code assumes a loopback hardware widget is connected to the AXI DMA core for data packet loopback.
To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.
Make sure that MEMORY_BASE is defined properly as per the HW system. The h/w system built in Area mode has a maximum DDR memory limit of 64MB. In throughput mode, it is 512MB. These limits are need to ensured for proper operation of this code.
MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 9.4 adk 25/07/17 Initial version. 9.6 rsp 02/14/18 Support data buffers above 4GB.Use UINTPTR for storing and typecasting buffer address(CR-992638). 9.8 rsp 07/24/18 Set TX DMACR[Cyclic BD enable] before starting DMA operation i.e. in TxSetup.
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int | main (void) |
Main function. More... | |
int main | ( | void | ) |
Main function.
This function is the main entry of the interrupt test. It does the following:
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