csudma
Xilinx SDK Drivers API Documentation
Csudma_v1_3

Macros

#define XCSUDMA_H_
 Prevent circular inclusions by using protection macros. More...
 
#define XCSUDMA_HW_H_
 Prevent circular inclusions by using protection macros. More...
 
#define XCsuDma_In32   Xil_In32
 Input operation. More...
 
#define XCsuDma_Out32   Xil_Out32
 Output operation. More...
 
#define XCsuDma_ReadReg(BaseAddress, RegOffset)   XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
 This macro reads the given register. More...
 
#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data)   XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
 This macro writes the value into the given register. More...
 

Enumerations

enum  XCsuDma_Channel { XCSUDMA_SRC_CHANNEL = 0U, XCSUDMA_DST_CHANNEL }
 This typedef contains CSU_DMA Channel Types. More...
 

Functions

s32 XCsuDma_CfgInitialize (XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, u32 EffectiveAddr)
 This function initializes an CSU_DMA core. More...
 
void XCsuDma_Transfer (XCsuDma *InstancePtr, XCsuDma_Channel Channel, UINTPTR Addr, u32 Size, u8 EnDataLast)
 This function sets the starting address and amount(size) of the data to be transfered from/to the memory through the AXI interface. More...
 
void XCsuDma_64BitTransfer (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast)
 This function sets the starting address and amount(size) of the data to be transfered from/to the memory through the AXI interface. More...
 
u64 XCsuDma_GetAddr (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 This function returns the current address location of the memory, from where it has to read the data(SRC) or the location where it has to write the data (DST) based on the channel selection. More...
 
u32 XCsuDma_GetSize (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 This function returns the size of the data yet to be transfered from memory to CSU_DMA or CSU_DMA to memory based on the channel selection. More...
 
void XCsuDma_Pause (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
 This function pause the Channel data tranfer to/from memory or to/from stream based on pause type. More...
 
s32 XCsuDma_IsPaused (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
 This functions checks whether Channel's memory or stream is paused or not based on the given pause type. More...
 
void XCsuDma_Resume (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_PauseType Type)
 This function resumes the channel if it is in paused state and continues where it has left or no effect if it is not in paused state, based on the type of pause. More...
 
u32 XCsuDma_GetCheckSum (XCsuDma *InstancePtr)
 This function returns the sum of all the data read from AXI memory. More...
 
void XCsuDma_ClearCheckSum (XCsuDma *InstancePtr)
 This function clears the check sum of the data read from AXI memory. More...
 
void XCsuDma_SetConfig (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_Configure *ConfigurValues)
 This function cofigures all the values of CSU_DMA's Channels with the values of updated XCsuDma_Configure structure. More...
 
void XCsuDma_GetConfig (XCsuDma *InstancePtr, XCsuDma_Channel Channel, XCsuDma_Configure *ConfigurValues)
 This function updates XCsuDma_Configure structure members with the cofigured values of CSU_DMA's Channel. More...
 
u32 XCsuDma_IntrGetStatus (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 This function returns interrupt status read from Interrupt Status Register. More...
 
void XCsuDma_IntrClear (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
 This function clears interrupt(s). More...
 
void XCsuDma_EnableIntr (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
 This function enables the interrupt(s). More...
 
void XCsuDma_DisableIntr (XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask)
 This function disables the interrupt(s). More...
 
u32 XCsuDma_GetIntrMask (XCsuDma *InstancePtr, XCsuDma_Channel Channel)
 This function returns the interrupt mask to know which interrupts are enabled and which of them were disaled. More...
 
s32 XCsuDma_SelfTest (XCsuDma *InstancePtr)
 This function runs a self-test on the driver and hardware device. More...
 
XCsuDma_ConfigXCsuDma_LookupConfig (u16 DeviceId)
 XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure based on the unique device id, DeviceId. More...
 

Registers offsets

#define XCSUDMA_ADDR_OFFSET   0x000
 Address Register Offset. More...
 
#define XCSUDMA_SIZE_OFFSET   0x004
 Size Register Offset. More...
 
#define XCSUDMA_STS_OFFSET   0x008
 Status Register Offset. More...
 
#define XCSUDMA_CTRL_OFFSET   0x00C
 Control Register Offset. More...
 
#define XCSUDMA_CRC_OFFSET   0x010
 CheckSum Register Offset. More...
 
#define XCSUDMA_I_STS_OFFSET   0x014
 Interrupt Status Register Offset. More...
 
#define XCSUDMA_I_EN_OFFSET   0x018
 Interrupt Enable Register Offset. More...
 
#define XCSUDMA_I_DIS_OFFSET   0x01C
 Interrupt Disable Register Offset. More...
 
#define XCSUDMA_I_MASK_OFFSET   0x020
 Interrupt Mask Register Offset. More...
 
#define XCSUDMA_CTRL2_OFFSET   0x024
 Interrupt Control Register 2 Offset. More...
 
#define XCSUDMA_ADDR_MSB_OFFSET   0x028
 Address's MSB Register Offset. More...
 
#define XCSUDMA_SAFETY_CHK_OFFSET   0xFF8
 Safety Check Field Offset. More...
 
#define XCSUDMA_FUTURE_ECO_OFFSET   0xFFC
 Future potential ECO Offset. More...
 

CSU Base address and CSU_DMA reset offset

#define XCSU_BASEADDRESS   0xFFCA0000U
 CSU Base Address. More...
 
#define XCSU_DMA_RESET_OFFSET   0x0000000CU
 CSU_DMA Reset offset. More...
 

CSU_DMA Reset register bit masks

#define XCSUDMA_RESET_SET_MASK   0x00000001U
 Reset set mask. More...
 
#define XCSUDMA_RESET_UNSET_MASK   0x00000000U
 Reset unset mask. More...
 

Offset difference for Source and destination

#define XCSUDMA_OFFSET_DIFF   0x00000800U
 Offset difference for source and destination channels. More...
 

Address register bit masks

#define XCSUDMA_ADDR_MASK   0xFFFFFFFCU
 Address mask. More...
 
#define XCSUDMA_ADDR_LSB_MASK   0x00000003U
 Address alignment check mask. More...
 

Size register bit masks and shifts

#define XCSUDMA_SIZE_MASK   0x1FFFFFFCU
 Mask for size. More...
 
#define XCSUDMA_LAST_WORD_MASK   0x00000001U
 Last word check bit mask. More...
 
#define XCSUDMA_SIZE_SHIFT   2U
 Shift for size. More...
 

Status register bit masks and shifts

#define XCSUDMA_STS_DONE_CNT_MASK   0x0000E000U
 Count done mask. More...
 
#define XCSUDMA_STS_FIFO_LEVEL_MASK   0x00001FE0U
 FIFO level mask. More...
 
#define XCUSDMA_STS_OUTSTDG_MASK   0x0000001EU
 No.of outstanding read/write commands mask. More...
 
#define XCSUDMA_STS_BUSY_MASK   0x00000001U
 Busy mask. More...
 
#define XCSUDMA_STS_DONE_CNT_SHIFT   13U
 Shift for Count done. More...
 
#define XCSUDMA_STS_FIFO_LEVEL_SHIFT   5U
 Shift for FIFO level. More...
 
#define XCUSDMA_STS_OUTSTDG_SHIFT   1U
 Shift for No.of outstanding read/write commands. More...
 

Control register bit masks and shifts

#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK   0xFE000000U
 SSS FIFO threshold value mask. More...
 
#define XCSUDMA_CTRL_APB_ERR_MASK   0x01000000U
 APB register access error mask. More...
 
#define XCSUDMA_CTRL_ENDIAN_MASK   0x00800000U
 Endianess mask. More...
 
#define XCSUDMA_CTRL_BURST_MASK   0x00400000U
 AXI burst type mask. More...
 
#define XCSUDMA_CTRL_TIMEOUT_MASK   0x003FFC00U
 Time out value mask. More...
 
#define XCSUDMA_CTRL_FIFO_THRESH_MASK   0x000003FCU
 FIFO threshold mask. More...
 
#define XCSUDMA_CTRL_PAUSE_MEM_MASK   0x00000001U
 Memory pause mask. More...
 
#define XCSUDMA_CTRL_PAUSE_STRM_MASK   0x00000002U
 Stream pause mask. More...
 
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT   25U
 SSS FIFO threshold shift. More...
 
#define XCSUDMA_CTRL_APB_ERR_SHIFT   24U
 APB error shift. More...
 
#define XCSUDMA_CTRL_ENDIAN_SHIFT   23U
 Endianess shift. More...
 
#define XCSUDMA_CTRL_BURST_SHIFT   22U
 AXI burst type shift. More...
 
#define XCSUDMA_CTRL_TIMEOUT_SHIFT   10U
 Time out value shift. More...
 
#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT   2U
 FIFO thresh shift. More...
 

CheckSum register bit masks

#define XCSUDMA_CRC_RESET_MASK   0x00000000U
 Mask to reset value of check sum. More...
 

Interrupt Enable/Disable/Mask/Status registers bit masks

#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK   0x00000001U
 FIFO overflow mask, it is valid only to Destination Channel. More...
 
#define XCSUDMA_IXR_INVALID_APB_MASK   0x00000040U
 Invalid APB access mask. More...
 
#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK   0x00000020U
 FIFO threshold hit indicator mask. More...
 
#define XCSUDMA_IXR_TIMEOUT_MEM_MASK   0x00000010U
 Time out counter expired to access memory mask. More...
 
#define XCSUDMA_IXR_TIMEOUT_STRM_MASK   0x00000008U
 Time out counter expired to access stream mask. More...
 
#define XCSUDMA_IXR_AXI_WRERR_MASK   0x00000004U
 AXI Read/Write error mask. More...
 
#define XCSUDMA_IXR_DONE_MASK   0x00000002U
 Done mask. More...
 
#define XCSUDMA_IXR_MEM_DONE_MASK   0x00000001U
 Memory done mask, it is valid only for source channel. More...
 
#define XCSUDMA_IXR_SRC_MASK   0x0000007FU
 ((XCSUDMA_IXR_INVALID_APB_MASK)| (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK)) More...
 
#define XCSUDMA_IXR_DST_MASK   0x000000FEU
 ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK)) More...
 

Control register 2 bit masks and shifts

#define XCSUDMA_CTRL2_RESERVED_MASK   0x083F0000U
 Reserved bits mask. More...
 
#define XCSUDMA_CTRL2_ACACHE_MASK   0X07000000U
 AXI CACHE mask. More...
 
#define XCSUDMA_CTRL2_ROUTE_MASK   0x00800000U
 Route mask. More...
 
#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK   0x00400000U
 Time out counters enable mask. More...
 
#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK   0x0000FFF0U
 Time out pre mask. More...
 
#define XCSUDMA_CTRL2_MAXCMDS_MASK   0x0000000FU
 Maximum commands mask. More...
 
#define XCSUDMA_CTRL2_RESET_MASK   0x0000FFF8U
 Reset mask. More...
 
#define XCSUDMA_CTRL2_ACACHE_SHIFT   24U
 Shift for AXI R/W CACHE. More...
 
#define XCSUDMA_CTRL2_ROUTE_SHIFT   23U
 Shift for route. More...
 
#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT   22U
 Shift for Timeout enable feild. More...
 
#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT   4U
 Shift for Timeout pre feild. More...
 

MSB Address register bit masks and shifts

#define XCSUDMA_MSB_ADDR_MASK   0x0001FFFFU
 MSB bits of address mask. More...
 
#define XCSUDMA_MSB_ADDR_SHIFT   32U
 Shift for MSB bits of address. More...
 

Macro Definition Documentation

◆ XCSU_BASEADDRESS

#define XCSU_BASEADDRESS   0xFFCA0000U

#include <xcsudma_hw.h>

CSU Base Address.

◆ XCSU_DMA_RESET_OFFSET

#define XCSU_DMA_RESET_OFFSET   0x0000000CU

#include <xcsudma_hw.h>

CSU_DMA Reset offset.

◆ XCSUDMA_ADDR_LSB_MASK

#define XCSUDMA_ADDR_LSB_MASK   0x00000003U

#include <xcsudma_hw.h>

Address alignment check mask.

Referenced by XCsuDma_Transfer().

◆ XCSUDMA_ADDR_MASK

#define XCSUDMA_ADDR_MASK   0xFFFFFFFCU

#include <xcsudma_hw.h>

Address mask.

Referenced by XCsuDma_64BitTransfer(), and XCsuDma_Transfer().

◆ XCSUDMA_ADDR_MSB_OFFSET

#define XCSUDMA_ADDR_MSB_OFFSET   0x028

#include <xcsudma_hw.h>

Address's MSB Register Offset.

Referenced by XCsuDma_64BitTransfer(), XCsuDma_GetAddr(), and XCsuDma_Transfer().

◆ XCSUDMA_ADDR_OFFSET

#define XCSUDMA_ADDR_OFFSET   0x000

#include <xcsudma_hw.h>

Address Register Offset.

Referenced by XCsuDma_64BitTransfer(), XCsuDma_GetAddr(), and XCsuDma_Transfer().

◆ XCSUDMA_CRC_OFFSET

#define XCSUDMA_CRC_OFFSET   0x010

#include <xcsudma_hw.h>

CheckSum Register Offset.

Referenced by XCsuDma_ClearCheckSum(), and XCsuDma_GetCheckSum().

◆ XCSUDMA_CRC_RESET_MASK

#define XCSUDMA_CRC_RESET_MASK   0x00000000U

#include <xcsudma_hw.h>

Mask to reset value of check sum.

Referenced by XCsuDma_ClearCheckSum().

◆ XCSUDMA_CTRL2_ACACHE_MASK

#define XCSUDMA_CTRL2_ACACHE_MASK   0X07000000U

#include <xcsudma_hw.h>

AXI CACHE mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_ACACHE_SHIFT

#define XCSUDMA_CTRL2_ACACHE_SHIFT   24U

#include <xcsudma_hw.h>

Shift for AXI R/W CACHE.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_MAXCMDS_MASK

#define XCSUDMA_CTRL2_MAXCMDS_MASK   0x0000000FU

#include <xcsudma_hw.h>

Maximum commands mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_OFFSET

#define XCSUDMA_CTRL2_OFFSET   0x024

#include <xcsudma_hw.h>

Interrupt Control Register 2 Offset.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_RESERVED_MASK

#define XCSUDMA_CTRL2_RESERVED_MASK   0x083F0000U

#include <xcsudma_hw.h>

Reserved bits mask.

Referenced by XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_RESET_MASK

#define XCSUDMA_CTRL2_RESET_MASK   0x0000FFF8U

#include <xcsudma_hw.h>

Reset mask.

◆ XCSUDMA_CTRL2_ROUTE_MASK

#define XCSUDMA_CTRL2_ROUTE_MASK   0x00800000U

#include <xcsudma_hw.h>

Route mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_ROUTE_SHIFT

#define XCSUDMA_CTRL2_ROUTE_SHIFT   23U

#include <xcsudma_hw.h>

Shift for route.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_TIMEOUT_EN_MASK

#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK   0x00400000U

#include <xcsudma_hw.h>

Time out counters enable mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT

#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT   22U

#include <xcsudma_hw.h>

Shift for Timeout enable feild.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_TIMEOUT_PRE_MASK

#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK   0x0000FFF0U

#include <xcsudma_hw.h>

Time out pre mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT

#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT   4U

#include <xcsudma_hw.h>

Shift for Timeout pre feild.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_APB_ERR_MASK

#define XCSUDMA_CTRL_APB_ERR_MASK   0x01000000U

#include <xcsudma_hw.h>

APB register access error mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_APB_ERR_SHIFT

#define XCSUDMA_CTRL_APB_ERR_SHIFT   24U

#include <xcsudma_hw.h>

APB error shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_BURST_MASK

#define XCSUDMA_CTRL_BURST_MASK   0x00400000U

#include <xcsudma_hw.h>

AXI burst type mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_BURST_SHIFT

#define XCSUDMA_CTRL_BURST_SHIFT   22U

#include <xcsudma_hw.h>

AXI burst type shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_ENDIAN_MASK

#define XCSUDMA_CTRL_ENDIAN_MASK   0x00800000U

#include <xcsudma_hw.h>

Endianess mask.

Referenced by XCsuDma_GetConfig(), XCsuDma_SelfTest(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_ENDIAN_SHIFT

#define XCSUDMA_CTRL_ENDIAN_SHIFT   23U

#include <xcsudma_hw.h>

Endianess shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_FIFO_THRESH_MASK

#define XCSUDMA_CTRL_FIFO_THRESH_MASK   0x000003FCU

#include <xcsudma_hw.h>

FIFO threshold mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_FIFO_THRESH_SHIFT

#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT   2U

#include <xcsudma_hw.h>

FIFO thresh shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_OFFSET

#define XCSUDMA_CTRL_OFFSET   0x00C

◆ XCSUDMA_CTRL_PAUSE_MEM_MASK

#define XCSUDMA_CTRL_PAUSE_MEM_MASK   0x00000001U

#include <xcsudma_hw.h>

Memory pause mask.

Referenced by XCsuDma_IsPaused(), XCsuDma_Pause(), and XCsuDma_Resume().

◆ XCSUDMA_CTRL_PAUSE_STRM_MASK

#define XCSUDMA_CTRL_PAUSE_STRM_MASK   0x00000002U

#include <xcsudma_hw.h>

Stream pause mask.

Referenced by XCsuDma_IsPaused(), XCsuDma_Pause(), and XCsuDma_Resume().

◆ XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK

#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK   0xFE000000U

#include <xcsudma_hw.h>

SSS FIFO threshold value mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT

#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT   25U

#include <xcsudma_hw.h>

SSS FIFO threshold shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_TIMEOUT_MASK

#define XCSUDMA_CTRL_TIMEOUT_MASK   0x003FFC00U

#include <xcsudma_hw.h>

Time out value mask.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_CTRL_TIMEOUT_SHIFT

#define XCSUDMA_CTRL_TIMEOUT_SHIFT   10U

#include <xcsudma_hw.h>

Time out value shift.

Referenced by XCsuDma_GetConfig(), and XCsuDma_SetConfig().

◆ XCSUDMA_FUTURE_ECO_OFFSET

#define XCSUDMA_FUTURE_ECO_OFFSET   0xFFC

#include <xcsudma_hw.h>

Future potential ECO Offset.

◆ XCSUDMA_H_

#define XCSUDMA_H_

#include <xcsudma.h>

Prevent circular inclusions by using protection macros.

◆ XCSUDMA_HW_H_

#define XCSUDMA_HW_H_

#include <xcsudma_hw.h>

Prevent circular inclusions by using protection macros.

◆ XCSUDMA_I_DIS_OFFSET

#define XCSUDMA_I_DIS_OFFSET   0x01C

#include <xcsudma_hw.h>

Interrupt Disable Register Offset.

Referenced by XCsuDma_DisableIntr().

◆ XCSUDMA_I_EN_OFFSET

#define XCSUDMA_I_EN_OFFSET   0x018

#include <xcsudma_hw.h>

Interrupt Enable Register Offset.

Referenced by XCsuDma_EnableIntr().

◆ XCSUDMA_I_MASK_OFFSET

#define XCSUDMA_I_MASK_OFFSET   0x020

#include <xcsudma_hw.h>

Interrupt Mask Register Offset.

Referenced by XCsuDma_GetIntrMask().

◆ XCSUDMA_I_STS_OFFSET

#define XCSUDMA_I_STS_OFFSET   0x014

#include <xcsudma_hw.h>

Interrupt Status Register Offset.

Referenced by XCsuDma_IntrClear(), and XCsuDma_IntrGetStatus().

◆ XCsuDma_In32

#define XCsuDma_In32   Xil_In32

#include <xcsudma_hw.h>

Input operation.

◆ XCSUDMA_IXR_AXI_WRERR_MASK

#define XCSUDMA_IXR_AXI_WRERR_MASK   0x00000004U

#include <xcsudma_hw.h>

AXI Read/Write error mask.

◆ XCSUDMA_IXR_DONE_MASK

#define XCSUDMA_IXR_DONE_MASK   0x00000002U

#include <xcsudma_hw.h>

Done mask.

◆ XCSUDMA_IXR_DST_MASK

#define XCSUDMA_IXR_DST_MASK   0x000000FEU

#include <xcsudma_hw.h>

((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK))

All interrupt mask for destination

Referenced by XCsuDma_DisableIntr(), XCsuDma_EnableIntr(), and XCsuDma_IntrClear().

◆ XCSUDMA_IXR_FIFO_OVERFLOW_MASK

#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK   0x00000001U

#include <xcsudma_hw.h>

FIFO overflow mask, it is valid only to Destination Channel.

◆ XCSUDMA_IXR_FIFO_THRESHHIT_MASK

#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK   0x00000020U

#include <xcsudma_hw.h>

FIFO threshold hit indicator mask.

◆ XCSUDMA_IXR_INVALID_APB_MASK

#define XCSUDMA_IXR_INVALID_APB_MASK   0x00000040U

#include <xcsudma_hw.h>

Invalid APB access mask.

◆ XCSUDMA_IXR_MEM_DONE_MASK

#define XCSUDMA_IXR_MEM_DONE_MASK   0x00000001U

#include <xcsudma_hw.h>

Memory done mask, it is valid only for source channel.

◆ XCSUDMA_IXR_SRC_MASK

#define XCSUDMA_IXR_SRC_MASK   0x0000007FU

#include <xcsudma_hw.h>

((XCSUDMA_IXR_INVALID_APB_MASK)| (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK))

All interrupt mask for source

Referenced by XCsuDma_DisableIntr(), XCsuDma_EnableIntr(), and XCsuDma_IntrClear().

◆ XCSUDMA_IXR_TIMEOUT_MEM_MASK

#define XCSUDMA_IXR_TIMEOUT_MEM_MASK   0x00000010U

#include <xcsudma_hw.h>

Time out counter expired to access memory mask.

◆ XCSUDMA_IXR_TIMEOUT_STRM_MASK

#define XCSUDMA_IXR_TIMEOUT_STRM_MASK   0x00000008U

#include <xcsudma_hw.h>

Time out counter expired to access stream mask.

◆ XCSUDMA_LAST_WORD_MASK

#define XCSUDMA_LAST_WORD_MASK   0x00000001U

#include <xcsudma_hw.h>

Last word check bit mask.

Referenced by XCsuDma_64BitTransfer(), and XCsuDma_Transfer().

◆ XCSUDMA_MSB_ADDR_MASK

#define XCSUDMA_MSB_ADDR_MASK   0x0001FFFFU

#include <xcsudma_hw.h>

MSB bits of address mask.

Referenced by XCsuDma_64BitTransfer(), and XCsuDma_Transfer().

◆ XCSUDMA_MSB_ADDR_SHIFT

#define XCSUDMA_MSB_ADDR_SHIFT   32U

#include <xcsudma_hw.h>

Shift for MSB bits of address.

Referenced by XCsuDma_GetAddr(), and XCsuDma_Transfer().

◆ XCSUDMA_OFFSET_DIFF

◆ XCsuDma_Out32

#define XCsuDma_Out32   Xil_Out32

#include <xcsudma_hw.h>

Output operation.

◆ XCsuDma_ReadReg

#define XCsuDma_ReadReg (   BaseAddress,
  RegOffset 
)    XCsuDma_In32((BaseAddress) + (u32)(RegOffset))

#include <xcsudma_hw.h>

This macro reads the given register.

Parameters
BaseAddressis the Xilinx base address of the CSU_DMA core.
RegOffsetis the register offset of the register.
Returns
The 32-bit value of the register.
Note
C-style signature: u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XCsuDma_GetAddr(), XCsuDma_GetCheckSum(), XCsuDma_GetConfig(), XCsuDma_GetIntrMask(), XCsuDma_GetSize(), XCsuDma_IntrGetStatus(), XCsuDma_IsPaused(), XCsuDma_Pause(), XCsuDma_Resume(), XCsuDma_SelfTest(), and XCsuDma_SetConfig().

◆ XCSUDMA_RESET_SET_MASK

#define XCSUDMA_RESET_SET_MASK   0x00000001U

#include <xcsudma_hw.h>

Reset set mask.

◆ XCSUDMA_RESET_UNSET_MASK

#define XCSUDMA_RESET_UNSET_MASK   0x00000000U

#include <xcsudma_hw.h>

Reset unset mask.

◆ XCSUDMA_SAFETY_CHK_OFFSET

#define XCSUDMA_SAFETY_CHK_OFFSET   0xFF8

#include <xcsudma_hw.h>

Safety Check Field Offset.

◆ XCSUDMA_SIZE_MASK

#define XCSUDMA_SIZE_MASK   0x1FFFFFFCU

#include <xcsudma_hw.h>

Mask for size.

◆ XCSUDMA_SIZE_OFFSET

#define XCSUDMA_SIZE_OFFSET   0x004

#include <xcsudma_hw.h>

Size Register Offset.

Referenced by XCsuDma_64BitTransfer(), XCsuDma_GetSize(), and XCsuDma_Transfer().

◆ XCSUDMA_SIZE_SHIFT

#define XCSUDMA_SIZE_SHIFT   2U

#include <xcsudma_hw.h>

Shift for size.

Referenced by XCsuDma_64BitTransfer(), XCsuDma_GetSize(), and XCsuDma_Transfer().

◆ XCSUDMA_STS_BUSY_MASK

#define XCSUDMA_STS_BUSY_MASK   0x00000001U

#include <xcsudma_hw.h>

Busy mask.

◆ XCSUDMA_STS_DONE_CNT_MASK

#define XCSUDMA_STS_DONE_CNT_MASK   0x0000E000U

#include <xcsudma_hw.h>

Count done mask.

◆ XCSUDMA_STS_DONE_CNT_SHIFT

#define XCSUDMA_STS_DONE_CNT_SHIFT   13U

#include <xcsudma_hw.h>

Shift for Count done.

◆ XCSUDMA_STS_FIFO_LEVEL_MASK

#define XCSUDMA_STS_FIFO_LEVEL_MASK   0x00001FE0U

#include <xcsudma_hw.h>

FIFO level mask.

◆ XCSUDMA_STS_FIFO_LEVEL_SHIFT

#define XCSUDMA_STS_FIFO_LEVEL_SHIFT   5U

#include <xcsudma_hw.h>

Shift for FIFO level.

◆ XCSUDMA_STS_OFFSET

#define XCSUDMA_STS_OFFSET   0x008

#include <xcsudma_hw.h>

Status Register Offset.

◆ XCsuDma_WriteReg

#define XCsuDma_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))

#include <xcsudma_hw.h>

This macro writes the value into the given register.

Parameters
BaseAddressis the Xilinx base address of the CSU_DMA core.
RegOffsetis the register offset of the register.
Datais the 32-bit value to write to the register.
Returns
None.
Note
C-style signature: void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XCsuDma_64BitTransfer(), XCsuDma_ClearCheckSum(), XCsuDma_DisableIntr(), XCsuDma_EnableIntr(), XCsuDma_IntrClear(), XCsuDma_Pause(), XCsuDma_Resume(), XCsuDma_SelfTest(), XCsuDma_SetConfig(), and XCsuDma_Transfer().

◆ XCUSDMA_STS_OUTSTDG_MASK

#define XCUSDMA_STS_OUTSTDG_MASK   0x0000001EU

#include <xcsudma_hw.h>

No.of outstanding read/write commands mask.

◆ XCUSDMA_STS_OUTSTDG_SHIFT

#define XCUSDMA_STS_OUTSTDG_SHIFT   1U

#include <xcsudma_hw.h>

Shift for No.of outstanding read/write commands.

Enumeration Type Documentation

◆ XCsuDma_Channel

#include <xcsudma.h>

This typedef contains CSU_DMA Channel Types.

Enumerator
XCSUDMA_SRC_CHANNEL 

Source Channel of CSU_DMA.

XCSUDMA_DST_CHANNEL 

Destination Channel of CSU_DMA.

Function Documentation

◆ XCsuDma_64BitTransfer()

void XCsuDma_64BitTransfer ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
u32  AddrLow,
u32  AddrHigh,
u32  Size,
u8  EnDataLast 
)

#include <xcsudma.c>

This function sets the starting address and amount(size) of the data to be transfered from/to the memory through the AXI interface.

This function is useful for pmu processor when it wishes to do a 64-bit DMA transfer.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
AddrLowis a 32 bit variable which holds the starting lower address of data which needs to write into the memory(DST) (or read from the memory(SRC)).
AddrHighis a 32 bit variable which holds the higher address of data which needs to write into the memory(DST) (or read from the memroy(SRC)).
Sizeis a 32 bit variable which represents the number of 4 byte words needs to be transfered from starting address.
EnDataLastis to trigger an end of message. It will enable or disable data_inp_last signal to stream interface when current command is completed. It is applicable only to source channel and neglected for destination channel.
  • 1 - Asserts data_inp_last signal.
  • 0 - data_inp_last will not be asserted.
Returns
None.
Note
Data_inp_last signal is asserted simultaneously with the data_inp_valid signal associated with the final 32-bit word transfer This API won't do flush/invalidation for the DMA buffer. It is recommened to call this API only through PMU processor.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, XCSUDMA_ADDR_MASK, XCSUDMA_ADDR_MSB_OFFSET, XCSUDMA_ADDR_OFFSET, XCSUDMA_DST_CHANNEL, XCSUDMA_LAST_WORD_MASK, XCSUDMA_MSB_ADDR_MASK, XCSUDMA_OFFSET_DIFF, XCSUDMA_SIZE_MAX, XCSUDMA_SIZE_OFFSET, XCSUDMA_SIZE_SHIFT, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_CfgInitialize()

s32 XCsuDma_CfgInitialize ( XCsuDma InstancePtr,
XCsuDma_Config CfgPtr,
u32  EffectiveAddr 
)

#include <xcsudma.c>

This function initializes an CSU_DMA core.

This function must be called prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting up the instance data and ensuring the hardware is in a quiescent state.

Parameters
InstancePtris a pointer to the XCsuDma instance.
CfgPtris a reference to a structure containing information about a specific XCsuDma instance.
EffectiveAddris the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, pass in the physical address instead.
Returns
  • XST_SUCCESS if initialization was successful.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, and XCsuDma_Reset.

Referenced by XCsuDma_SelfTestExample().

◆ XCsuDma_ClearCheckSum()

void XCsuDma_ClearCheckSum ( XCsuDma InstancePtr)

#include <xcsudma.c>

This function clears the check sum of the data read from AXI memory.

It is valid only for CSU_DMA source channel.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Returns
Returns the sum of all the data read from memory.
Note
Before start of the transfer need to clear this register to get correct sum otherwise it adds to previous value which results to wrong output.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_CRC_OFFSET, XCSUDMA_CRC_RESET_MASK, and XCsuDma_WriteReg.

◆ XCsuDma_DisableIntr()

void XCsuDma_DisableIntr ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
u32  Mask 
)

#include <xcsudma_intr.c>

This function disables the interrupt(s).

Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to create the bit-mask to disable interrupts.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Maskcontains interrupts to be disabled.
  • Bit positions of 1 will be disabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in xcsudma_hw.h.
Returns
None.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_I_DIS_OFFSET, XCSUDMA_IXR_DST_MASK, XCSUDMA_IXR_SRC_MASK, XCSUDMA_OFFSET_DIFF, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_EnableIntr()

void XCsuDma_EnableIntr ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
u32  Mask 
)

#include <xcsudma_intr.c>

This function enables the interrupt(s).

Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to create the bit-mask to enable interrupts.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Maskcontains interrupts to be enabled.
  • Bit positions of 1 will be enabled. This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined in xcsudma_hw.h.
Returns
None.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_I_EN_OFFSET, XCSUDMA_IXR_DST_MASK, XCSUDMA_IXR_SRC_MASK, XCSUDMA_OFFSET_DIFF, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_GetAddr()

u64 XCsuDma_GetAddr ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel 
)

#include <xcsudma.c>

This function returns the current address location of the memory, from where it has to read the data(SRC) or the location where it has to write the data (DST) based on the channel selection.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Returns
Address is a 64 bit variable which holds the current address.
  • From this location data has to be read(SRC)
  • At this location data has to be written(DST)
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_ADDR_MSB_OFFSET, XCSUDMA_ADDR_OFFSET, XCSUDMA_DST_CHANNEL, XCSUDMA_MSB_ADDR_SHIFT, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_GetCheckSum()

u32 XCsuDma_GetCheckSum ( XCsuDma InstancePtr)

#include <xcsudma.c>

This function returns the sum of all the data read from AXI memory.

It is valid only one we use CSU_DMA source channel.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Returns
Returns the sum of all the data read from memory.
Note
Before start of the transfer need to clear this register to get correct sum otherwise it adds to previous value which results to wrong output. Valid only for source channel

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, XCSUDMA_CRC_OFFSET, and XCsuDma_ReadReg.

◆ XCsuDma_GetConfig()

void XCsuDma_GetConfig ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
XCsuDma_Configure ConfigurValues 
)

#include <xcsudma.c>

This function updates XCsuDma_Configure structure members with the cofigured values of CSU_DMA's Channel.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
ConfigurValuesis a pointer to the structure XCsuDma_Configure whose members are updated with configurations of CSU_DMA core.
  • SssFifoThesh When the DST FIFO level >= this value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.
    • Range is (0x10 to 0x7A) threshold is 17 to 123 entries.
    • It is valid only for DST CSU_DMA IP.
  • ApbErr When accessed to invalid APB the resulting pslerr will be
    • 0 - 1'b0
    • 1 - 1'b1
  • EndianType Type of endianness
    • 0 doesn't change order
    • 1 will flip the order.
  • AxiBurstType....Type of the burst
    • 0 will issue INCR type burst
    • 1 will issue FIXED type burst
  • TimeoutValue Time out value for timers
    • 0x000 to 0xFFE are valid inputs
    • 0xFFF clears both timers
  • FifoThresh......Programmed watermark value
    • Range is 0x00 to 0x80 (0 to 128 entries).
  • Acache Sets the AXI CACHE bits on the AXI Write/Read channel.
    • Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:
    • 0x000 - Cacheable, but do not allocate
    • 0x001 - Cacheable and bufferable, but do not allocate
    • 0x010 - Cacheable write-through, allocate on reads only
    • 0x011 - Cacheable write-back, allocate on reads only
    • 0x100 - Cacheable write-through, allocate on writes only
    • 0x101 - Cacheable write-back, allocate on writes only
    • 0x110 - Cacheable write-through, allocate on both reads and writes
    • 0x111 - Cacheable write-back, allocate on both reads and writes
  • RouteBit To select route
    • 0 : Command will be routed based normally
    • 1 : Command will be routed to APU's cache controller
  • TimeoutEn To enable or disable time out counters
    • 0 : The 2 Timeout counters are disabled
    • 1 : The 2 Timeout counters are enabled
  • TimeoutPre Set the prescaler value for the timeout in clk (~2.5ns) cycles
    • Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)
  • MaxOutCmds Controls the maximumum number of outstanding AXI read commands issued.
    • Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)
Returns
None.
Note
None.

References XCsuDma_Configure::Acache, XCsuDma_Configure::ApbErr, XCsuDma_Configure::AxiBurstType, XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma_Configure::EndianType, XCsuDma_Configure::FifoThresh, XCsuDma_Configure::MaxOutCmds, XCsuDma_Configure::RouteBit, XCsuDma_Configure::SssFifoThesh, XCsuDma_Configure::TimeoutEn, XCsuDma_Configure::TimeoutPre, XCsuDma_Configure::TimeoutValue, XCSUDMA_CTRL2_ACACHE_MASK, XCSUDMA_CTRL2_ACACHE_SHIFT, XCSUDMA_CTRL2_MAXCMDS_MASK, XCSUDMA_CTRL2_OFFSET, XCSUDMA_CTRL2_ROUTE_MASK, XCSUDMA_CTRL2_ROUTE_SHIFT, XCSUDMA_CTRL2_TIMEOUT_EN_MASK, XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT, XCSUDMA_CTRL2_TIMEOUT_PRE_MASK, XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT, XCSUDMA_CTRL_APB_ERR_MASK, XCSUDMA_CTRL_APB_ERR_SHIFT, XCSUDMA_CTRL_BURST_MASK, XCSUDMA_CTRL_BURST_SHIFT, XCSUDMA_CTRL_ENDIAN_MASK, XCSUDMA_CTRL_ENDIAN_SHIFT, XCSUDMA_CTRL_FIFO_THRESH_MASK, XCSUDMA_CTRL_FIFO_THRESH_SHIFT, XCSUDMA_CTRL_OFFSET, XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK, XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT, XCSUDMA_CTRL_TIMEOUT_MASK, XCSUDMA_CTRL_TIMEOUT_SHIFT, XCSUDMA_DST_CHANNEL, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_GetIntrMask()

u32 XCsuDma_GetIntrMask ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel 
)

#include <xcsudma_intr.c>

This function returns the interrupt mask to know which interrupts are enabled and which of them were disaled.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Returns
The current interrupt mask. The mask indicates which interrupts are enabled/disabled. 0 bit represents .....corresponding interrupt is enabled. 1 bit represents .....Corresponding interrupt is disabled. To interpret returned mask use XCSUDMA_IXR_SRC_MASK........For source channel XCSUDMA_IXR_DST_MASK........For destination channel
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_I_MASK_OFFSET, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_GetSize()

u32 XCsuDma_GetSize ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel 
)

#include <xcsudma.c>

This function returns the size of the data yet to be transfered from memory to CSU_DMA or CSU_DMA to memory based on the channel selection.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Returns
Size is amount of data yet to be transfered.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, XCSUDMA_SIZE_OFFSET, XCSUDMA_SIZE_SHIFT, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_IntrClear()

void XCsuDma_IntrClear ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
u32  Mask 
)

#include <xcsudma_intr.c>

This function clears interrupt(s).

Every bit set in Interrupt Status Register indicates that a specific type of interrupt is occurring, and this function clears one or more interrupts by writing a bit mask to Interrupt Clear Register.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Maskis the mask to clear. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XCSUDMA_IXR_* bits defined in xcsudma_hw.h.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_I_STS_OFFSET, XCSUDMA_IXR_DST_MASK, XCSUDMA_IXR_SRC_MASK, XCSUDMA_OFFSET_DIFF, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_IntrGetStatus()

u32 XCsuDma_IntrGetStatus ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel 
)

#include <xcsudma_intr.c>

This function returns interrupt status read from Interrupt Status Register.

Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the returned value.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Returns
The pending interrupts of the CSU_DMA. Use th following masks to interpret the returned value. XCSUDMA_IXR_SRC_MASK - For Source channel XCSUDMA_IXR_DST_MASK - For Destination channel
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_DST_CHANNEL, XCSUDMA_I_STS_OFFSET, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_IsPaused()

s32 XCsuDma_IsPaused ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
XCsuDma_PauseType  Type 
)

#include <xcsudma.c>

This functions checks whether Channel's memory or stream is paused or not based on the given pause type.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Typeis type of the pause which needs to be checked.
  • XCSUDMA_PAUSE_MEMORY(0) - Pause memory
    • SRC Stops issuing of new read commands to memory.
    • DST Stops issuing of new write commands to memory.
  • XCSUDMA_PAUSE_STREAM(1) - Pause stream
    • SRC Stops transfer of data from FIFO to Stream.
    • DST Stops transfer of data from stream to FIFO.
Returns
Returns the pause status.
  • TRUE if it is in paused state.
  • FALSE if it is not in pause state.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_CTRL_OFFSET, XCSUDMA_CTRL_PAUSE_MEM_MASK, XCSUDMA_CTRL_PAUSE_STRM_MASK, XCSUDMA_DST_CHANNEL, XCSUDMA_OFFSET_DIFF, XCSUDMA_PAUSE_MEMORY, XCSUDMA_PAUSE_STREAM, XCsuDma_ReadReg, and XCSUDMA_SRC_CHANNEL.

◆ XCsuDma_LookupConfig()

XCsuDma_Config* XCsuDma_LookupConfig ( u16  DeviceId)

#include <xcsudma_sinit.c>

XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure based on the unique device id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xcsudma_g.c file.

Parameters
DeviceIdis the unique device ID of the device for the lookup operation.
Returns
CfgPtr is a reference to a config record in the configuration table (in xcsudma_g.c) corresponding to DeviceId, or NULL if no match is found.
Note
None.

Referenced by XCsuDma_SelfTestExample().

◆ XCsuDma_Pause()

void XCsuDma_Pause ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
XCsuDma_PauseType  Type 
)

#include <xcsudma.c>

This function pause the Channel data tranfer to/from memory or to/from stream based on pause type.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Typeis type of the pause to be enabled.
  • XCSUDMA_PAUSE_MEMORY(0) - Pause memory
    • SRC Stops issuing of new read commands to memory.
    • DST Stops issuing of new write commands to memory.
  • XCSUDMA_PAUSE_STREAM(1) - Pause stream
    • SRC Stops transfer of data from FIFO to Stream.
    • DST Stops transfer of data from stream to FIFO.
Returns
None.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, XCSUDMA_CTRL_OFFSET, XCSUDMA_CTRL_PAUSE_MEM_MASK, XCSUDMA_CTRL_PAUSE_STRM_MASK, XCSUDMA_DST_CHANNEL, XCSUDMA_OFFSET_DIFF, XCSUDMA_PAUSE_MEMORY, XCSUDMA_PAUSE_STREAM, XCsuDma_ReadReg, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_Resume()

void XCsuDma_Resume ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
XCsuDma_PauseType  Type 
)

#include <xcsudma.c>

This function resumes the channel if it is in paused state and continues where it has left or no effect if it is not in paused state, based on the type of pause.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Typeis type of the pause to be Resume if it is in pause state.
  • XCSUDMA_PAUSE_MEMORY(0) - Pause memory
    • SRC Stops issuing of new read commands to memory.
    • DST Stops issuing of new write commands to memory.
  • XCSUDMA_PAUSE_STREAM(1) - Pause stream
    • SRC Stops transfer of data from FIFO to Stream.
    • DST Stops transfer of data from stream to FIFO.
Returns
None.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, XCSUDMA_CTRL_OFFSET, XCSUDMA_CTRL_PAUSE_MEM_MASK, XCSUDMA_CTRL_PAUSE_STRM_MASK, XCSUDMA_DST_CHANNEL, XCSUDMA_OFFSET_DIFF, XCSUDMA_PAUSE_MEMORY, XCSUDMA_PAUSE_STREAM, XCsuDma_ReadReg, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_SelfTest()

s32 XCsuDma_SelfTest ( XCsuDma InstancePtr)

#include <xcsudma_selftest.c>

This function runs a self-test on the driver and hardware device.

Performs reset of both source and destination channels and checks if reset is working properly or not.

Parameters
InstancePtris a pointer to the XCsuDma instance.
Returns
  • XST_SUCCESS if the self-test passed.
    • XST_FAILURE otherwise.
Note
None.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCSUDMA_CTRL_ENDIAN_MASK, XCSUDMA_CTRL_OFFSET, XCsuDma_ReadReg, and XCsuDma_WriteReg.

Referenced by XCsuDma_SelfTestExample().

◆ XCsuDma_SetConfig()

void XCsuDma_SetConfig ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
XCsuDma_Configure ConfigurValues 
)

#include <xcsudma.c>

This function cofigures all the values of CSU_DMA's Channels with the values of updated XCsuDma_Configure structure.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
ConfigurValuesis a pointer to the structure XCsuDma_Configure whose values are used to configure CSU_DMA core.
  • SssFifoThesh When the DST FIFO level >= this value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA.
    • Range is (0x10 to 0x7A) threshold is 17 to 123 entries.
    • It is valid only for DST CSU_DMA IP.
  • ApbErr When accessed to invalid APB the resulting pslerr will be
    • 0 - 1'b0
    • 1 - 1'b1
  • EndianType Type of endianness
    • 0 doesn't change order
    • 1 will flip the order.
  • AxiBurstType....Type of the burst
    • 0 will issue INCR type burst
    • 1 will issue FIXED type burst
  • TimeoutValue Time out value for timers
    • 0x000 to 0xFFE are valid inputs
    • 0xFFF clears both timers
  • FifoThresh......Programmed watermark value
    • Range is 0x00 to 0x80 (0 to 128 entries).
  • Acache Sets the AXI CACHE bits on the AXI Write/Read channel.
    • Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] for DST channel are always 1, we need to configure remaining 3 signal support (Bufferable, Read allocate and Write allocate). Valid inputs are:
    • 0x000 - Cacheable, but do not allocate
    • 0x001 - Cacheable and bufferable, but do not allocate
    • 0x010 - Cacheable write-through, allocate on reads only
    • 0x011 - Cacheable write-back, allocate on reads only
    • 0x100 - Cacheable write-through, allocate on writes only
    • 0x101 - Cacheable write-back, allocate on writes only
    • 0x110 - Cacheable write-through, allocate on both reads and writes
    • 0x111 - Cacheable write-back, allocate on both reads and writes
  • RouteBit To select route
    • 0 : Command will be routed normally
    • 1 : Command will be routed to APU's cache controller
  • TimeoutEn To enable or disable time out counters
    • 0 : The 2 Timeout counters are disabled
    • 1 : The 2 Timeout counters are enabled
  • TimeoutPre Set the prescaler value for the timeout in clk (~2.5ns) cycles
    • Range is 0x000(Prescaler enables timer every cycles) to 0xFFF(Prescaler enables timer every 4096 cycles)
  • MaxOutCmds Controls the maximumum number of outstanding AXI read commands issued.
    • Range is 0x0(Up to 1 Outstanding Read command allowed) to 0x8 (Up to 9 Outstanding Read command allowed)
Returns
None.
Note
To use timers timeout value Timeout enable field should be enabled.

References XCsuDma_Configure::Acache, XCsuDma_Configure::ApbErr, XCsuDma_Configure::AxiBurstType, XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma_Configure::EndianType, XCsuDma_Configure::FifoThresh, XCsuDma::IsReady, XCsuDma_Configure::MaxOutCmds, XCsuDma_Configure::RouteBit, XCsuDma_Configure::SssFifoThesh, XCsuDma_Configure::TimeoutEn, XCsuDma_Configure::TimeoutPre, XCsuDma_Configure::TimeoutValue, XCSUDMA_CTRL2_ACACHE_MASK, XCSUDMA_CTRL2_ACACHE_SHIFT, XCSUDMA_CTRL2_MAXCMDS_MASK, XCSUDMA_CTRL2_OFFSET, XCSUDMA_CTRL2_RESERVED_MASK, XCSUDMA_CTRL2_ROUTE_MASK, XCSUDMA_CTRL2_ROUTE_SHIFT, XCSUDMA_CTRL2_TIMEOUT_EN_MASK, XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT, XCSUDMA_CTRL2_TIMEOUT_PRE_MASK, XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT, XCSUDMA_CTRL_APB_ERR_MASK, XCSUDMA_CTRL_APB_ERR_SHIFT, XCSUDMA_CTRL_BURST_MASK, XCSUDMA_CTRL_BURST_SHIFT, XCSUDMA_CTRL_ENDIAN_MASK, XCSUDMA_CTRL_ENDIAN_SHIFT, XCSUDMA_CTRL_FIFO_THRESH_MASK, XCSUDMA_CTRL_FIFO_THRESH_SHIFT, XCSUDMA_CTRL_OFFSET, XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK, XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT, XCSUDMA_CTRL_TIMEOUT_MASK, XCSUDMA_CTRL_TIMEOUT_SHIFT, XCSUDMA_DST_CHANNEL, XCsuDma_IsBusy, XCSUDMA_OFFSET_DIFF, XCsuDma_ReadReg, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.

◆ XCsuDma_Transfer()

void XCsuDma_Transfer ( XCsuDma InstancePtr,
XCsuDma_Channel  Channel,
UINTPTR  Addr,
u32  Size,
u8  EnDataLast 
)

#include <xcsudma.c>

This function sets the starting address and amount(size) of the data to be transfered from/to the memory through the AXI interface.

Parameters
InstancePtris a pointer to XCsuDma instance to be worked on.
Channelrepresents the type of channel either it is Source or Destination. Source channel - XCSUDMA_SRC_CHANNEL Destination Channel - XCSUDMA_DST_CHANNEL
Addris a 64 bit variable which holds the starting address of data which needs to write into the memory(DST) (or read from the memory(SRC)).
Sizeis a 32 bit variable which represents the number of 4 byte words needs to be transfered from starting address.
EnDataLastis to trigger an end of message. It will enable or disable data_inp_last signal to stream interface when current command is completed. It is applicable only to source channel and neglected for destination channel.
  • 1 - Asserts data_inp_last signal.
  • 0 - data_inp_last will not be asserted.
Returns
None.
Note
Data_inp_last signal is asserted simultaneously with the data_inp_valid signal associated with the final 32-bit word transfer.

References XCsuDma_Config::BaseAddress, XCsuDma::Config, XCsuDma::IsReady, XCSUDMA_ADDR_LSB_MASK, XCSUDMA_ADDR_MASK, XCSUDMA_ADDR_MSB_OFFSET, XCSUDMA_ADDR_OFFSET, XCSUDMA_DST_CHANNEL, XCSUDMA_LAST_WORD_MASK, XCSUDMA_MSB_ADDR_MASK, XCSUDMA_MSB_ADDR_SHIFT, XCSUDMA_OFFSET_DIFF, XCSUDMA_SIZE_MAX, XCSUDMA_SIZE_OFFSET, XCSUDMA_SIZE_SHIFT, XCSUDMA_SRC_CHANNEL, and XCsuDma_WriteReg.