qspipsu
Xilinx SDK Drivers API Documentation
Qspipsu_v1_8

Data Structures

struct  XQspiPsu_Msg
 This typedef contains configuration information for a flash message. More...
 
struct  XQspiPsu_Config
 This typedef contains configuration information for the device. More...
 
struct  XQspiPsu
 The XQspiPsu driver instance data. More...
 

Macros

#define BYTES256_PER_PAGE   256U
 Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry. More...
 
#define BYTES512_PER_PAGE   512U
 512 Bytes per Page More...
 
#define BYTES1024_PER_PAGE   1024U
 1024 Bytes per Page More...
 
#define PAGES16_PER_SECTOR   16U
 16 Pages per Sector More...
 
#define PAGES128_PER_SECTOR   128U
 128 Pages per Sector More...
 
#define PAGES256_PER_SECTOR   256U
 256 Pages per Sector More...
 
#define PAGES512_PER_SECTOR   512U
 512 Pages per Sector More...
 
#define PAGES1024_PER_SECTOR   1024U
 1024 Pages per Sector More...
 
#define NUM_OF_SECTORS2   2U
 2 Sectors More...
 
#define NUM_OF_SECTORS4   4U
 4 Sectors More...
 
#define NUM_OF_SECTORS8   8U
 8 Sector More...
 
#define NUM_OF_SECTORS16   16U
 16 Sectors More...
 
#define NUM_OF_SECTORS32   32U
 32 Sectors More...
 
#define NUM_OF_SECTORS64   64U
 64 Sectors More...
 
#define NUM_OF_SECTORS128   128U
 128 Sectors More...
 
#define NUM_OF_SECTORS256   256U
 256 Sectors More...
 
#define NUM_OF_SECTORS512   512U
 512 Sectors More...
 
#define NUM_OF_SECTORS1024   1024U
 1024 Sectors More...
 
#define NUM_OF_SECTORS2048   2048U
 2048 Sectors More...
 
#define NUM_OF_SECTORS4096   4096U
 4096 Sectors More...
 
#define NUM_OF_SECTORS8192   8192U
 8192 Sectors More...
 
#define SECTOR_SIZE_64K   0X10000U
 64K Sector More...
 
#define SECTOR_SIZE_128K   0X20000U
 128K Sector More...
 
#define SECTOR_SIZE_256K   0X40000U
 256K Sector More...
 
#define SECTOR_SIZE_512K   0X80000U
 512K Sector More...
 
#define XQSPIPS_BASEADDR   0XFF0F0000U
 QSPI Base Address. More...
 
#define XQSPIPSU_BASEADDR   0xFF0F0100U
 GQSPI Base Address. More...
 
#define XQSPIPS_EN_REG   ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
 Register: XQSPIPS_EN_REG. More...
 
#define XQSPIPSU_CFG_OFFSET   0X00000000U
 Register: XQSPIPSU_CFG. More...
 
#define XQSPIPSU_LQSPI_CR_OFFSET   0X000000A0U
 Register: XQSPIPSU_CFG. More...
 
#define XQSPIPSU_LQSPI_CR_OFFSET   0X000000A0U
 Register: XQSPIPSU_CFG. More...
 
#define XQSPIPSU_LQSPI_CR_LINEAR_MASK   0x80000000
 LQSPI mode enable. More...
 
#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK   0x40000000
 Both memories or one. More...
 
#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK   0x20000000
 Seperate memory bus. More...
 
#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK   0x10000000
 Upper memory page. More...
 
#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK   0x01000000
 Upper memory page. More...
 
#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK   0x02000000
 Enable mode bits. More...
 
#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK   0x01000000
 Mode on. More...
 
#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK   0x00FF0000
 Mode value for dual I/O or quad I/O. More...
 
#define XQSPIPS_LQSPI_CR_INST_MASK   0x000000FF
 Read instr code. More...
 
#define XQSPIPS_LQSPI_CR_RST_STATE   0x80000003
 Default LQSPI CR value. More...
 
#define XQSPIPS_LQSPI_CR_4_BYTE_STATE   0x88000013
 Default 4 Byte LQSPI CR value. More...
 
#define XQSPIPS_LQSPI_CFG_RST_STATE   0x800238C1
 Default LQSPI CFG value. More...
 
#define XQSPIPSU_ISR_OFFSET   0X00000004U
 Register: XQSPIPSU_ISR. More...
 
#define XQSPIPSU_IER_OFFSET   0X00000008U
 Register: XQSPIPSU_IER. More...
 
#define XQSPIPSU_IDR_OFFSET   0X0000000CU
 Register: XQSPIPSU_IDR. More...
 
#define XQSPIPSU_IMR_OFFSET   0X00000010U
 Register: XQSPIPSU_IMR. More...
 
#define XQSPIPSU_EN_OFFSET   0X00000014U
 Register: XQSPIPSU_EN_REG. More...
 
#define XQSPIPSU_TXD_OFFSET   0X0000001CU
 Register: XQSPIPSU_TXD. More...
 
#define XQSPIPSU_RXD_OFFSET   0X00000020U
 Register: XQSPIPSU_RXD. More...
 
#define XQSPIPSU_TX_THRESHOLD_OFFSET   0X00000028U
 Register: XQSPIPSU_TX_THRESHOLD. More...
 
#define XQSPIPSU_RX_THRESHOLD_OFFSET   0X0000002CU
 Register: XQSPIPSU_RX_THRESHOLD. More...
 
#define XQSPIPSU_GPIO_OFFSET   0X00000030U
 Register: XQSPIPSU_GPIO. More...
 
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET   0X00000038U
 Register: XQSPIPSU_LPBK_DLY_ADJ. More...
 
#define XQSPIPSU_GEN_FIFO_OFFSET   0X00000040U
 Register: XQSPIPSU_GEN_FIFO. More...
 
#define XQSPIPSU_SEL_OFFSET   0X00000044U
 Register: XQSPIPSU_SEL. More...
 
#define XQSPIPSU_FIFO_CTRL_OFFSET   0X0000004CU
 Register: XQSPIPSU_FIFO_CTRL. More...
 
#define XQSPIPSU_GF_THRESHOLD_OFFSET   0X00000050U
 Register: XQSPIPSU_GF_THRESHOLD. More...
 
#define XQSPIPSU_POLL_CFG_OFFSET   0X00000054U
 Register: XQSPIPSU_POLL_CFG. More...
 
#define XQSPIPSU_P_TO_OFFSET   0X00000058U
 Register: XQSPIPSU_P_TIMEOUT. More...
 
#define XQSPIPSU_XFER_STS_OFFSET   0X0000005CU
 Register: XQSPIPSU_XFER_STS. More...
 
#define XQSPIPSU_GF_SNAPSHOT_OFFSET   0X00000060U
 Register: XQSPIPSU_GF_SNAPSHOT. More...
 
#define XQSPIPSU_RX_COPY_OFFSET   0X00000064U
 Register: XQSPIPSU_RX_COPY. More...
 
#define XQSPIPSU_MOD_ID_OFFSET   0X000000FCU
 Register: XQSPIPSU_MOD_ID. More...
 
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET   0X00000700U
 Register: XQSPIPSU_QSPIDMA_DST_ADDR. More...
 
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET   0X00000704U
 Register: XQSPIPSU_QSPIDMA_DST_SIZE. More...
 
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET   0X00000708U
 Register: XQSPIPSU_QSPIDMA_DST_STS. More...
 
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET   0X0000070CU
 Register: XQSPIPSU_QSPIDMA_DST_CTRL. More...
 
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET   0X00000714U
 Register: XQSPIPSU_QSPIDMA_DST_I_STS. More...
 
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET   0X00000718U
 Register: XQSPIPSU_QSPIDMA_DST_I_EN. More...
 
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET   0X0000071CU
 Register: XQSPIPSU_QSPIDMA_DST_I_DIS. More...
 
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET   0X00000720U
 Register: XQSPIPSU_QSPIDMA_DST_IMR. More...
 
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET   0X00000724U
 Register: XQSPIPSU_QSPIDMA_DST_CTRL2. More...
 
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET   0X00000728U
 Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB. More...
 
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET   0X00000EFCU
 Register: XQSPIPSU_QSPIDMA_FUTURE_ECO. More...
 
#define XQspiPsu_ReadReg(BaseAddress, RegOffset)   XQspiPsu_In32((BaseAddress) + (RegOffset))
 Read a register. More...
 
#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue)   XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 Write to a register. More...
 

Typedefs

typedef void(* XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 ByteCount)
 The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. More...
 

Functions

s32 XQspiPsu_CfgInitialize (XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, u32 EffectiveAddr)
 Initializes a specific XQspiPsu instance as such the driver is ready to use. More...
 
void XQspiPsu_Reset (XQspiPsu *InstancePtr)
 Resets the QSPIPSU device. More...
 
void XQspiPsu_Abort (XQspiPsu *InstancePtr)
 Aborts a transfer in progress by. More...
 
s32 XQspiPsu_PolledTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 NumMsg)
 This function performs a transfer on the bus in polled mode. More...
 
s32 XQspiPsu_InterruptTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 NumMsg)
 This function initiates a transfer on the bus and enables interrupts. More...
 
s32 XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)
 Handles interrupt based transfers by acting on GENFIFO and DMA interurpts. More...
 
void XQspiPsu_SetStatusHandler (XQspiPsu *InstancePtr, void *CallBackRef, XQspiPsu_StatusHandler FuncPointer)
 Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More...
 
void XQspiPsu_WriteProtectToggle (XQspiPsu *QspiPsuPtr, u32 Toggle)
 This API enables/ disables Write Protect pin on the flash parts. More...
 
XQspiPsu_ConfigXQspiPsu_LookupConfig (u16 DeviceId)
 Looks up the device configuration based on the unique device ID. More...
 
s32 XQspiPsu_SetClkPrescaler (XQspiPsu *InstancePtr, u8 Prescaler)
 Configures the clock according to the prescaler passed. More...
 
void XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
 This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used. More...
 
s32 XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)
 This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More...
 
s32 XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)
 This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More...
 
u32 XQspiPsu_GetOptions (XQspiPsu *InstancePtr)
 This function gets the options for the QSPIPSU device. More...
 
s32 XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)
 This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options. More...
 
void XQspiPsu_SetWP (XQspiPsu *InstancePtr, u8 Value)
 This function sets the Write Protect and Hold options for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Write Protect and Hold options. More...
 

Variables

XQspiPsu_Config XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
 This table contains configuration information for each QSPIPSU device in the system. More...
 
XQspiPsu_Config XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
 This table contains configuration information for each QSPIPSU device in the system. More...
 

Macro Definition Documentation

◆ BYTES1024_PER_PAGE

#define BYTES1024_PER_PAGE   1024U

#include <xqspipsu.h>

1024 Bytes per Page

◆ BYTES256_PER_PAGE

#define BYTES256_PER_PAGE   256U

#include <xqspipsu.h>

Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry.

256 Bytes per Page

◆ BYTES512_PER_PAGE

#define BYTES512_PER_PAGE   512U

#include <xqspipsu.h>

512 Bytes per Page

◆ NUM_OF_SECTORS1024

#define NUM_OF_SECTORS1024   1024U

#include <xqspipsu.h>

1024 Sectors

◆ NUM_OF_SECTORS128

#define NUM_OF_SECTORS128   128U

#include <xqspipsu.h>

128 Sectors

◆ NUM_OF_SECTORS16

#define NUM_OF_SECTORS16   16U

#include <xqspipsu.h>

16 Sectors

◆ NUM_OF_SECTORS2

#define NUM_OF_SECTORS2   2U

#include <xqspipsu.h>

2 Sectors

◆ NUM_OF_SECTORS2048

#define NUM_OF_SECTORS2048   2048U

#include <xqspipsu.h>

2048 Sectors

◆ NUM_OF_SECTORS256

#define NUM_OF_SECTORS256   256U

#include <xqspipsu.h>

256 Sectors

◆ NUM_OF_SECTORS32

#define NUM_OF_SECTORS32   32U

#include <xqspipsu.h>

32 Sectors

◆ NUM_OF_SECTORS4

#define NUM_OF_SECTORS4   4U

#include <xqspipsu.h>

4 Sectors

◆ NUM_OF_SECTORS4096

#define NUM_OF_SECTORS4096   4096U

#include <xqspipsu.h>

4096 Sectors

◆ NUM_OF_SECTORS512

#define NUM_OF_SECTORS512   512U

#include <xqspipsu.h>

512 Sectors

◆ NUM_OF_SECTORS64

#define NUM_OF_SECTORS64   64U

#include <xqspipsu.h>

64 Sectors

◆ NUM_OF_SECTORS8

#define NUM_OF_SECTORS8   8U

#include <xqspipsu.h>

8 Sector

◆ NUM_OF_SECTORS8192

#define NUM_OF_SECTORS8192   8192U

#include <xqspipsu.h>

8192 Sectors

◆ PAGES1024_PER_SECTOR

#define PAGES1024_PER_SECTOR   1024U

#include <xqspipsu.h>

1024 Pages per Sector

◆ PAGES128_PER_SECTOR

#define PAGES128_PER_SECTOR   128U

#include <xqspipsu.h>

128 Pages per Sector

◆ PAGES16_PER_SECTOR

#define PAGES16_PER_SECTOR   16U

#include <xqspipsu.h>

16 Pages per Sector

◆ PAGES256_PER_SECTOR

#define PAGES256_PER_SECTOR   256U

#include <xqspipsu.h>

256 Pages per Sector

◆ PAGES512_PER_SECTOR

#define PAGES512_PER_SECTOR   512U

#include <xqspipsu.h>

512 Pages per Sector

◆ SECTOR_SIZE_128K

#define SECTOR_SIZE_128K   0X20000U

#include <xqspipsu.h>

128K Sector

◆ SECTOR_SIZE_256K

#define SECTOR_SIZE_256K   0X40000U

#include <xqspipsu.h>

256K Sector

◆ SECTOR_SIZE_512K

#define SECTOR_SIZE_512K   0X80000U

#include <xqspipsu.h>

512K Sector

◆ SECTOR_SIZE_64K

#define SECTOR_SIZE_64K   0X10000U

#include <xqspipsu.h>

64K Sector

◆ XQSPIPS_BASEADDR

#define XQSPIPS_BASEADDR   0XFF0F0000U

#include <xqspipsu_hw.h>

QSPI Base Address.

◆ XQSPIPS_EN_REG

#define XQSPIPS_EN_REG   ( ( XQSPIPS_BASEADDR ) + 0X00000014U )

#include <xqspipsu_hw.h>

Register: XQSPIPS_EN_REG.

◆ XQSPIPS_LQSPI_CFG_RST_STATE

#define XQSPIPS_LQSPI_CFG_RST_STATE   0x800238C1

#include <xqspipsu_hw.h>

Default LQSPI CFG value.

◆ XQSPIPS_LQSPI_CR_4_BYTE_STATE

#define XQSPIPS_LQSPI_CR_4_BYTE_STATE   0x88000013

#include <xqspipsu_hw.h>

Default 4 Byte LQSPI CR value.

◆ XQSPIPS_LQSPI_CR_INST_MASK

#define XQSPIPS_LQSPI_CR_INST_MASK   0x000000FF

#include <xqspipsu_hw.h>

Read instr code.

◆ XQSPIPS_LQSPI_CR_RST_STATE

#define XQSPIPS_LQSPI_CR_RST_STATE   0x80000003

#include <xqspipsu_hw.h>

Default LQSPI CR value.

◆ XQSPIPSU_BASEADDR

#define XQSPIPSU_BASEADDR   0xFF0F0100U

#include <xqspipsu_hw.h>

GQSPI Base Address.

◆ XQSPIPSU_CFG_OFFSET

#define XQSPIPSU_CFG_OFFSET   0X00000000U

◆ XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET   0X00000014U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_EN_REG.

◆ XQSPIPSU_FIFO_CTRL_OFFSET

#define XQSPIPSU_FIFO_CTRL_OFFSET   0X0000004CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_FIFO_CTRL.

◆ XQSPIPSU_GEN_FIFO_OFFSET

#define XQSPIPSU_GEN_FIFO_OFFSET   0X00000040U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_GEN_FIFO.

◆ XQSPIPSU_GF_SNAPSHOT_OFFSET

#define XQSPIPSU_GF_SNAPSHOT_OFFSET   0X00000060U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_GF_SNAPSHOT.

◆ XQSPIPSU_GF_THRESHOLD_OFFSET

#define XQSPIPSU_GF_THRESHOLD_OFFSET   0X00000050U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_GF_THRESHOLD.

◆ XQSPIPSU_GPIO_OFFSET

#define XQSPIPSU_GPIO_OFFSET   0X00000030U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_GPIO.

◆ XQSPIPSU_IDR_OFFSET

#define XQSPIPSU_IDR_OFFSET   0X0000000CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_IDR.

◆ XQSPIPSU_IER_OFFSET

#define XQSPIPSU_IER_OFFSET   0X00000008U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_IER.

◆ XQSPIPSU_IMR_OFFSET

#define XQSPIPSU_IMR_OFFSET   0X00000010U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_IMR.

◆ XQSPIPSU_ISR_OFFSET

#define XQSPIPSU_ISR_OFFSET   0X00000004U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_ISR.

Referenced by XQspiPsu_Abort(), and XQspiPsu_InterruptHandler().

◆ XQSPIPSU_LPBK_DLY_ADJ_OFFSET

#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET   0X00000038U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_LPBK_DLY_ADJ.

◆ XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK

#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK   0x01000000

#include <xqspipsu_hw.h>

Upper memory page.

◆ XQSPIPSU_LQSPI_CR_LINEAR_MASK

#define XQSPIPSU_LQSPI_CR_LINEAR_MASK   0x80000000

#include <xqspipsu_hw.h>

LQSPI mode enable.

◆ XQSPIPSU_LQSPI_CR_MODE_BITS_MASK

#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK   0x00FF0000

#include <xqspipsu_hw.h>

Mode value for dual I/O or quad I/O.

◆ XQSPIPSU_LQSPI_CR_MODE_EN_MASK

#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK   0x02000000

#include <xqspipsu_hw.h>

Enable mode bits.

◆ XQSPIPSU_LQSPI_CR_MODE_ON_MASK

#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK   0x01000000

#include <xqspipsu_hw.h>

Mode on.

◆ XQSPIPSU_LQSPI_CR_OFFSET [1/2]

#define XQSPIPSU_LQSPI_CR_OFFSET   0X000000A0U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_CFG.

◆ XQSPIPSU_LQSPI_CR_OFFSET [2/2]

#define XQSPIPSU_LQSPI_CR_OFFSET   0X000000A0U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_CFG.

◆ XQSPIPSU_LQSPI_CR_SEP_BUS_MASK

#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK   0x20000000

#include <xqspipsu_hw.h>

Seperate memory bus.

◆ XQSPIPSU_LQSPI_CR_TWO_MEM_MASK

#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK   0x40000000

#include <xqspipsu_hw.h>

Both memories or one.

◆ XQSPIPSU_LQSPI_CR_U_PAGE_MASK

#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK   0x10000000

#include <xqspipsu_hw.h>

Upper memory page.

◆ XQSPIPSU_MOD_ID_OFFSET

#define XQSPIPSU_MOD_ID_OFFSET   0X000000FCU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_MOD_ID.

◆ XQSPIPSU_P_TO_OFFSET

#define XQSPIPSU_P_TO_OFFSET   0X00000058U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_P_TIMEOUT.

◆ XQSPIPSU_POLL_CFG_OFFSET

#define XQSPIPSU_POLL_CFG_OFFSET   0X00000054U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_POLL_CFG.

◆ XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET

#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET   0X00000728U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB.

◆ XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET

#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET   0X00000700U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_ADDR.

◆ XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET

#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET   0X00000724U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_CTRL2.

◆ XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET

#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET   0X0000070CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_CTRL.

◆ XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET

#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET   0X0000071CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_I_DIS.

◆ XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET

#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET   0X00000718U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_I_EN.

◆ XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET

#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET   0X00000714U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_I_STS.

◆ XQSPIPSU_QSPIDMA_DST_IMR_OFFSET

#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET   0X00000720U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_IMR.

◆ XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET

#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET   0X00000704U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_SIZE.

◆ XQSPIPSU_QSPIDMA_DST_STS_OFFSET

#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET   0X00000708U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_DST_STS.

◆ XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET

#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET   0X00000EFCU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_QSPIDMA_FUTURE_ECO.

◆ XQspiPsu_ReadReg

#define XQspiPsu_ReadReg (   BaseAddress,
  RegOffset 
)    XQspiPsu_In32((BaseAddress) + (RegOffset))

#include <xqspipsu_hw.h>

Read a register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to the target register.
Returns
The value read from the register.
Note
C-Style signature: u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)

Referenced by XQspiPsu_Abort(), XQspiPsu_ClearOptions(), XQspiPsu_GetOptions(), XQspiPsu_InterruptHandler(), XQspiPsu_Reset(), XQspiPsu_SetOptions(), XQspiPsu_SetReadMode(), and XQspiPsu_SetWP().

◆ XQSPIPSU_RX_COPY_OFFSET

#define XQSPIPSU_RX_COPY_OFFSET   0X00000064U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_RX_COPY.

◆ XQSPIPSU_RX_THRESHOLD_OFFSET

#define XQSPIPSU_RX_THRESHOLD_OFFSET   0X0000002CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_RX_THRESHOLD.

◆ XQSPIPSU_RXD_OFFSET

#define XQSPIPSU_RXD_OFFSET   0X00000020U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_RXD.

◆ XQSPIPSU_SEL_OFFSET

#define XQSPIPSU_SEL_OFFSET   0X00000044U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_SEL.

◆ XQSPIPSU_TX_THRESHOLD_OFFSET

#define XQSPIPSU_TX_THRESHOLD_OFFSET   0X00000028U

#include <xqspipsu_hw.h>

Register: XQSPIPSU_TX_THRESHOLD.

◆ XQSPIPSU_TXD_OFFSET

#define XQSPIPSU_TXD_OFFSET   0X0000001CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_TXD.

◆ XQspiPsu_WriteReg

#define XQspiPsu_WriteReg (   BaseAddress,
  RegOffset,
  RegisterValue 
)    XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

#include <xqspipsu_hw.h>

Write to a register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to target register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, u32 RegisterValue)

Referenced by XQspiPsu_Abort().

◆ XQSPIPSU_XFER_STS_OFFSET

#define XQSPIPSU_XFER_STS_OFFSET   0X0000005CU

#include <xqspipsu_hw.h>

Register: XQSPIPSU_XFER_STS.

Typedef Documentation

◆ XQspiPsu_StatusHandler

typedef void(* XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 ByteCount)

#include <xqspipsu.h>

The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

Parameters
CallBackRefis the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEventholds one or more status events that have occurred. See the XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback.
ByteCountindicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error.

Function Documentation

◆ XQspiPsu_Abort()

void XQspiPsu_Abort ( XQspiPsu InstancePtr)

#include <xqspipsu.c>

Aborts a transfer in progress by.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Returns
None.
Note

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQSPIPSU_ISR_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_Reset().

◆ XQspiPsu_CfgInitialize()

s32 XQspiPsu_CfgInitialize ( XQspiPsu InstancePtr,
XQspiPsu_Config ConfigPtr,
u32  EffectiveAddr 
)

#include <xqspipsu.c>

Initializes a specific XQspiPsu instance as such the driver is ready to use.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
ConfigPtris a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddris the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.
Returns
  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.
Note
None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, and XQspiPsu::IsBusy.

◆ XQspiPsu_ClearOptions()

s32 XQspiPsu_ClearOptions ( XQspiPsu InstancePtr,
u32  Options 
)

#include <xqspipsu.h>

This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.

The device must be idle rather than busy transferring data before setting these device options.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Optionscontains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.
Note
This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_GetOptions()

u32 XQspiPsu_GetOptions ( XQspiPsu InstancePtr)

#include <xqspipsu.h>

This function gets the options for the QSPIPSU device.

The options control how the device behaves relative to the QSPIPSU bus.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Returns

Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.

Note
None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_InterruptHandler()

s32 XQspiPsu_InterruptHandler ( XQspiPsu InstancePtr)

#include <xqspipsu.c>

Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if transfer fails.
Note
None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::ReadMode, XQSPIPSU_ISR_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_InterruptTransfer()

s32 XQspiPsu_InterruptTransfer ( XQspiPsu InstancePtr,
XQspiPsu_Msg Msg,
u32  NumMsg 
)

#include <xqspipsu.c>

This function initiates a transfer on the bus and enables interrupts.

The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Msgis a pointer to the structure containing transfer data.
NumMsgis the number of messages to be transferred.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if transfer fails.
  • XST_DEVICE_BUSY if a transfer is already in progress.
Note
None.

References XQspiPsu::IsBusy, and XQspiPsu::IsReady.

◆ XQspiPsu_LookupConfig()

XQspiPsu_Config * XQspiPsu_LookupConfig ( u16  DeviceId)

#include <xqspipsu.h>

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters
DeviceIdcontains the ID of the device to look up the configuration for.
Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.

Note
None.

◆ XQspiPsu_PolledTransfer()

s32 XQspiPsu_PolledTransfer ( XQspiPsu InstancePtr,
XQspiPsu_Msg Msg,
u32  NumMsg 
)

#include <xqspipsu.c>

This function performs a transfer on the bus in polled mode.

The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Msgis a pointer to the structure containing transfer data.
NumMsgis the number of messages to be transferred.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if transfer fails.
  • XST_DEVICE_BUSY if a transfer is already in progress.
Note
None.

References XQspiPsu::IsBusy, and XQspiPsu::IsReady.

◆ XQspiPsu_Reset()

void XQspiPsu_Reset ( XQspiPsu InstancePtr)

#include <xqspipsu.c>

Resets the QSPIPSU device.

Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Returns
None.
Note
None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Abort(), XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_SelectFlash()

void XQspiPsu_SelectFlash ( XQspiPsu InstancePtr,
u8  FlashCS,
u8  FlashBus 
)

#include <xqspipsu.h>

This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used.

This API should be called atleast once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
FlashCS- Flash Chip Select.
FlashBus- Flash Bus (Upper, Lower or Both).
Returns
  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.
Note
If this funciton is not called atleast once in the application, the driver assumes there is a single flash connected to the lower bus and CS line.

◆ XQspiPsu_SetClkPrescaler()

s32 XQspiPsu_SetClkPrescaler ( XQspiPsu InstancePtr,
u8  Prescaler 
)

#include <xqspipsu.h>

Configures the clock according to the prescaler passed.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Prescaler- clock prescaler to be set.
Returns
  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started.
  • XST_DEVICE_BUSY if the device is currently transferring data. It must be stopped to re-initialize.
Note
None.

References XQspiPsu::IsReady.

◆ XQspiPsu_SetOptions()

s32 XQspiPsu_SetOptions ( XQspiPsu InstancePtr,
u32  Options 
)

#include <xqspipsu.h>

This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.

The device must be idle rather than busy transferring data before setting these device options.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Optionscontains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.
Note
This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_SetReadMode()

s32 XQspiPsu_SetReadMode ( XQspiPsu InstancePtr,
u32  Mode 
)

#include <xqspipsu.h>

This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Modecontains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
Returns
  • XST_SUCCESS if options are successfully set.
  • XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.
Note
This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_SetStatusHandler()

void XQspiPsu_SetStatusHandler ( XQspiPsu InstancePtr,
void *  CallBackRef,
XQspiPsu_StatusHandler  FuncPointer 
)

#include <xqspipsu.c>

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

XST_SPI_TRANSFER_DONE           The requested data transfer is done
XST_SPI_TRANSMIT_UNDERRUN       As a slave device, the master clocked data
                        but there were none available in the transmit
                        register/FIFO. This typically means the slave
                        application did not issue a transfer request
                        fast enough, or the processor/driver could not
                        fill the transmit register/FIFO fast enough.
XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
                        but the receive data register/FIFO was full.
 
Parameters
InstancePtris a pointer to the XQspiPsu instance.
CallBackRefis the upper layer callback reference passed back when the callback function is invoked.
FuncPointeris the pointer to the callback function.
Returns
None.
Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XQspiPsu::IsReady, and XQspiPsu::StatusRef.

◆ XQspiPsu_SetWP()

void XQspiPsu_SetWP ( XQspiPsu InstancePtr,
u8  Value 
)

#include <xqspipsu.h>

This function sets the Write Protect and Hold options for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Write Protect and Hold options.

Parameters
InstancePtris a pointer to the XQspiPsu instance.
Valueof the WP_HOLD bit in configuration register
Returns
None
Note
This function is not thread-safe. This function can only be used with single flash configuration and x1/x2 data mode. This function cannot be used with x4 data mode and dual parallel and stacked flash configuration.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.

◆ XQspiPsu_WriteProtectToggle()

void XQspiPsu_WriteProtectToggle ( XQspiPsu QspiPsuPtr,
u32  Toggle 
)

#include <xqspipsu.c>

This API enables/ disables Write Protect pin on the flash parts.

Parameters
QspiPsuPtris a pointer to the QSPIPSU driver component to use.
Toggleis a value of the GPIO pin
Returns
None
Note
By default WP pin as per the QSPI controller is driven High which means no write protection. Calling this function once will enable the protection.

References XQspiPsu::Config, and XQspiPsu_Config::ConnectionMode.

Variable Documentation

◆ XQspiPsu_ConfigTable [1/2]

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

#include <xqspipsu_sinit.c>

This table contains configuration information for each QSPIPSU device in the system.

◆ XQspiPsu_ConfigTable [2/2]

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

#include <xqspipsu_g.c>

Initial value:
= {
{
XPAR_XQSPIPSU_0_DEVICE_ID,
XPAR_XQSPIPSU_0_BASEADDR,
XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
XPAR_XQSPIPSU_0_QSPI_MODE,
XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH,
XPAR_XQSPIPSU_0_IS_CACHE_COHERENT
},
}

This table contains configuration information for each QSPIPSU device in the system.