dp12
Xilinx SDK Drivers API Documentation
Dp_v6_0

Data Structures

struct  XDp_Config
 This typedef contains configuration information for the DisplayPort core. More...
 
struct  XDp_TxSinkConfig
 This typedef contains configuration information about the RX device. More...
 
struct  XDp_TxLinkConfig
 This typedef contains configuration information about the main link settings. More...
 
struct  XDp_TxMainStreamAttributes
 This typedef contains the main stream attributes which determine how the video will be displayed. More...
 
struct  XDp_TxMstStream
 This typedef describes a stream when the driver is running in multi-stream transport (MST) mode. More...
 
struct  XDp_TxBoardChar
 This typedef describes some board characteristics information that affects link training. More...
 
struct  XDp_TxTopologyNode
 This typedef describes a downstream DisplayPort device when the driver is running in multi-stream transport (MST) mode. More...
 
struct  XDp_TxTopology
 This typedef describes a the entire topology of connected downstream DisplayPort devices (from the DisplayPort TX) when the driver is operating in multi-stream transport (MST) mode. More...
 
struct  XDp_SbMsgLinkAddressReplyPortDetail
 This typedef describes a port that is connected to a DisplayPort branch device. More...
 
struct  XDp_SbMsgLinkAddressReplyDeviceInfo
 This typedef describes a DisplayPort branch device. More...
 
struct  XDp_RxLinkConfig
 This typedef contains configuration information about the main link settings. More...
 
struct  XDp_RxIicMapEntry
 This typedef represents one I2C map entry for a device. More...
 
struct  XDp_RxDpcdMap
 This typedef represents the DPCD address map for a device. More...
 
struct  XDp_RxPort
 This typedef contains information on the directly connected ports to the RX branch. More...
 
struct  XDp_RxTopology
 This typedef contains topology information on directly connected sinks and of the RX branch itself. More...
 
struct  XDp_Tx
 The XDp driver instance data representing the TX mode of operation. More...
 
struct  XDp_Rx
 The XDp driver instance data representing the RX mode of operation. More...
 
struct  XDp
 The XDp instance data. More...
 

Macros

#define XDp_GetCoreType(InstancePtr)
 This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX). More...
 
#define XDp_TxCfgSetRGB(InstancePtr, Stream)
 The following functions set the color encoding scheme for a given stream. More...
 
#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT   3
 The number of I2C user- defined entries in the I2C map of each port. More...
 
#define XDP_GUID_NBYTES   16
 The number of bytes for the global unique ID. More...
 
#define XDP_MAX_NPORTS   16
 The maximum number of ports connected to a DisplayPort device. More...
 
#define XDp_ReadReg(BaseAddress, RegOffset)   XDp_In32((BaseAddress) + (RegOffset))
 This is a low-level function that reads from the specified register. More...
 
#define XDp_WriteReg(BaseAddress, RegOffset, Data)   XDp_Out32((BaseAddress) + (RegOffset), (Data))
 This is a low-level function that writes to the specified register. More...
 

Typedefs

typedef void(* XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds)
 Callback type which represents a custom timer wait handler. More...
 
typedef void(* XDp_IntrHandler) (void *InstancePtr)
 Callback type which represents the handler for interrupts. More...
 

Enumerations

enum  XDp_CoreType
 This typedef enumerates the RX and TX modes of operation for the DisplayPort core. More...
 
enum  XDp_DynamicRange
 This typedef enumerates the dynamic ranges available to the DisplayPort core. More...
 
enum  Dp_Rx_HandlerType
 This typedef enumerates the handlers for the the DisplayPort Receiver. More...
 
enum  XDp_Tx_HandlerType
 This typedef enumerates the handlers for the the DisplayPort Transmitter. More...
 

Functions

void XDp_CfgInitialize (XDp *InstancePtr, XDp_Config *ConfigPtr, UINTPTR EffectiveAddr)
 This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure. More...
 
u32 XDp_Initialize (XDp *InstancePtr)
 This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode. More...
 
void XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef)
 This function installs a custom delay/sleep function to be used by the XDp driver. More...
 
void XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds)
 This function is the delay/sleep function for the XDp driver. More...
 
u8 XDp_IsLinkRateValid (XDp *InstancePtr, u8 LinkRate)
 This function checks the validity of the link rate. More...
 
u8 XDp_IsLaneCountValid (XDp *InstancePtr, u8 LaneCount)
 This function checks the validity of the lane count. More...
 
XDp_ConfigXDp_LookupConfig (u16 DeviceId)
 This function looks for the device configuration based on the unique device ID. More...
 
void XDp_InterruptHandler (XDp *InstancePtr)
 This function is the interrupt handler for the XDp driver. More...
 
u32 XDp_SelfTest (XDp *InstancePtr)
 This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. More...
 

Variables

u8 GuidTable [16][XDP_GUID_NBYTES]
 This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function. More...
 
XDp_Config XDp_ConfigTable [XPAR_XDP_NUM_INSTANCES]
 A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. More...
 

DP generic definitions: Link bandwith and lane count.

#define XDP_LINK_BW_SET_162GBPS   0x06
 1.62 Gbps link rate. More...
 
#define XDP_LINK_BW_SET_270GBPS   0x0A
 2.70 Gbps link rate. More...
 
#define XDP_LINK_BW_SET_540GBPS   0x14
 5.40 Gbps link rate. More...
 
#define XDP_LANE_COUNT_SET_1   0x01
 Lane count of 1. More...
 
#define XDP_LANE_COUNT_SET_2   0x02
 Lane count of 2. More...
 
#define XDP_LANE_COUNT_SET_4   0x04
 Lane count of 4. More...
 

DP generic definitions: Bits per color components.

#define XDP_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
 Bit depth per color component (BDC). More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_SHIFT   5
 Shift bits for BDC. More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_6BPC   0x0
 6 bits per component. More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_8BPC   0x1
 8 bits per component. More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_10BPC   0x2
 10 bits per component. More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_12BPC   0x3
 12 bits per component. More...
 
#define XDP_MAIN_STREAMX_MISC0_BDC_16BPC   0x4
 16 bits per component. More...
 

DP generic definitions: Miscellaneous components; color format.

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
 Component format. More...
 
#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
 Shift bits for component format. More...
 
#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0
 Stream's component format is RGB. More...
 
#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x5
 Stream's component format is YcbCr 4:2:2. More...
 
#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x6
 Stream's component format is YcbCr 4:4:4. More...
 

DisplayPort Configuration Data: Receiver capability field.

Address mapping for the DisplayPort Configuration Data (DPCD) of the downstream device.

#define XDP_DPCD_REV   0x00000
 
#define XDP_DPCD_MAX_LINK_RATE   0x00001
 
#define XDP_DPCD_MAX_LANE_COUNT   0x00002
 
#define XDP_DPCD_MAX_DOWNSPREAD   0x00003
 
#define XDP_DPCD_NORP_PWR_V_CAP   0x00004
 
#define XDP_DPCD_DOWNSP_PRESENT   0x00005
 
#define XDP_DPCD_ML_CH_CODING_CAP   0x00006
 
#define XDP_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007
 
#define XDP_DPCD_RX_PORT0_CAP_0   0x00008
 
#define XDP_DPCD_RX_PORT0_CAP_1   0x00009
 
#define XDP_DPCD_RX_PORT1_CAP_0   0x0000A
 
#define XDP_DPCD_RX_PORT1_CAP_1   0x0000B
 
#define XDP_DPCD_I2C_SPEED_CTL_CAP   0x0000C
 
#define XDP_DPCD_EDP_CFG_CAP   0x0000D
 
#define XDP_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E
 
#define XDP_DPCD_ADAPTER_CAP   0x0000F
 
#define XDP_DPCD_FAUX_CAP   0x00020
 
#define XDP_DPCD_MSTM_CAP   0x00021
 
#define XDP_DPCD_NUM_AUDIO_EPS   0x00022
 
#define XDP_DPCD_AV_GRANULARITY   0x00023
 
#define XDP_DPCD_AUD_DEC_LAT_7_0   0x00024
 
#define XDP_DPCD_AUD_DEC_LAT_15_8   0x00025
 
#define XDP_DPCD_AUD_PP_LAT_7_0   0x00026
 
#define XDP_DPCD_AUD_PP_LAT_15_8   0x00027
 
#define XDP_DPCD_VID_INTER_LAT   0x00028
 
#define XDP_DPCD_VID_PROG_LAT   0x00029
 
#define XDP_DPCD_REP_LAT   0x0002A
 
#define XDP_DPCD_AUD_DEL_INS_7_0   0x0002B
 
#define XDP_DPCD_AUD_DEL_INS_15_8   0x0002C
 
#define XDP_DPCD_AUD_DEL_INS_23_16   0x0002D
 
#define XDP_DPCD_GUID   0x00030
 
#define XDP_DPCD_RX_GTC_VALUE_7_0   0x00054
 
#define XDP_DPCD_RX_GTC_VALUE_15_8   0x00055
 
#define XDP_DPCD_RX_GTC_VALUE_23_16   0x00056
 
#define XDP_DPCD_RX_GTC_VALUE_31_24   0x00057
 
#define XDP_DPCD_RX_GTC_MSTR_REQ   0x00058
 
#define XDP_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059
 
#define XDP_DPCD_DOWNSP_0_CAP   0x00080
 
#define XDP_DPCD_DOWNSP_1_CAP   0x00081
 
#define XDP_DPCD_DOWNSP_2_CAP   0x00082
 
#define XDP_DPCD_DOWNSP_3_CAP   0x00083
 
#define XDP_DPCD_DOWNSP_0_DET_CAP   0x00080
 
#define XDP_DPCD_DOWNSP_1_DET_CAP   0x00084
 
#define XDP_DPCD_DOWNSP_2_DET_CAP   0x00088
 
#define XDP_DPCD_DOWNSP_3_DET_CAP   0x0008C
 

DisplayPort Configuration Data: Link configuration field.

#define XDP_DPCD_LINK_BW_SET   0x00100
 
#define XDP_DPCD_LANE_COUNT_SET   0x00101
 
#define XDP_DPCD_TP_SET   0x00102
 
#define XDP_DPCD_TRAINING_LANE0_SET   0x00103
 
#define XDP_DPCD_TRAINING_LANE1_SET   0x00104
 
#define XDP_DPCD_TRAINING_LANE2_SET   0x00105
 
#define XDP_DPCD_TRAINING_LANE3_SET   0x00106
 
#define XDP_DPCD_DOWNSPREAD_CTRL   0x00107
 
#define XDP_DPCD_ML_CH_CODING_SET   0x00108
 
#define XDP_DPCD_I2C_SPEED_CTL_SET   0x00109
 
#define XDP_DPCD_EDP_CFG_SET   0x0010A
 
#define XDP_DPCD_LINK_QUAL_LANE0_SET   0x0010B
 
#define XDP_DPCD_LINK_QUAL_LANE1_SET   0x0010C
 
#define XDP_DPCD_LINK_QUAL_LANE2_SET   0x0010D
 
#define XDP_DPCD_LINK_QUAL_LANE3_SET   0x0010E
 
#define XDP_DPCD_TRAINING_LANE0_1_SET2   0x0010F
 
#define XDP_DPCD_TRAINING_LANE2_3_SET2   0x00110
 
#define XDP_DPCD_MSTM_CTRL   0x00111
 
#define XDP_DPCD_AUDIO_DELAY_7_0   0x00112
 
#define XDP_DPCD_AUDIO_DELAY_15_8   0x00113
 
#define XDP_DPCD_AUDIO_DELAY_23_6   0x00114
 
#define XDP_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118
 
#define XDP_DPCD_FAUX_MODE_CTRL   0x00120
 
#define XDP_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121
 
#define XDP_DPCD_BACK_CH_STATUS   0x00122
 
#define XDP_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123
 
#define XDP_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125
 
#define XDP_DPCD_TX_GTC_VALUE_7_0   0x00154
 
#define XDP_DPCD_TX_GTC_VALUE_15_8   0x00155
 
#define XDP_DPCD_TX_GTC_VALUE_23_16   0x00156
 
#define XDP_DPCD_TX_GTC_VALUE_31_24   0x00157
 
#define XDP_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158
 
#define XDP_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159
 
#define XDP_DPCD_ADAPTER_CTRL   0x001A0
 
#define XDP_DPCD_BRANCH_DEVICE_CTRL   0x001A1
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2
 

DisplayPort Configuration Data: Link/sink status field.

#define XDP_DPCD_SINK_COUNT   0x00200
 
#define XDP_DPCD_DEVICE_SERVICE_IRQ   0x00201
 
#define XDP_DPCD_STATUS_LANE_0_1   0x00202
 
#define XDP_DPCD_STATUS_LANE_2_3   0x00203
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204
 
#define XDP_DPCD_SINK_STATUS   0x00205
 
#define XDP_DPCD_ADJ_REQ_LANE_0_1   0x00206
 
#define XDP_DPCD_ADJ_REQ_LANE_2_3   0x00207
 
#define XDP_DPCD_TRAINING_SCORE_LANE_0   0x00208
 
#define XDP_DPCD_TRAINING_SCORE_LANE_1   0x00209
 
#define XDP_DPCD_TRAINING_SCORE_LANE_2   0x0020A
 
#define XDP_DPCD_TRAINING_SCORE_LANE_3   0x0020B
 
#define XDP_DPCD_ADJ_REQ_PC2   0x0020C
 
#define XDP_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216
 

DisplayPort Configuration Data: Automated testing sub-field.

#define XDP_DPCD_FAUX_FORWARD_CH_STATUS   0x00280
 
#define XDP_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281
 
#define XDP_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282
 
#define XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0
 
#define XDP_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum)   (XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
 

DisplayPort Configuration Data: Sink control field.

#define XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600
 

DisplayPort Configuration Data: Sideband message buffers.

#define XDP_DPCD_DOWN_REQ   0x01000
 
#define XDP_DPCD_UP_REP   0x01200
 
#define XDP_DPCD_DOWN_REP   0x01400
 
#define XDP_DPCD_UP_REQ   0x01600
 

DisplayPort Configuration Data: Event status indicator field.

#define XDP_DPCD_SINK_COUNT_ESI   0x02002
 
#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003
 
#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004
 
#define XDP_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005
 
#define XDP_DPCD_SINK_LANE0_1_STATUS   0x0200C
 
#define XDP_DPCD_SINK_LANE2_3_STATUS   0x0200D
 
#define XDP_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E
 
#define XDP_DPCD_SINK_STATUS_ESI   0x0200F
 

DisplayPort Configuration Data: Field addresses and sizes.

#define XDP_DPCD_RECEIVER_CAP_FIELD_START   XDP_DPCD_REV
 
#define XDP_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100
 
#define XDP_DPCD_LINK_CFG_FIELD_START   XDP_DPCD_LINK_BW_SET
 
#define XDP_DPCD_LINK_CFG_FIELD_SIZE   0x100
 
#define XDP_DPCD_LINK_SINK_STATUS_FIELD_START   XDP_DPCD_SINK_COUNT
 
#define XDP_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17
 

DisplayPort Configuration Data: Receiver capability field masks,

shifts, and register values.

#define XDP_DPCD_REV_MNR_MASK   0x0F
 
#define XDP_DPCD_REV_MJR_MASK   0xF0
 
#define XDP_DPCD_REV_MJR_SHIFT   4
 
#define XDP_DPCD_MAX_LINK_RATE_162GBPS   0x06
 
#define XDP_DPCD_MAX_LINK_RATE_270GBPS   0x0A
 
#define XDP_DPCD_MAX_LINK_RATE_540GBPS   0x14
 
#define XDP_DPCD_MAX_LANE_COUNT_MASK   0x1F
 
#define XDP_DPCD_MAX_LANE_COUNT_1   0x01
 
#define XDP_DPCD_MAX_LANE_COUNT_2   0x02
 
#define XDP_DPCD_MAX_LANE_COUNT_4   0x04
 
#define XDP_DPCD_TPS3_SUPPORT_MASK   0x40
 
#define XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80
 
#define XDP_DPCD_MAX_DOWNSPREAD_MASK   0x01
 
#define XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40
 
#define XDP_DPCD_DOWNSP_PRESENT_MASK   0x01
 
#define XDP_DPCD_DOWNSP_TYPE_MASK   0x06
 
#define XDP_DPCD_DOWNSP_TYPE_SHIFT   1
 
#define XDP_DPCD_DOWNSP_TYPE_DP   0x0
 
#define XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1
 
#define XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2
 
#define XDP_DPCD_DOWNSP_TYPE_OTHERS   0x3
 
#define XDP_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08
 
#define XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10
 
#define XDP_DPCD_ML_CH_CODING_MASK   0x01
 
#define XDP_DPCD_DOWNSP_COUNT_MASK   0x0F
 
#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40
 
#define XDP_DPCD_OUI_SUPPORT_MASK   0x80
 
#define XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02
 
#define XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04
 
#define XDP_DPCD_I2C_SPEED_CTL_NONE   0x00
 
#define XDP_DPCD_I2C_SPEED_CTL_1KBIPS   0x01
 
#define XDP_DPCD_I2C_SPEED_CTL_5KBIPS   0x02
 
#define XDP_DPCD_I2C_SPEED_CTL_10KBIPS   0x04
 
#define XDP_DPCD_I2C_SPEED_CTL_100KBIPS   0x08
 
#define XDP_DPCD_I2C_SPEED_CTL_400KBIPS   0x10
 
#define XDP_DPCD_I2C_SPEED_CTL_1MBIPS   0x20
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_4MS   0x01
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_8MS   0x02
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_12MS   0x03
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_16MS   0x04
 
#define XDP_DPCD_FAUX_CAP_MASK   0x01
 
#define XDP_DPCD_MST_CAP_MASK   0x01
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5
 
#define XDP_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3
 
#define XDP_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01
 
#define XDP_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02
 
#define XDP_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04
 

DisplayPort Configuration Data: Link configuration field masks,

shifts, and register values.

#define XDP_DPCD_LINK_BW_SET_162GBPS   0x06
 
#define XDP_DPCD_LINK_BW_SET_270GBPS   0x0A
 
#define XDP_DPCD_LINK_BW_SET_540GBPS   0x14
 
#define XDP_DPCD_LANE_COUNT_SET_MASK   0x1F
 
#define XDP_DPCD_LANE_COUNT_SET_1   0x01
 
#define XDP_DPCD_LANE_COUNT_SET_2   0x02
 
#define XDP_DPCD_LANE_COUNT_SET_4   0x04
 
#define XDP_DPCD_ENHANCED_FRAME_EN_MASK   0x80
 
#define XDP_DPCD_TP_SEL_MASK   0x03
 
#define XDP_DPCD_TP_SEL_OFF   0x0
 
#define XDP_DPCD_TP_SEL_TP1   0x1
 
#define XDP_DPCD_TP_SEL_TP2   0x2
 
#define XDP_DPCD_TP_SEL_TP3   0x3
 
#define XDP_DPCD_TP_SET_LQP_MASK   0x06
 
#define XDP_DPCD_TP_SET_LQP_SHIFT   2
 
#define XDP_DPCD_TP_SET_LQP_OFF   0x0
 
#define XDP_DPCD_TP_SET_LQP_D102_TEST   0x1
 
#define XDP_DPCD_TP_SET_LQP_SER_MES   0x2
 
#define XDP_DPCD_TP_SET_LQP_PRBS7   0x3
 
#define XDP_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10
 
#define XDP_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2
 
#define XDP_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03
 
#define XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
 
#define XDP_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18
 
#define XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
 
#define XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
 
#define XDP_DPCD_SPREAD_AMP_MASK   0x10
 
#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80
 
#define XDP_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03
 
#define XDP_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40
 
#define XDP_DPCD_MST_EN_MASK   0x01
 
#define XDP_DPCD_UP_REQ_EN_MASK   0x02
 
#define XDP_DPCD_UP_IS_SRC_MASK   0x03
 

DisplayPort Configuration Data: Link/sink status field masks, shifts,

and register values.

#define XDP_DPCD_SINK_COUNT_LOW_MASK   0x3F
 
#define XDP_DPCD_SINK_CP_READY_MASK   0x40
 
#define XDP_DPCD_SINK_COUNT_HIGH_MASK   0x80
 
#define XDP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT   1
 
#define XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01
 
#define XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02
 
#define XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04
 
#define XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10
 
#define XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20
 
#define XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40
 
#define XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01
 
#define XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02
 
#define XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04
 
#define XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10
 
#define XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20
 
#define XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80
 
#define XDP_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01
 
#define XDP_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6
 

Extended Display Identification Data: Field addresses and sizes.

Address mapping for the Extended Display Identification Data (EDID) of the downstream device.

#define XDP_SEGPTR_ADDR   0x30
 
#define XDP_EDID_ADDR   0x50
 
#define XDP_EDID_BLOCK_SIZE   128
 
#define XDP_EDID_DTD_DD(Num)   (0x36 + (18 * Num))
 
#define XDP_EDID_PTM   XDP_EDID_DTD_DD(0)
 
#define XDP_EDID_EXT_BLOCK_COUNT   0x7E
 

Extended Display Identification Data: Register offsets for the

Detailed Timing Descriptor (DTD).

#define XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00
 
#define XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01
 
#define XDP_EDID_DTD_HRES_LSB   0x02
 
#define XDP_EDID_DTD_HBLANK_LSB   0x03
 
#define XDP_EDID_DTD_HRES_HBLANK_U4   0x04
 
#define XDP_EDID_DTD_VRES_LSB   0x05
 
#define XDP_EDID_DTD_VBLANK_LSB   0x06
 
#define XDP_EDID_DTD_VRES_VBLANK_U4   0x07
 
#define XDP_EDID_DTD_HFPORCH_LSB   0x08
 
#define XDP_EDID_DTD_HSPW_LSB   0x09
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4   0x0A
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2   0x0B
 
#define XDP_EDID_DTD_HIMGSIZE_MM_LSB   0x0C
 
#define XDP_EDID_DTD_VIMGSIZE_MM_LSB   0x0D
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4   0x0E
 
#define XDP_EDID_DTD_HBORDER   0x0F
 
#define XDP_EDID_DTD_VBORDER   0x10
 
#define XDP_EDID_DTD_SIGNAL   0x11
 

Extended Display Identification Data: Masks, shifts, and register

values.

#define XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F
 
#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0
 
#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4
 
#define XDP_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02
 
#define XDP_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04
 
#define XDP_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1
 
#define XDP_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2
 

Stream identification.

Multi-stream transport (MST) definitions.

#define XDP_TX_STREAM_ID1   1
 
#define XDP_TX_STREAM_ID2   2
 
#define XDP_TX_STREAM_ID3   3
 
#define XDP_TX_STREAM_ID4   4
 

Sideband message codes when the driver is in MST mode.

#define XDP_SBMSG_LINK_ADDRESS   0x01
 
#define XDP_SBMSG_CONNECTION_STATUS_NOTIFY   0x02
 
#define XDP_SBMSG_ENUM_PATH_RESOURCES   0x10
 
#define XDP_SBMSG_ALLOCATE_PAYLOAD   0x11
 
#define XDP_SBMSG_QUERY_PAYLOAD   0x12
 
#define XDP_SBMSG_RESOURCE_STATUS_NOTIFY   0x13
 
#define XDP_SBMSG_CLEAR_PAYLOAD_ID_TABLE   0x14
 
#define XDP_SBMSG_REMOTE_DPCD_READ   0x20
 
#define XDP_SBMSG_REMOTE_DPCD_WRITE   0x21
 
#define XDP_SBMSG_REMOTE_I2C_READ   0x22
 
#define XDP_SBMSG_REMOTE_I2C_WRITE   0x23
 
#define XDP_SBMSG_POWER_UP_PHY   0x24
 
#define XDP_SBMSG_POWER_DOWN_PHY   0x25
 
#define XDP_SBMSG_SINK_EVENT_NOTIFY   0x30
 
#define XDP_SBMSG_QUERY_STREAM_ENCRYPT_STATUS   0x38
 
#define XDP_SBMSG_NAK_REASON_WRITE_FAILURE   0x01
 
#define XDP_SBMSG_NAK_REASON_INVALID_RAD   0x02
 
#define XDP_SBMSG_NAK_REASON_CRC_FAILURE   0x03
 
#define XDP_SBMSG_NAK_REASON_BAD_PARAM   0x04
 
#define XDP_SBMSG_NAK_REASON_DEFER   0x05
 
#define XDP_SBMSG_NAK_REASON_LINK_FAILURE   0x06
 
#define XDP_SBMSG_NAK_REASON_NO_RESOURCES   0x07
 
#define XDP_SBMSG_NAK_REASON_DPCD_FAIL   0x08
 
#define XDP_SBMSG_NAK_REASON_I2C_NAK   0x09
 
#define XDP_SBMSG_NAK_REASON_ALLOCATE_FAIL   0x0A
 

Register access macro definitions.

#define XDp_In32   Xil_In32
 
#define XDp_Out32   Xil_Out32
 

Macro Definition Documentation

◆ XDp_GetCoreType

#define XDp_GetCoreType (   InstancePtr)

#include <xdp.h>

Value:
((InstancePtr)->Config.IsRx \
? XDP_RX : XDP_TX)

This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX).

Parameters
InstancePtris a pointer to the XDp instance.
Returns
XDP_RX if the core is of type RX. XDP_TX if the core is of type TX.
Note
C-style signature: XDp_CoreType XDp_GetCoreType(XDp *InstancePtr)

Referenced by XDp_CfgInitialize(), XDp_Initialize(), XDp_InterruptHandler(), and XDp_SelfTest().

◆ XDP_GUID_NBYTES

#define XDP_GUID_NBYTES   16

#include <xdp_hw.h>

The number of bytes for the global unique ID.

◆ XDP_LANE_COUNT_SET_1

#define XDP_LANE_COUNT_SET_1   0x01

#include <xdp_hw.h>

Lane count of 1.

Referenced by XDp_IsLaneCountValid().

◆ XDP_LANE_COUNT_SET_2

#define XDP_LANE_COUNT_SET_2   0x02

#include <xdp_hw.h>

Lane count of 2.

Referenced by XDp_IsLaneCountValid().

◆ XDP_LANE_COUNT_SET_4

#define XDP_LANE_COUNT_SET_4   0x04

#include <xdp_hw.h>

Lane count of 4.

Referenced by XDp_IsLaneCountValid().

◆ XDP_LINK_BW_SET_162GBPS

#define XDP_LINK_BW_SET_162GBPS   0x06

#include <xdp_hw.h>

1.62 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_LINK_BW_SET_270GBPS

#define XDP_LINK_BW_SET_270GBPS   0x0A

#include <xdp_hw.h>

2.70 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_LINK_BW_SET_540GBPS

#define XDP_LINK_BW_SET_540GBPS   0x14

#include <xdp_hw.h>

5.40 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_MAIN_STREAMX_MISC0_BDC_10BPC

#define XDP_MAIN_STREAMX_MISC0_BDC_10BPC   0x2

#include <xdp_hw.h>

10 bits per component.

◆ XDP_MAIN_STREAMX_MISC0_BDC_12BPC

#define XDP_MAIN_STREAMX_MISC0_BDC_12BPC   0x3

#include <xdp_hw.h>

12 bits per component.

◆ XDP_MAIN_STREAMX_MISC0_BDC_16BPC

#define XDP_MAIN_STREAMX_MISC0_BDC_16BPC   0x4

#include <xdp_hw.h>

16 bits per component.

◆ XDP_MAIN_STREAMX_MISC0_BDC_6BPC

#define XDP_MAIN_STREAMX_MISC0_BDC_6BPC   0x0

#include <xdp_hw.h>

6 bits per component.

◆ XDP_MAIN_STREAMX_MISC0_BDC_8BPC

#define XDP_MAIN_STREAMX_MISC0_BDC_8BPC   0x1

#include <xdp_hw.h>

8 bits per component.

◆ XDP_MAIN_STREAMX_MISC0_BDC_MASK

#define XDP_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0

#include <xdp_hw.h>

Bit depth per color component (BDC).

◆ XDP_MAIN_STREAMX_MISC0_BDC_SHIFT

#define XDP_MAIN_STREAMX_MISC0_BDC_SHIFT   5

#include <xdp_hw.h>

Shift bits for BDC.

◆ XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006

#include <xdp_hw.h>

Component format.

◆ XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0

#include <xdp_hw.h>

Stream's component format is RGB.

◆ XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1

#include <xdp_hw.h>

Shift bits for component format.

◆ XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x5

#include <xdp_hw.h>

Stream's component format is YcbCr 4:2:2.

◆ XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444

#define XDP_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x6

#include <xdp_hw.h>

Stream's component format is YcbCr 4:4:4.

◆ XDP_MAX_NPORTS

#define XDP_MAX_NPORTS   16

#include <xdp_hw.h>

The maximum number of ports connected to a DisplayPort device.

◆ XDp_ReadReg

#define XDp_ReadReg (   BaseAddress,
  RegOffset 
)    XDp_In32((BaseAddress) + (RegOffset))

#include <xdp_hw.h>

This is a low-level function that reads from the specified register.

Parameters
BaseAddressis the base address of the device.
RegOffsetis the register offset to be read from.
Returns
The 32-bit value of the specified register.
Note
C-style signature: u32 XDp_ReadReg(UINTPTR BaseAddress, u32 RegOffset)

Referenced by XDp_IsLaneCountValid().

◆ XDP_RX_NUM_I2C_ENTRIES_PER_PORT

#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT   3

#include <xdp_hw.h>

The number of I2C user- defined entries in the I2C map of each port.

◆ XDp_TxCfgSetRGB

#define XDp_TxCfgSetRGB (   InstancePtr,
  Stream 
)

#include <xdp.h>

Value:
XDp_TxCfgSetColorEncode((InstancePtr), (Stream), \
XVIDC_CSF_RGB, XVIDC_BT_601, XDP_DR_VESA)

The following functions set the color encoding scheme for a given stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to configure the color encoding scheme for.
Returns
XST_SUCCESS.
Note
C-style signatures: u32 XDp_TxCfgSetRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetSRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYonly(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetAdbRGB(XDp *InstancePtr, u8 Stream)

◆ XDp_WriteReg

#define XDp_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    XDp_Out32((BaseAddress) + (RegOffset), (Data))

#include <xdp_hw.h>

This is a low-level function that writes to the specified register.

Parameters
BaseAddressis the base address of the device.
RegOffsetis the register offset to write to.
Datais the 32-bit data to write to the specified register.
Returns
None.
Note
C-style signature: void XDp_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)

Referenced by XDp_IsLaneCountValid().

Typedef Documentation

◆ XDp_IntrHandler

typedef void(* XDp_IntrHandler) (void *InstancePtr)

#include <xdp.h>

Callback type which represents the handler for interrupts.

Parameters
InstancePtris a pointer to the XDp instance.
Note
None.

◆ XDp_TimerHandler

typedef void(* XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds)

#include <xdp.h>

Callback type which represents a custom timer wait handler.

This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.

Parameters
InstancePtris a pointer to the XDp instance.
MicroSecondsis the number of microseconds to be passed to the timer function.
Note
None.

Enumeration Type Documentation

◆ Dp_Rx_HandlerType

#include <xdp.h>

This typedef enumerates the handlers for the the DisplayPort Receiver.

◆ XDp_CoreType

#include <xdp.h>

This typedef enumerates the RX and TX modes of operation for the DisplayPort core.

◆ XDp_DynamicRange

#include <xdp.h>

This typedef enumerates the dynamic ranges available to the DisplayPort core.

◆ XDp_Tx_HandlerType

#include <xdp.h>

This typedef enumerates the handlers for the the DisplayPort Transmitter.

Function Documentation

◆ XDp_CfgInitialize()

void XDp_CfgInitialize ( XDp InstancePtr,
XDp_Config ConfigPtr,
UINTPTR  EffectiveAddr 
)

#include <xdp.c>

This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.

Parameters
InstancePtris a pointer to the XDp instance.
ConfigPtris a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddris the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
Returns
None.
Note
Unexpected errors may occur if the address mapping is changed after this function is invoked.

References XDp_Config::BaseAddr, XDp::Config, and XDp_GetCoreType.

Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().

◆ XDp_Initialize()

u32 XDp_Initialize ( XDp InstancePtr)

#include <xdp.c>

This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the DisplayPort core was successfully initialized.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

Referenced by Dptx_SetupExample().

◆ XDp_InterruptHandler()

void XDp_InterruptHandler ( XDp InstancePtr)

#include <xdp.h>

This function is the interrupt handler for the XDp driver.

When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_IsLaneCountValid()

u8 XDp_IsLaneCountValid ( XDp InstancePtr,
u8  LaneCount 
)

#include <xdp.c>

This function checks the validity of the lane count.

Parameters
InstancePtris a pointer to the XDp instance.
LaneCountis the number of lanes to check if valid.
Returns
  • 1 if specified lane count is valid.
  • 0 otherwise, if the lane count specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.
Note
None.

References XDp_Config::BaseAddr, XDp::Config, XDp_Config::MaxLaneCount, XDp_Config::MaxLinkRate, XDp_Config::MstSupport, XDp_Config::SAxiClkHz, XDP_LANE_COUNT_SET_1, XDP_LANE_COUNT_SET_2, XDP_LANE_COUNT_SET_4, XDp_ReadReg, and XDp_WriteReg.

◆ XDp_IsLinkRateValid()

u8 XDp_IsLinkRateValid ( XDp InstancePtr,
u8  LinkRate 
)

#include <xdp.c>

This function checks the validity of the link rate.

Parameters
InstancePtris a pointer to the XDp instance.
LinkRateis the link rate to check if valid.
Returns
  • 1 if specified link rate is valid.
  • 0 otherwise, if the link rate specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.
Note
None.

References XDp::Config, XDp_Config::MaxLinkRate, XDP_LINK_BW_SET_162GBPS, XDP_LINK_BW_SET_270GBPS, and XDP_LINK_BW_SET_540GBPS.

◆ XDp_LookupConfig()

XDp_Config * XDp_LookupConfig ( u16  DeviceId)

#include <xdp.h>

This function looks for the device configuration based on the unique device ID.

The table XDp_ConfigTable[] contains the configuration information for each device in the system.

Parameters
DeviceIdis the unique device ID of the device being looked up.
Returns
A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
Note
None.

Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().

◆ XDp_SelfTest()

u32 XDp_SelfTest ( XDp InstancePtr)

#include <xdp.h>

This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode.

The sanity test checks whether or not all tested registers hold their default reset values.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

Referenced by Dp_SelfTestExample().

◆ XDp_SetUserTimerHandler()

void XDp_SetUserTimerHandler ( XDp InstancePtr,
XDp_TimerHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.c>

This function installs a custom delay/sleep function to be used by the XDp driver.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
Returns
None.
Note
None.

References XDp::UserTimerPtr, and XDp::UserTimerWaitUs.

◆ XDp_WaitUs()

void XDp_WaitUs ( XDp InstancePtr,
u32  MicroSeconds 
)

#include <xdp.c>

This function is the delay/sleep function for the XDp driver.

For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

Parameters
InstancePtris a pointer to the XDp instance.
MicroSecondsis the number of microseconds to delay/sleep for.
Returns
None.
Note
None.

References XDp::IsReady, and XDp::UserTimerWaitUs.

Variable Documentation

◆ GuidTable

u8 GuidTable[16][XDP_GUID_NBYTES]

#include <xdp_mst.c>

This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function.

◆ XDp_ConfigTable

XDp_Config XDp_ConfigTable[XPAR_XDP_NUM_INSTANCES]

#include <xdp_sinit.c>

A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.