clk_wiz
Xilinx SDK Drivers API Documentation
XClk_Wiz_Config Struct Reference

The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver. More...

Data Fields

u32 DeviceId
 Device Id. More...
 
UINTPTR BaseAddr
 Base address of CLK_WIZ Controller. More...
 
u32 EnableClkMon
 It enables the Clock Monitor. More...
 
u32 EnableUserClkWiz0
 Enable user clk 0. More...
 
u32 EnableUserClkWiz1
 Enable user clk 1. More...
 
u32 EnableUserClkWiz2
 Enable user clk 2. More...
 
u32 EnableUserClkWiz3
 Enable user clk 3. More...
 
double RefClkFreq
 Frequency of Reference Clock. More...
 
double UserClkFreq0
 Hold the user clock frequency0. More...
 
double UserClkFreq1
 Hold the user clock frequency1. More...
 
double UserClkFreq2
 Hold the user clock frequency2. More...
 
double UserClkFreq3
 Hold the user clock frequency3. More...
 
double Precision
 Holds the value of precision. More...
 
u8 EnablePll0
 specify if this user clock is going as input to the PLL/MMCM More...
 
u8 EnablePll1
 specify if this user clock is going as input to the PLL/MMCM More...
 

Detailed Description

The configuration structure for CLK_WIZ Controller This structure passes the hardware building information to the driver.

Field Documentation

◆ BaseAddr

UINTPTR XClk_Wiz_Config::BaseAddr

Base address of CLK_WIZ Controller.

Referenced by Clk_Wiz_Reconfig(), Wait_For_Lock(), and XClk_Wiz_CfgInitialize().

◆ DeviceId

u32 XClk_Wiz_Config::DeviceId

Device Id.

◆ EnableClkMon

u32 XClk_Wiz_Config::EnableClkMon

It enables the Clock Monitor.

◆ EnablePll0

u8 XClk_Wiz_Config::EnablePll0

specify if this user clock is going as input to the PLL/MMCM

◆ EnablePll1

u8 XClk_Wiz_Config::EnablePll1

specify if this user clock is going as input to the PLL/MMCM

◆ EnableUserClkWiz0

u32 XClk_Wiz_Config::EnableUserClkWiz0

Enable user clk 0.

◆ EnableUserClkWiz1

u32 XClk_Wiz_Config::EnableUserClkWiz1

Enable user clk 1.

◆ EnableUserClkWiz2

u32 XClk_Wiz_Config::EnableUserClkWiz2

Enable user clk 2.

◆ EnableUserClkWiz3

u32 XClk_Wiz_Config::EnableUserClkWiz3

Enable user clk 3.

◆ Precision

double XClk_Wiz_Config::Precision

Holds the value of precision.

◆ RefClkFreq

double XClk_Wiz_Config::RefClkFreq

Frequency of Reference Clock.

◆ UserClkFreq0

double XClk_Wiz_Config::UserClkFreq0

Hold the user clock frequency0.

◆ UserClkFreq1

double XClk_Wiz_Config::UserClkFreq1

Hold the user clock frequency1.

◆ UserClkFreq2

double XClk_Wiz_Config::UserClkFreq2

Hold the user clock frequency2.

◆ UserClkFreq3

double XClk_Wiz_Config::UserClkFreq3

Hold the user clock frequency3.