hwicap
Xilinx SDK Drivers API Documentation
xhwicap_i.h File Reference

Macros

#define XHwIcap_Type1Read(Register)
 Generates a Type 1 packet header that reads back the requested Configuration register. More...
 
#define XHwIcap_Type2Read(Register)   ( XHI_TYPE_2_READ | (Register << XHI_REGISTER_SHIFT))
 Generates a Type 2 packet header that reads back the requested Configuration register. More...
 
#define XHwIcap_Type1Write(Register)
 Generates a Type 1 packet header that writes to the requested Configuration register. More...
 
#define XHwIcap_Type2Write(Register)
 Generates a Type 2 packet header that writes to the requested Configuration register. More...
 
#define XHwIcap_SetupFarV5(Top, Block, Row, ColumnAddress, MinorAddress)
 Generates a Type 1 packet header that is written to the Frame Address Register (FAR). More...
 
Configuration Type1/Type2 packet headers masks
#define XHI_TYPE_MASK   0x7
 
#define XHI_REGISTER_MASK   0x1F
 
#define XHI_OP_MASK   0x3
 
#define XHI_WORD_COUNT_MASK_TYPE_1   0x7FF
 
#define XHI_WORD_COUNT_MASK_TYPE_2   0x07FFFFFF
 
#define XHI_TYPE_SHIFT   29
 
#define XHI_REGISTER_SHIFT   13
 
#define XHI_OP_SHIFT   27
 
#define XHI_TYPE_1   1
 
#define XHI_TYPE_2   2
 
#define XHI_OP_WRITE   2
 
#define XHI_OP_READ   1
 
Frame Address Register mask(s)
#define XHI_FAR_BLOCK_MASK   0x7
 
#define XHI_FAR_TOP_BOTTOM_MASK   0x1
 
#define XHI_FAR_ROW_ADDR_MASK   0x1F
 
#define XHI_FAR_COLUMN_ADDR_MASK   0x3FF
 
#define XHI_FAR_MINOR_ADDR_MASK   0x7F
 
#define XHI_FAR_BLOCK_SHIFT   23
 
#define XHI_FAR_TOP_BOTTOM_SHIFT   22
 
#define XHI_FAR_ROW_ADDR_SHIFT   17
 
#define XHI_FAR_COLUMN_ADDR_SHIFT   7
 
#define XHI_FAR_MINOR_ADDR_SHIFT   0
 
#define XHI_FAR_CLB_BLOCK   0
 CLB/IO/CLK Block. More...
 
#define XHI_FAR_BRAM_BLOCK   1
 Block RAM interconnect. More...
 
#define XHI_FAR_CFG_CLB_BLOCK   2
 CFG CLB Block. More...