![]() |
devcfg
Xilinx SDK Drivers API Documentation
|
This file contains a polled mode design example for the Device Configuration Interface.
This example downloads a given bitstream to the FPGA fabric.
BIT_STREAM_LOCATION specifies the memory location of the bitstream. BIT_STREAM_SIZE_WORDS specifies the size of the bitstream in words. User has to define these correctly for this example to work.
MODIFICATION HISTORY:
Ver Who Date Changes
1.00a hvm 11/19/10 First release 1.00a nm 11/26/11 Holding FPGA in reset before download and releasing it after bitstream download. This code is not checking bitstream download errors. 2.00a nm 05/31/12 Updated the notes in the example for CR 660139 to add information that the 2 LSBs of the Source/Destination address when equal to 2�b01 indicate the last DMA command of an overall transfer. Updated the example for CR 660835 so that input length for source/destination to the XDcfg_Transfer APIs is words (32 bit) and not bytes. 2.01a nm 11/21/12 Fixed CR# 688146. Modified the bitstream address. 2.02a nm 01/31/13 Fixed CR# 679335. Removed disabling and enabling AXI interface. Clearing the interrupts before the transfer. Added support for partial reconfiguration. 3.00a kpc 02/20/14 Renamed the DcfgInstance variable name to DcfgInstPtr 3.1 kpc 04/22/14 Fixed CR#780203. Enable the pcap clock if it is not set. ms 04/10/17 Modified filename tag to include the file in doxygen examples. *
Macros | |
#define | SLCR_LOCK 0xF8000004 |
SLCR Write Protection Lock. More... | |
#define | SLCR_UNLOCK 0xF8000008 |
SLCR Write Protection Unlock. More... | |
#define | SLCR_LVL_SHFTR_EN 0xF8000900 |
SLCR Level Shifters Enable. More... | |
#define | SLCR_PCAP_CLK_CTRL XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168 |
SLCR PCAP clock control register address. More... | |
Functions | |
int | XDcfgPolledExample (XDcfg *DcfgInstPtr, u16 DeviceId) |
This function downloads the Non secure bit stream to the FPGA fabric using the Device Configuration Interface. More... | |
int | main (void) |
Main function to call the polled mode example. More... | |
#define SLCR_LOCK 0xF8000004 |
SLCR Write Protection Lock.
#define SLCR_LVL_SHFTR_EN 0xF8000900 |
SLCR Level Shifters Enable.
#define SLCR_PCAP_CLK_CTRL XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168 |
SLCR PCAP clock control register address.
#define SLCR_UNLOCK 0xF8000008 |
SLCR Write Protection Unlock.
int main | ( | void | ) |
Main function to call the polled mode example.
None. |
int XDcfgPolledExample | ( | XDcfg * | DcfgInstPtr, |
u16 | DeviceId | ||
) |
This function downloads the Non secure bit stream to the FPGA fabric using the Device Configuration Interface.
DcfgInstPtr | is a pointer to the instance of XDcfg driver. |
DeviceId | is the unique device id of the device. |