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iicps
Xilinx SDK Drivers API Documentation
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Data Structures | |
struct | XIicPs_Config |
This typedef contains configuration information for the device. More... | |
struct | XIicPs |
The XIicPs driver instance data. More... | |
Macros | |
#define | XIicPs_ReadReg(BaseAddress, RegOffset) XIicPs_In32((BaseAddress) + (u32)(RegOffset)) |
Read an IIC register. More... | |
#define | XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) |
Write an IIC register. More... | |
#define | XIicPs_ReadIER(BaseAddress) XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) |
Read the interrupt enable register. More... | |
#define | XIicPs_EnableInterrupts(BaseAddress, IntrMask) XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) |
Write to the interrupt enable register. More... | |
#define | XIicPs_DisableAllInterrupts(BaseAddress) |
Disable all interrupts. More... | |
#define | XIicPs_DisableInterrupts(BaseAddress, IntrMask) |
Disable selected interrupts. More... | |
Functions | |
void | XIicPs_ResetHw (u32 BaseAddress) |
This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specifc registers the i2cps reset squence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values. More... | |
Variables | |
u16 | XIicPs_Config::DeviceId |
Unique ID of device. More... | |
u32 | XIicPs_Config::BaseAddress |
Base address of the device. More... | |
u32 | XIicPs_Config::InputClockHz |
Input clock frequency. More... | |
XIicPs_Config | XIicPs_ConfigTable [XPAR_XIICPS_NUM_INSTANCES] |
This table contains configuration information for each IIC device in the system. More... | |
XIicPs_Config | XIicPs_ConfigTable [XPAR_XIICPS_NUM_INSTANCES] |
This table contains configuration information for each IIC device in the system. More... | |
Configuration options | |
The following options may be specified or retrieved for the device and enable/disable additional features of the IIC. Each of the options are bit fields, so more than one may be specified. | |
#define | XIICPS_7_BIT_ADDR_OPTION 0x01U |
7-bit address mode More... | |
#define | XIICPS_10_BIT_ADDR_OPTION 0x02U |
10-bit address mode More... | |
#define | XIICPS_SLAVE_MON_OPTION 0x04U |
Slave monitor mode. More... | |
#define | XIICPS_REP_START_OPTION 0x08U |
Repeated Start. More... | |
Callback events | |
These constants specify the handler events that are passed to an application event handler from the driver. These constants are bit masks such that more than one event can be passed to the handler. | |
#define | XIICPS_EVENT_COMPLETE_SEND 0x0001U |
Transmit Complete Event. More... | |
#define | XIICPS_EVENT_COMPLETE_RECV 0x0002U |
Receive Complete Event. More... | |
#define | XIICPS_EVENT_TIME_OUT 0x0004U |
Transfer timed out. More... | |
#define | XIICPS_EVENT_ERROR 0x0008U |
Receive error. More... | |
#define | XIICPS_EVENT_ARB_LOST 0x0010U |
Arbitration lost. More... | |
#define | XIICPS_EVENT_NACK 0x0020U |
NACK Received. More... | |
#define | XIICPS_EVENT_SLAVE_RDY 0x0040U |
Slave ready. More... | |
#define | XIICPS_EVENT_RX_OVR 0x0080U |
RX overflow. More... | |
#define | XIICPS_EVENT_TX_OVR 0x0100U |
TX overflow. More... | |
#define | XIICPS_EVENT_RX_UNF 0x0200U |
RX underflow. More... | |
Role constants | |
These constants are used to pass into the device setup routines to set up the device according to transfer direction. | |
typedef void(* | XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent) |
The handler data type allows the user to define a callback function to respond to interrupt events in the system. More... | |
s32 | XIicPs_CfgInitialize (XIicPs *InstancePtr, XIicPs_Config *ConfigPtr, u32 EffectiveAddr) |
Initializes a specific XIicPs instance such that the driver is ready to use. More... | |
s32 | XIicPs_BusIsBusy (XIicPs *InstancePtr) |
Check whether the I2C bus is busy. More... | |
void | XIicPs_Abort (XIicPs *InstancePtr) |
Aborts a transfer in progress by resetting the FIFOs. More... | |
void | XIicPs_Reset (XIicPs *InstancePtr) |
Resets the IIC device. More... | |
s32 | TransmitFifoFill (XIicPs *InstancePtr) |
Put more data into the transmit FIFO, number of bytes is ether expected number of bytes for this transfer or available space in FIFO, which ever is less. More... | |
XIicPs_Config * | XIicPs_LookupConfig (u16 DeviceId) |
Looks up the device configuration based on the unique device ID. More... | |
void | XIicPs_SetStatusHandler (XIicPs *InstancePtr, void *CallBackRef, XIicPs_IntrHandler FunctionPtr) |
This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More... | |
void | XIicPs_MasterSend (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr) |
This function initiates an interrupt-driven send in master mode. More... | |
void | XIicPs_MasterRecv (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr) |
This function initiates an interrupt-driven receive in master mode. More... | |
s32 | XIicPs_MasterSendPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr) |
This function initiates a polled mode send in master mode. More... | |
s32 | XIicPs_MasterRecvPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr) |
This function initiates a polled mode receive in master mode. More... | |
void | XIicPs_EnableSlaveMonitor (XIicPs *InstancePtr, u16 SlaveAddr) |
This function enables the slave monitor mode. More... | |
void | XIicPs_DisableSlaveMonitor (XIicPs *InstancePtr) |
This function disables slave monitor mode. More... | |
void | XIicPs_MasterInterruptHandler (XIicPs *InstancePtr) |
The interrupt handler for the master mode. More... | |
void | XIicPs_SetupSlave (XIicPs *InstancePtr, u16 SlaveAddr) |
This function sets up the device to be a slave. More... | |
void | XIicPs_SlaveSend (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) |
This function setup a slave interrupt-driven send. More... | |
void | XIicPs_SlaveRecv (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) |
This function setup a slave interrupt-driven receive. More... | |
s32 | XIicPs_SlaveSendPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) |
This function sends a buffer in polled mode as a slave. More... | |
s32 | XIicPs_SlaveRecvPolled (XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) |
This function receives a buffer in polled mode as a slave. More... | |
void | XIicPs_SlaveInterruptHandler (XIicPs *InstancePtr) |
The interrupt handler for slave mode. More... | |
s32 | XIicPs_SelfTest (XIicPs *InstancePtr) |
Runs a self-test on the driver/device. More... | |
s32 | XIicPs_SetOptions (XIicPs *InstancePtr, u32 Options) |
This function sets the options for the IIC device driver. More... | |
s32 | XIicPs_ClearOptions (XIicPs *InstancePtr, u32 Options) |
This function clears the options for the IIC device driver. More... | |
u32 | XIicPs_GetOptions (XIicPs *InstancePtr) |
This function gets the options for the IIC device. More... | |
s32 | XIicPs_SetSClk (XIicPs *InstancePtr, u32 FsclHz) |
This function sets the serial clock rate for the IIC device. More... | |
u32 | XIicPs_GetSClk (XIicPs *InstancePtr) |
This function gets the serial clock rate for the IIC device. More... | |
#define | SENDING_ROLE 1 |
Transfer direction is sending. More... | |
#define | RECVING_ROLE 0 |
Transfer direction is receiving. More... | |
#define | XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U) |
#define | XIicPs_SendByte(InstancePtr) |
#define | XIicPs_RecvByte(InstancePtr) |
Register Map | |
#define | XIICPS_CR_OFFSET 0x00U |
32-bit Control More... | |
#define | XIICPS_SR_OFFSET 0x04U |
Status. More... | |
#define | XIICPS_ADDR_OFFSET 0x08U |
IIC Address. More... | |
#define | XIICPS_DATA_OFFSET 0x0CU |
IIC FIFO Data. More... | |
#define | XIICPS_ISR_OFFSET 0x10U |
Interrupt Status. More... | |
#define | XIICPS_TRANS_SIZE_OFFSET 0x14U |
Transfer Size. More... | |
#define | XIICPS_SLV_PAUSE_OFFSET 0x18U |
Slave monitor pause. More... | |
#define | XIICPS_TIME_OUT_OFFSET 0x1CU |
Time Out. More... | |
#define | XIICPS_IMR_OFFSET 0x20U |
Interrupt Enabled Mask. More... | |
#define | XIICPS_IER_OFFSET 0x24U |
Interrupt Enable. More... | |
#define | XIICPS_IDR_OFFSET 0x28U |
Interrupt Disable. More... | |
Control Register | |
This register contains various control bits that affects the operation of the IIC controller. Read/Write. | |
#define | XIICPS_CR_DIV_A_MASK 0x0000C000U |
Clock Divisor A. More... | |
#define | XIICPS_CR_DIV_A_SHIFT 14U |
Clock Divisor A shift. More... | |
#define | XIICPS_DIV_A_MAX 4U |
Maximum value of Divisor A. More... | |
#define | XIICPS_CR_DIV_B_MASK 0x00003F00U |
Clock Divisor B. More... | |
#define | XIICPS_CR_DIV_B_SHIFT 8U |
Clock Divisor B shift. More... | |
#define | XIICPS_CR_CLR_FIFO_MASK 0x00000040U |
Clear FIFO, auto clears. More... | |
#define | XIICPS_CR_SLVMON_MASK 0x00000020U |
Slave monitor mode. More... | |
#define | XIICPS_CR_HOLD_MASK 0x00000010U |
Hold bus 1=Hold scl, 0=terminate transfer. More... | |
#define | XIICPS_CR_ACKEN_MASK 0x00000008U |
Enable TX of ACK when Master receiver. More... | |
#define | XIICPS_CR_NEA_MASK 0x00000004U |
Addressing Mode 1=7 bit, 0=10 bit. More... | |
#define | XIICPS_CR_MS_MASK 0x00000002U |
Master mode bit 1=Master, 0=Slave. More... | |
#define | XIICPS_CR_RD_WR_MASK 0x00000001U |
Read or Write Master transfer 0=Transmitter, 1=Receiver. More... | |
#define | XIICPS_CR_RESET_VALUE 0U |
Reset value of the Control register. More... | |
IIC Status Register | |
This register is used to indicate status of the IIC controller. Read only | |
#define | XIICPS_SR_BA_MASK 0x00000100U |
Bus Active Mask. More... | |
#define | XIICPS_SR_RXOVF_MASK 0x00000080U |
Receiver Overflow Mask. More... | |
#define | XIICPS_SR_TXDV_MASK 0x00000040U |
Transmit Data Valid Mask. More... | |
#define | XIICPS_SR_RXDV_MASK 0x00000020U |
Receiver Data Valid Mask. More... | |
#define | XIICPS_SR_RXRW_MASK 0x00000008U |
Receive read/write Mask. More... | |
IIC Address Register | |
Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. A write access to this register always initiates a transfer if the IIC is in master mode. Read/Write | |
#define | XIICPS_ADDR_MASK 0x000003FF |
IIC Address Mask. More... | |
IIC Data Register | |
When written to, the data register sets data to transmit. When read from, the data register reads the last received byte of data. Read/Write | |
#define | XIICPS_DATA_MASK 0x000000FF |
IIC Data Mask. More... | |
IIC Interrupt Registers | |
This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered
IIC Interrupt Enable Register This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Disable Register This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Mask Register This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register | |
#define | XIICPS_IXR_ARB_LOST_MASK 0x00000200U |
Arbitration Lost Interrupt mask. More... | |
#define | XIICPS_IXR_RX_UNF_MASK 0x00000080U |
FIFO Recieve Underflow Interrupt mask. More... | |
#define | XIICPS_IXR_TX_OVR_MASK 0x00000040U |
Transmit Overflow Interrupt mask. More... | |
#define | XIICPS_IXR_RX_OVR_MASK 0x00000020U |
Receive Overflow Interrupt mask. More... | |
#define | XIICPS_IXR_SLV_RDY_MASK 0x00000010U |
Monitored Slave Ready Interrupt mask. More... | |
#define | XIICPS_IXR_TO_MASK 0x00000008U |
Transfer Time Out Interrupt mask. More... | |
#define | XIICPS_IXR_NACK_MASK 0x00000004U |
NACK Interrupt mask. More... | |
#define | XIICPS_IXR_DATA_MASK 0x00000002U |
Data Interrupt mask. More... | |
#define | XIICPS_IXR_COMP_MASK 0x00000001U |
Transfer Complete Interrupt mask. More... | |
#define | XIICPS_IXR_DEFAULT_MASK 0x000002FFU |
Default ISR Mask. More... | |
#define | XIICPS_IXR_ALL_INTR_MASK 0x000002FFU |
All ISR Mask. More... | |
IIC Transfer Size Register | |
The register's meaning varies according to the operating mode as follows:
This register is cleared if CLR_FIFO bit in the control register is set. Read/Write | |
#define | XIICPS_TRANS_SIZE_MASK 0x0000003F |
IIC Transfer Size Mask. More... | |
#define | XIICPS_FIFO_DEPTH 16 |
Number of bytes in the FIFO. More... | |
#define | XIICPS_DATA_INTR_DEPTH 14 |
Number of bytes at DATA intr. More... | |
IIC Slave Monitor Pause Register | |
This register is associated with the slave monitor mode of the I2C interface. It is meaningful only when the module is in master mode and bit SLVMON in the control register is set. This register defines the pause interval between consecutive attempts to address the slave once a write to an I2C address register is done by the host. It represents the number of sclk cycles minus one between two attempts. The reset value of the register is 0, which results in the master repeatedly trying to access the slave immediately after unsuccessful attempt. Read/Write | |
#define | XIICPS_SLV_PAUSE_MASK 0x0000000F |
Slave monitor pause mask. More... | |
IIC Time Out Register | |
The value of time out register represents the time out interval in number of sclk cycles minus one. When the accessed slave holds the sclk line low for longer than the time out period, thus prohibiting the I2C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set. The reset value of the register is 0x1f. Read/Write | |
#define | XIICPS_TIME_OUT_MASK 0x000000FFU |
IIC Time Out mask. More... | |
#define | XIICPS_TO_RESET_VALUE 0x000000FFU |
IIC Time Out reset value. More... | |
#define RECVING_ROLE 0 |
#include <xiicps.h>
Transfer direction is receiving.
#define SENDING_ROLE 1 |
#include <xiicps.h>
Transfer direction is sending.
#define XIICPS_10_BIT_ADDR_OPTION 0x02U |
#include <xiicps.h>
10-bit address mode
#define XIICPS_7_BIT_ADDR_OPTION 0x01U |
#include <xiicps.h>
7-bit address mode
#define XIICPS_ADDR_MASK 0x000003FF |
#include <xiicps_hw.h>
IIC Address Mask.
Referenced by XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), and XIicPs_SetupSlave().
#define XIICPS_ADDR_OFFSET 0x08U |
#define XIICPS_CR_ACKEN_MASK 0x00000008U |
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U |
#include <xiicps_hw.h>
Clear FIFO, auto clears.
Referenced by XIicPs_Abort(), XIicPs_EnableSlaveMonitor(), and XIicPs_ResetHw().
#define XIICPS_CR_DIV_A_MASK 0x0000C000U |
#define XIICPS_CR_DIV_A_SHIFT 14U |
#define XIICPS_CR_DIV_B_MASK 0x00003F00U |
#define XIICPS_CR_DIV_B_SHIFT 8U |
#define XIICPS_CR_HOLD_MASK 0x00000010U |
#include <xiicps_hw.h>
Hold bus 1=Hold scl, 0=terminate transfer.
Referenced by XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), and XIicPs_ResetHw().
#define XIICPS_CR_MS_MASK 0x00000002U |
#include <xiicps_hw.h>
Master mode bit 1=Master, 0=Slave.
Referenced by XIicPs_EnableSlaveMonitor(), and XIicPs_ResetHw().
#define XIICPS_CR_NEA_MASK 0x00000004U |
#include <xiicps_hw.h>
Addressing Mode 1=7 bit, 0=10 bit.
Referenced by XIicPs_EnableSlaveMonitor().
#define XIICPS_CR_OFFSET 0x00U |
#include <xiicps_hw.h>
32-bit Control
Referenced by XIicPs_Abort(), XIicPs_ClearOptions(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_GetOptions(), XIicPs_GetSClk(), XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), XIicPs_Reset(), XIicPs_ResetHw(), XIicPs_SelfTest(), and XIicPs_SetOptions().
#define XIICPS_CR_RD_WR_MASK 0x00000001U |
#include <xiicps_hw.h>
Read or Write Master transfer 0=Transmitter, 1=Receiver.
Referenced by XIicPs_EnableSlaveMonitor().
#define XIICPS_CR_RESET_VALUE 0U |
#include <xiicps_hw.h>
Reset value of the Control register.
Referenced by XIicPs_Abort(), XIicPs_Reset(), and XIicPs_SelfTest().
#define XIICPS_CR_SLVMON_MASK 0x00000020U |
#include <xiicps_hw.h>
Slave monitor mode.
Referenced by XIicPs_DisableSlaveMonitor(), and XIicPs_EnableSlaveMonitor().
#define XIICPS_DATA_INTR_DEPTH 14 |
#include <xiicps_hw.h>
Number of bytes at DATA intr.
#define XIICPS_DATA_MASK 0x000000FF |
#include <xiicps_hw.h>
IIC Data Mask.
#define XIICPS_DATA_OFFSET 0x0CU |
#include <xiicps_hw.h>
IIC FIFO Data.
#define XIicPs_DisableAllInterrupts | ( | BaseAddress | ) |
#include <xiicps_hw.h>
Disable all interrupts.
BaseAddress | contains the base address of the device. |
#define XIicPs_DisableInterrupts | ( | BaseAddress, | |
IntrMask | |||
) |
#include <xiicps_hw.h>
Disable selected interrupts.
BaseAddress | contains the base address of the device. |
IntrMask | is the interrupts to be disabled. |
Referenced by XIicPs_DisableSlaveMonitor().
#define XIICPS_DIV_A_MAX 4U |
#include <xiicps_hw.h>
Maximum value of Divisor A.
#define XIicPs_EnableInterrupts | ( | BaseAddress, | |
IntrMask | |||
) | XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) |
#include <xiicps_hw.h>
Write to the interrupt enable register.
BaseAddress | contains the base address of the device. |
IntrMask | is the interrupts to be enabled. |
Referenced by XIicPs_EnableSlaveMonitor(), XIicPs_SlaveRecv(), and XIicPs_SlaveSend().
#define XIICPS_EVENT_ARB_LOST 0x0010U |
#include <xiicps.h>
Arbitration lost.
#define XIICPS_EVENT_COMPLETE_RECV 0x0002U |
#define XIICPS_EVENT_COMPLETE_SEND 0x0001U |
#define XIICPS_EVENT_ERROR 0x0008U |
#include <xiicps.h>
Receive error.
#define XIICPS_EVENT_NACK 0x0020U |
#include <xiicps.h>
NACK Received.
#define XIICPS_EVENT_RX_OVR 0x0080U |
#include <xiicps.h>
RX overflow.
#define XIICPS_EVENT_RX_UNF 0x0200U |
#include <xiicps.h>
RX underflow.
#define XIICPS_EVENT_SLAVE_RDY 0x0040U |
#include <xiicps.h>
Slave ready.
#define XIICPS_EVENT_TIME_OUT 0x0004U |
#include <xiicps.h>
Transfer timed out.
#define XIICPS_EVENT_TX_OVR 0x0100U |
#include <xiicps.h>
TX overflow.
#define XIICPS_FIFO_DEPTH 16 |
#include <xiicps_hw.h>
Number of bytes in the FIFO.
Referenced by TransmitFifoFill(), XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), and XIicPs_SlaveSendPolled().
#define XIICPS_IDR_OFFSET 0x28U |
#include <xiicps_hw.h>
Interrupt Disable.
Referenced by XIicPs_Abort(), XIicPs_Reset(), and XIicPs_ResetHw().
#define XIICPS_IER_OFFSET 0x24U |
#define XIICPS_IMR_OFFSET 0x20U |
#include <xiicps_hw.h>
Interrupt Enabled Mask.
Referenced by XIicPs_Abort(), XIicPs_SelfTest(), and XIicPs_SlaveInterruptHandler().
#define XIICPS_ISR_OFFSET 0x10U |
#include <xiicps_hw.h>
Interrupt Status.
Referenced by XIicPs_Abort(), XIicPs_ResetHw(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU |
#include <xiicps_hw.h>
All ISR Mask.
Referenced by XIicPs_Abort(), XIicPs_Reset(), XIicPs_ResetHw(), and XIicPs_SelfTest().
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U |
#include <xiicps_hw.h>
Arbitration Lost Interrupt mask.
#define XIICPS_IXR_COMP_MASK 0x00000001U |
#include <xiicps_hw.h>
Transfer Complete Interrupt mask.
Referenced by XIicPs_SlaveRecv(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSend().
#define XIICPS_IXR_DATA_MASK 0x00000002U |
#include <xiicps_hw.h>
Data Interrupt mask.
Referenced by XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecv(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSend().
#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU |
#include <xiicps_hw.h>
Default ISR Mask.
#define XIICPS_IXR_NACK_MASK 0x00000004U |
#include <xiicps_hw.h>
NACK Interrupt mask.
Referenced by XIicPs_SlaveRecv(), and XIicPs_SlaveSend().
#define XIICPS_IXR_RX_OVR_MASK 0x00000020U |
#define XIICPS_IXR_RX_UNF_MASK 0x00000080U |
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U |
#include <xiicps_hw.h>
Monitored Slave Ready Interrupt mask.
Referenced by XIicPs_DisableSlaveMonitor(), and XIicPs_EnableSlaveMonitor().
#define XIICPS_IXR_TO_MASK 0x00000008U |
#include <xiicps_hw.h>
Transfer Time Out Interrupt mask.
Referenced by XIicPs_SlaveRecv(), and XIicPs_SlaveSend().
#define XIICPS_IXR_TX_OVR_MASK 0x00000040U |
#define XIicPs_ReadIER | ( | BaseAddress | ) | XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) |
#include <xiicps_hw.h>
Read the interrupt enable register.
BaseAddress | contains the base address of the device. |
#define XIicPs_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XIicPs_In32((BaseAddress) + (u32)(RegOffset)) |
#include <xiicps_hw.h>
Read an IIC register.
BaseAddress | contains the base address of the device. |
RegOffset | contains the offset from the 1st register of the device to select the specific register. |
Referenced by TransmitFifoFill(), XIicPs_Abort(), XIicPs_BusIsBusy(), XIicPs_ClearOptions(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_GetOptions(), XIicPs_GetSClk(), XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), XIicPs_ResetHw(), XIicPs_SelfTest(), XIicPs_SetOptions(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().
#define XIICPS_REP_START_OPTION 0x08U |
#define XIICPS_SLAVE_MON_OPTION 0x04U |
#include <xiicps.h>
Slave monitor mode.
#define XIICPS_SLV_PAUSE_MASK 0x0000000F |
#include <xiicps_hw.h>
Slave monitor pause mask.
#define XIICPS_SLV_PAUSE_OFFSET 0x18U |
#include <xiicps_hw.h>
Slave monitor pause.
Referenced by XIicPs_EnableSlaveMonitor(), and XIicPs_SelfTest().
#define XIICPS_SR_BA_MASK 0x00000100U |
#define XIICPS_SR_OFFSET 0x04U |
#include <xiicps_hw.h>
Status.
Referenced by XIicPs_BusIsBusy(), XIicPs_ResetHw(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().
#define XIICPS_SR_RXDV_MASK 0x00000020U |
#include <xiicps_hw.h>
Receiver Data Valid Mask.
Referenced by XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().
#define XIICPS_SR_RXOVF_MASK 0x00000080U |
#include <xiicps_hw.h>
Receiver Overflow Mask.
#define XIICPS_SR_RXRW_MASK 0x00000008U |
#define XIICPS_SR_TXDV_MASK 0x00000040U |
#include <xiicps_hw.h>
Transmit Data Valid Mask.
#define XIICPS_TIME_OUT_MASK 0x000000FFU |
#include <xiicps_hw.h>
IIC Time Out mask.
#define XIICPS_TIME_OUT_OFFSET 0x1CU |
#define XIICPS_TO_RESET_VALUE 0x000000FFU |
#include <xiicps_hw.h>
IIC Time Out reset value.
Referenced by XIicPs_Reset(), and XIicPs_ResetHw().
#define XIICPS_TRANS_SIZE_MASK 0x0000003F |
#include <xiicps_hw.h>
IIC Transfer Size Mask.
#define XIICPS_TRANS_SIZE_OFFSET 0x14U |
#include <xiicps_hw.h>
Transfer Size.
Referenced by TransmitFifoFill(), XIicPs_EnableSlaveMonitor(), and XIicPs_ResetHw().
#define XIicPs_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
RegisterValue | |||
) | XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) |
#include <xiicps_hw.h>
Write an IIC register.
BaseAddress | contains the base address of the device. |
RegOffset | contains the offset from the 1st register of the device to select the specific register. |
RegisterValue | is the value to be written to the register. |
Referenced by XIicPs_Abort(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), XIicPs_Reset(), XIicPs_ResetHw(), XIicPs_SelfTest(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecvPolled(), and XIicPs_SlaveSendPolled().
typedef void(* XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent) |
#include <xiicps.h>
The handler data type allows the user to define a callback function to respond to interrupt events in the system.
This function is executed in interrupt context, so amount of processing should be minimized.
CallBackRef | is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer. |
StatusEvent | indicates one or more status events that occurred. |
s32 TransmitFifoFill | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.c>
Put more data into the transmit FIFO, number of bytes is ether expected number of bytes for this transfer or available space in FIFO, which ever is less.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIICPS_FIFO_DEPTH, XIicPs_ReadReg, and XIICPS_TRANS_SIZE_OFFSET.
Referenced by XIicPs_SlaveInterruptHandler().
void XIicPs_Abort | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.c>
Aborts a transfer in progress by resetting the FIFOs.
The byte counts are cleared.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IDR_OFFSET, XIICPS_IER_OFFSET, XIICPS_IMR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.
Referenced by XIicPs_Reset().
s32 XIicPs_BusIsBusy | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.c>
Check whether the I2C bus is busy.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIicPs_ReadReg, XIICPS_SR_BA_MASK, and XIICPS_SR_OFFSET.
s32 XIicPs_CfgInitialize | ( | XIicPs * | InstancePtr, |
XIicPs_Config * | ConfigPtr, | ||
u32 | EffectiveAddr | ||
) |
#include <xiicps.c>
Initializes a specific XIicPs instance such that the driver is ready to use.
The state of the device after initialization is:
InstancePtr | is a pointer to the XIicPs instance. |
ConfigPtr | is a reference to a structure containing information about a specific IIC device. This function initializes an InstancePtr object for a specific device specified by the contents of Config. |
EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->BaseAddress for this parameter, passing the physical address instead. |
References XIicPs_Config::BaseAddress, XIicPs_Config::DeviceId, and XIicPs_Config::InputClockHz.
Referenced by IicPsMasterPolledExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().
s32 XIicPs_ClearOptions | ( | XIicPs * | InstancePtr, |
u32 | Options | ||
) |
#include <xiicps.h>
This function clears the options for the IIC device driver.
The options control how the device behaves relative to the IIC bus. The device must be idle rather than busy transferring data before setting these device options.
InstancePtr | is a pointer to the XIicPs instance. |
Options | contains the specified options to be cleared. This is a bit mask where a 1 means to turn the option off. One or more bit values may be contained in the mask. See the bit definitions named XIICPS_*_OPTION in xiicps.h. |
References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIicPs_ReadReg, and XIICPS_REP_START_OPTION.
void XIicPs_DisableSlaveMonitor | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
This function disables slave monitor mode.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIICPS_CR_SLVMON_MASK, XIicPs_DisableInterrupts, XIICPS_IXR_SLV_RDY_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.
void XIicPs_EnableSlaveMonitor | ( | XIicPs * | InstancePtr, |
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function enables the slave monitor mode.
It enables slave monitor in the control register and enables slave ready interrupt. It then does an address transfer to slave. Interrupt handler will signal the caller if slave responds to the address transfer.
InstancePtr | is a pointer to the XIicPs instance. |
SlaveAddr | is the address of the slave we want to contact. |
References XIicPs_Config::BaseAddress, XIICPS_ADDR_OFFSET, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_MS_MASK, XIICPS_CR_NEA_MASK, XIICPS_CR_OFFSET, XIICPS_CR_RD_WR_MASK, XIICPS_CR_SLVMON_MASK, XIicPs_EnableInterrupts, XIICPS_IXR_SLV_RDY_MASK, XIicPs_ReadReg, XIICPS_SLV_PAUSE_OFFSET, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.
u32 XIicPs_GetOptions | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
This function gets the options for the IIC device.
The options control how the device behaves relative to the IIC bus.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, and XIicPs_ReadReg.
u32 XIicPs_GetSClk | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
This function gets the serial clock rate for the IIC device.
The device must be idle rather than busy transferring data before setting these device options.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIicPs_Config::InputClockHz, XIICPS_CR_DIV_A_MASK, XIICPS_CR_DIV_A_SHIFT, XIICPS_CR_DIV_B_MASK, XIICPS_CR_DIV_B_SHIFT, XIICPS_CR_OFFSET, and XIicPs_ReadReg.
XIicPs_Config * XIicPs_LookupConfig | ( | u16 | DeviceId | ) |
#include <xiicps.h>
Looks up the device configuration based on the unique device ID.
A table contains the configuration info for each device in the system.
DeviceId | contains the ID of the device to look up the configuration for. |
Referenced by IicPsMasterPolledExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().
void XIicPs_MasterInterruptHandler | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
The interrupt handler for the master mode.
It does the protocol handling for the interrupt-driven transfers.
Completion events and errors are signaled to upper layer for proper handling.
The interrupts that are handled are:
COMP If the Master is transmitting data and there is more data to be sent then the data is written to the FIFO. If there is no more data to be transmitted then a completion event is signalled to the upper layer by calling the callback handler.
If the Master is receiving data then the data is read from the FIFO and the Master has to request for more data (if there is more data to receive). If all the data has been received then a completion event is signalled to the upper layer by calling the callback handler. It is an error if the amount of received data is more than expected.
InstancePtr | is a pointer to the XIicPs instance. |
void XIicPs_MasterRecv | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount, | ||
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function initiates an interrupt-driven receive in master mode.
It sets the transfer size register so the slave can send data to us. The rest of the work is managed by interrupt handler.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the receive buffer. |
ByteCount | is the number of bytes to be received. |
SlaveAddr | is the address of the slave we are receiving from. |
References XIicPs_Config::BaseAddress, XIICPS_ADDR_MASK, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIICPS_FIFO_DEPTH, XIicPs_ReadReg, and XIicPs_WriteReg.
s32 XIicPs_MasterRecvPolled | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount, | ||
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function initiates a polled mode receive in master mode.
It repeatedly sets the transfer size register so the slave can send data to us. It polls the data register for data to come in. If slave fails to send us data, it fails with time out.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the receive buffer. |
ByteCount | is the number of bytes to be received. |
SlaveAddr | is the address of the slave we are receiving from. |
void XIicPs_MasterSend | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount, | ||
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function initiates an interrupt-driven send in master mode.
It tries to send the first FIFO-full of data, then lets the interrupt handler to handle the rest of the data if there is any.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the send buffer. |
ByteCount | is the number of bytes to be sent. |
SlaveAddr | is the address of the slave we are sending to. |
s32 XIicPs_MasterSendPolled | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount, | ||
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function initiates a polled mode send in master mode.
It sends data to the FIFO and waits for the slave to pick them up. If slave fails to remove data from FIFO, the send fails with time out.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the send buffer. |
ByteCount | is the number of bytes to be sent. |
SlaveAddr | is the address of the slave we are sending to. |
References XIicPs_Config::BaseAddress, XIICPS_ADDR_MASK, XIICPS_CR_HOLD_MASK, XIICPS_CR_OFFSET, XIICPS_FIFO_DEPTH, XIicPs_ReadReg, and XIicPs_WriteReg.
Referenced by EepromWriteData().
void XIicPs_Reset | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.c>
Resets the IIC device.
Reset must only be called after the driver has been initialized. The configuration of the device after reset is the same as its configuration after initialization. Any data transfer that is in progress is aborted.
The upper layer software is responsible for re-configuring (if necessary) and reenabling interrupts for the IIC device after the reset.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIicPs_Abort(), XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE, and XIicPs_WriteReg.
Referenced by XIicPs_SelfTest().
void XIicPs_ResetHw | ( | u32 | BaseAddress | ) |
#include <xiicps_hw.c>
This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specifc registers the i2cps reset squence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values.
BaseAddress | of the interface |
References XIICPS_CR_ACKEN_MASK, XIICPS_CR_CLR_FIFO_MASK, XIICPS_CR_HOLD_MASK, XIICPS_CR_MS_MASK, XIICPS_CR_OFFSET, XIICPS_IDR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, XIICPS_SR_OFFSET, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE, XIICPS_TRANS_SIZE_OFFSET, and XIicPs_WriteReg.
s32 XIicPs_SelfTest | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
Runs a self-test on the driver/device.
The self-test is destructive in that a reset of the device is performed in order to check the reset values of the registers and to get the device into a known state.
Upon successful return from the self-test, the device is reset.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIICPS_CR_RESET_VALUE, XIICPS_IMR_OFFSET, XIICPS_IXR_ALL_INTR_MASK, XIicPs_ReadReg, XIicPs_Reset(), XIICPS_SLV_PAUSE_OFFSET, and XIicPs_WriteReg.
Referenced by IicPsMasterPolledExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), and IicPsSlavePolledExample().
s32 XIicPs_SetOptions | ( | XIicPs * | InstancePtr, |
u32 | Options | ||
) |
#include <xiicps.h>
This function sets the options for the IIC device driver.
The options control how the device behaves relative to the IIC bus. The device must be idle rather than busy transferring data before setting these device options.
InstancePtr | is a pointer to the XIicPs instance. |
Options | contains the specified options to be set. This is a bit mask where a 1 means to turn the option on. One or more bit values may be contained in the mask. See the bit definitions named XIICPS_*_OPTION in xiicps.h. |
References XIicPs_Config::BaseAddress, XIICPS_CR_OFFSET, XIicPs_ReadReg, and XIICPS_REP_START_OPTION.
s32 XIicPs_SetSClk | ( | XIicPs * | InstancePtr, |
u32 | FsclHz | ||
) |
#include <xiicps.h>
This function sets the serial clock rate for the IIC device.
The device must be idle rather than busy transferring data before setting these device options.
The data rate is set by values in the control register. The formula for determining the correct register values is: Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) See the hardware data sheet for a full explanation of setting the serial clock rate.
InstancePtr | is a pointer to the XIicPs instance. |
FsclHz | is the clock frequency in Hz. The two most common clock rates are 100KHz and 400KHz. |
Referenced by IicPsMasterPolledExample().
void XIicPs_SetStatusHandler | ( | XIicPs * | InstancePtr, |
void * | CallBackRef, | ||
XIicPs_IntrHandler | FunctionPtr | ||
) |
#include <xiicps.h>
This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.
The handler executes in an interrupt context, so the amount of processing should be minimized
Refer to the xiicps.h file for a list of the Callback events. The events are defined to start with XIICPS_EVENT_*.
InstancePtr | is a pointer to the XIicPs instance. |
CallBackRef | is the upper layer callback reference passed back when the callback function is invoked. |
FunctionPtr | is the pointer to the callback function. |
The handler is called within interrupt context, so it should finish its work quickly.
void XIicPs_SetupSlave | ( | XIicPs * | InstancePtr, |
u16 | SlaveAddr | ||
) |
#include <xiicps.h>
This function sets up the device to be a slave.
InstancePtr | is a pointer to the XIicPs instance. |
SlaveAddr | is the address of the slave we are receiving from. |
References XIicPs_Config::BaseAddress, and XIICPS_ADDR_MASK.
Referenced by IicPsSlavePolledExample().
void XIicPs_SlaveInterruptHandler | ( | XIicPs * | InstancePtr | ) |
#include <xiicps.h>
The interrupt handler for slave mode.
It does the protocol handling for the interrupt-driven transfers.
Completion events and errors are signaled to upper layer for proper handling.
The interrupts that are handled are:
DATA If the instance is sending, it means that the master wants to read more data from us. Send more data, and check whether we are done with this send.
If the instance is receiving, it means that the master has writen more data to us. Receive more data, and check whether we are done with with this receive.
COMP This marks that stop sequence has been sent from the master, transfer is about to terminate. However, for receiving, the master may have written us some data, so receive that first.
It is an error if the amount of transfered data is less than expected.
InstancePtr | is a pointer to the XIicPs instance. |
References XIicPs_Config::BaseAddress, TransmitFifoFill(), XIICPS_EVENT_COMPLETE_SEND, XIICPS_IMR_OFFSET, XIICPS_ISR_OFFSET, XIICPS_IXR_DATA_MASK, XIicPs_ReadReg, and XIicPs_WriteReg.
void XIicPs_SlaveRecv | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount | ||
) |
#include <xiicps.h>
This function setup a slave interrupt-driven receive.
Data processing for the receive is handled by the interrupt handler.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the receive buffer. |
ByteCount | is the number of bytes to be received. |
References XIicPs_Config::BaseAddress, XIicPs_EnableInterrupts, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_RX_OVR_MASK, XIICPS_IXR_RX_UNF_MASK, and XIICPS_IXR_TO_MASK.
s32 XIicPs_SlaveRecvPolled | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount | ||
) |
#include <xiicps.h>
This function receives a buffer in polled mode as a slave.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the receive buffer. |
ByteCount | is the number of bytes to be received. |
References XIicPs_Config::BaseAddress, XIICPS_ISR_OFFSET, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIicPs_ReadReg, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, and XIicPs_WriteReg.
void XIicPs_SlaveSend | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount | ||
) |
#include <xiicps.h>
This function setup a slave interrupt-driven send.
It set the repeated start for the device is the tranfer size is larger than FIFO depth. Data processing for the send is initiated by the interrupt handler.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the send buffer. |
ByteCount | is the number of bytes to be sent. |
References XIicPs_Config::BaseAddress, XIicPs_EnableInterrupts, XIICPS_IXR_COMP_MASK, XIICPS_IXR_DATA_MASK, XIICPS_IXR_NACK_MASK, XIICPS_IXR_TO_MASK, and XIICPS_IXR_TX_OVR_MASK.
s32 XIicPs_SlaveSendPolled | ( | XIicPs * | InstancePtr, |
u8 * | MsgPtr, | ||
s32 | ByteCount | ||
) |
#include <xiicps.h>
This function sends a buffer in polled mode as a slave.
InstancePtr | is a pointer to the XIicPs instance. |
MsgPtr | is the pointer to the send buffer. |
ByteCount | is the number of bytes to be sent. |
References XIicPs_Config::BaseAddress, XIICPS_FIFO_DEPTH, XIICPS_ISR_OFFSET, XIicPs_ReadReg, XIICPS_SR_OFFSET, XIICPS_SR_RXDV_MASK, XIICPS_SR_RXRW_MASK, and XIicPs_WriteReg.
u32 XIicPs_Config::BaseAddress |
Base address of the device.
Referenced by IicPsMasterPolledExample(), IicPsSelfTestExample(), IicPsSlaveIntrExample(), IicPsSlavePolledExample(), TransmitFifoFill(), XIicPs_Abort(), XIicPs_BusIsBusy(), XIicPs_CfgInitialize(), XIicPs_ClearOptions(), XIicPs_DisableSlaveMonitor(), XIicPs_EnableSlaveMonitor(), XIicPs_GetOptions(), XIicPs_GetSClk(), XIicPs_MasterRecv(), XIicPs_MasterSendPolled(), XIicPs_Reset(), XIicPs_SelfTest(), XIicPs_SetOptions(), XIicPs_SetupSlave(), XIicPs_SlaveInterruptHandler(), XIicPs_SlaveRecv(), XIicPs_SlaveRecvPolled(), XIicPs_SlaveSend(), and XIicPs_SlaveSendPolled().
u16 XIicPs_Config::DeviceId |
Unique ID of device.
Referenced by XIicPs_CfgInitialize().
u32 XIicPs_Config::InputClockHz |
Input clock frequency.
Referenced by XIicPs_CfgInitialize(), and XIicPs_GetSClk().
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] |
#include <xiicps_sinit.c>
This table contains configuration information for each IIC device in the system.
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] |
#include <xiicps_g.c>
This table contains configuration information for each IIC device in the system.