devcfg
Xilinx SDK Drivers API Documentation
Devcfg_v3_3

Data Structures

struct  XDcfg_Config
 This typedef contains configuration information for the device. More...
 
struct  XDcfg
 The XDcfg driver instance data. More...
 

Macros

#define XDcfg_Unlock(InstancePtr)
 Unlock the Device Config Interface block. More...
 
#define XDcfg_GetPsVersion(InstancePtr)
 Get the version number of the PS from the Miscellaneous Control Register. More...
 
#define XDcfg_ReadMultiBootConfig(InstancePtr)
 Read the multiboot config register value. More...
 
#define XDcfg_SelectIcapInterface(InstancePtr)
 Selects ICAP interface for reconfiguration after the initial configuration of the PL. More...
 
#define XDcfg_SelectPcapInterface(InstancePtr)
 Selects PCAP interface for reconfiguration after the initial configuration of the PL. More...
 
#define XDCFG_DMA_INVALID_ADDRESS   0xFFFFFFFF
 Invalid DMA address. More...
 
#define XDCFG_UNLOCK_DATA   0x757BDF0D
 First APB access data. More...
 
#define XDCFG_BASE_ADDRESS   0xF8007000
 Device Config base address. More...
 
#define XDCFG_CONFIG_RESET_VALUE   0x508
 Config reg reset value. More...
 
#define XDcfg_ReadReg(BaseAddr, RegOffset)   Xil_In32((BaseAddr) + (RegOffset))
 Read the given register. More...
 
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)   Xil_Out32((BaseAddr) + (RegOffset), (Data))
 Write to the given register. More...
 

Typedefs

typedef void(* XDcfg_IntrHandler) (void *CallBackRef, u32 Status)
 The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...
 

Functions

int XDcfg_CfgInitialize (XDcfg *InstancePtr, XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
 Initialize the Device Config Interface driver. More...
 
void XDcfg_EnablePCAP (XDcfg *InstancePtr)
 The functions enables the PCAP interface by setting the PCAP mode bit in the control register. More...
 
void XDcfg_DisablePCAP (XDcfg *InstancePtr)
 The functions disables the PCAP interface by clearing the PCAP mode bit in the control register. More...
 
void XDcfg_SetControlRegister (XDcfg *InstancePtr, u32 Mask)
 The function sets the contents of the Control Register. More...
 
void XDcfg_ClearControlRegister (XDcfg *InstancePtr, u32 Mask)
 The function Clears the specified bit positions of the Control Register. More...
 
u32 XDcfg_GetControlRegister (XDcfg *InstancePtr)
 The function reads the contents of the Control Register. More...
 
void XDcfg_SetLockRegister (XDcfg *InstancePtr, u32 Data)
 The function sets the contents of the Lock Register. More...
 
u32 XDcfg_GetLockRegister (XDcfg *InstancePtr)
 The function reads the contents of the Lock Register. More...
 
void XDcfg_SetConfigRegister (XDcfg *InstancePtr, u32 Data)
 The function sets the contents of the Configuration Register with the given value. More...
 
u32 XDcfg_GetConfigRegister (XDcfg *InstancePtr)
 The function reads the contents of the Configuration Register with the given value. More...
 
void XDcfg_SetStatusRegister (XDcfg *InstancePtr, u32 Data)
 The function sets the contents of the Status Register. More...
 
u32 XDcfg_GetStatusRegister (XDcfg *InstancePtr)
 The function reads the contents of the Status Register. More...
 
void XDcfg_SetRomShadowRegister (XDcfg *InstancePtr, u32 Data)
 The function sets the contents of the ROM Shadow Control Register. More...
 
u32 XDcfg_GetSoftwareIdRegister (XDcfg *InstancePtr)
 The function reads the contents of the Software ID Register. More...
 
void XDcfg_SetMiscControlRegister (XDcfg *InstancePtr, u32 Mask)
 The function sets the bit mask for the feature in Miscellaneous Control Register. More...
 
u32 XDcfg_GetMiscControlRegister (XDcfg *InstancePtr)
 The function reads the contents of the Miscellaneous Control Register. More...
 
u32 XDcfg_IsDmaBusy (XDcfg *InstancePtr)
 This function checks if DMA command queue is full. More...
 
void XDcfg_InitiateDma (XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, u32 SrcWordLength, u32 DestWordLength)
 This function initiates the DMA transfer. More...
 
u32 XDcfg_Transfer (XDcfg *InstancePtr, void *SourcePtr, u32 SrcWordLength, void *DestPtr, u32 DestWordLength, u32 TransferType)
 This function starts the DMA transfer. More...
 
XDcfg_ConfigXDcfg_LookupConfig (u16 DeviceId)
 Lookup the device configuration based on the unique device ID. More...
 
int XDcfg_SelfTest (XDcfg *InstancePtr)
 Run a self-test on the Device Configuration Interface. More...
 
void XDcfg_IntrEnable (XDcfg *InstancePtr, u32 Mask)
 This function enables the specified interrupts in the device. More...
 
void XDcfg_IntrDisable (XDcfg *InstancePtr, u32 Mask)
 This function disables the specified interrupts in the device. More...
 
u32 XDcfg_IntrGetEnabled (XDcfg *InstancePtr)
 This function returns the enabled interrupts read from the Interrupt Mask Register. More...
 
u32 XDcfg_IntrGetStatus (XDcfg *InstancePtr)
 This function returns the interrupt status read from Interrupt Status Register. More...
 
void XDcfg_IntrClear (XDcfg *InstancePtr, u32 Mask)
 This function clears the specified interrupts in the Interrupt Status Register. More...
 
void XDcfg_InterruptHandler (XDcfg *InstancePtr)
 The interrupt handler for the Device Config Interface. More...
 
void XDcfg_SetHandler (XDcfg *InstancePtr, void *CallBackFunc, void *CallBackRef)
 This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention. More...
 
void XDcfg_ResetHw (u32 BaseAddr)
 This function perform the reset sequence to the given devcfg interface by configuring the appropriate control bits in the devcfg specifc registers the devcfg reset squence involves the following steps Disable all the interuupts Clear the status Update relevant config registers with reset values Disbale the looopback mode and pcap rate enable. More...
 

Variables

XDcfg_Config XDcfg_ConfigTable [1]
 This table contains configuration information for each Device Config Interface instance in the system. More...
 

Register Map

Offsets of registers from the start of the device

#define XDCFG_CTRL_OFFSET   0x00
 Control Register. More...
 
#define XDCFG_LOCK_OFFSET   0x04
 Lock Register. More...
 
#define XDCFG_CFG_OFFSET   0x08
 Configuration Register. More...
 
#define XDCFG_INT_STS_OFFSET   0x0C
 Interrupt Status Register. More...
 
#define XDCFG_INT_MASK_OFFSET   0x10
 Interrupt Mask Register. More...
 
#define XDCFG_STATUS_OFFSET   0x14
 Status Register. More...
 
#define XDCFG_DMA_SRC_ADDR_OFFSET   0x18
 DMA Source Address Register. More...
 
#define XDCFG_DMA_DEST_ADDR_OFFSET   0x1C
 DMA Destination Address Reg. More...
 
#define XDCFG_DMA_SRC_LEN_OFFSET   0x20
 DMA Source Transfer Length. More...
 
#define XDCFG_DMA_DEST_LEN_OFFSET   0x24
 DMA Destination Transfer. More...
 
#define XDCFG_ROM_SHADOW_OFFSET   0x28
 DMA ROM Shadow Register. More...
 
#define XDCFG_MULTIBOOT_ADDR_OFFSET   0x2C
 Multi BootAddress Pointer. More...
 
#define XDCFG_SW_ID_OFFSET   0x30
 Software ID Register. More...
 
#define XDCFG_UNLOCK_OFFSET   0x34
 Unlock Register. More...
 
#define XDCFG_MCTRL_OFFSET   0x80
 Miscellaneous Control Reg. More...
 

Control Register Bit definitions

#define XDCFG_CTRL_FORCE_RST_MASK   0x80000000
 Force into Secure Reset. More...
 
#define XDCFG_CTRL_PCFG_PROG_B_MASK   0x40000000
 Program signal to Reset FPGA. More...
 
#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK   0x20000000
 Control PL POR timer. More...
 
#define XDCFG_CTRL_PCAP_PR_MASK   0x08000000
 Enable PCAP for PR. More...
 
#define XDCFG_CTRL_PCAP_MODE_MASK   0x04000000
 Enable PCAP. More...
 
#define XDCFG_CTRL_PCAP_RATE_EN_MASK   0x02000000
 Enable PCAP send data to FPGA every 4 PCAP cycles. More...
 
#define XDCFG_CTRL_MULTIBOOT_EN_MASK   0x01000000
 Multiboot Enable. More...
 
#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK   0x00800000
 JTAG Chain Disable. More...
 
#define XDCFG_CTRL_USER_MODE_MASK   0x00008000
 User Mode Mask. More...
 
#define XDCFG_CTRL_PCFG_AES_FUSE_MASK   0x00001000
 AES key source. More...
 
#define XDCFG_CTRL_PCFG_AES_EN_MASK   0x00000E00
 AES Enable Mask. More...
 
#define XDCFG_CTRL_SEU_EN_MASK   0x00000100
 SEU Enable Mask. More...
 
#define XDCFG_CTRL_SEC_EN_MASK   0x00000080
 Secure/Non Secure Status mask. More...
 
#define XDCFG_CTRL_SPNIDEN_MASK   0x00000040
 Secure Non Invasive Debug Enable. More...
 
#define XDCFG_CTRL_SPIDEN_MASK   0x00000020
 Secure Invasive Debug Enable. More...
 
#define XDCFG_CTRL_NIDEN_MASK   0x00000010
 Non-Invasive Debug Enable. More...
 
#define XDCFG_CTRL_DBGEN_MASK   0x00000008
 Invasive Debug Enable. More...
 
#define XDCFG_CTRL_DAP_EN_MASK   0x00000007
 DAP Enable Mask. More...
 

Lock register bit definitions

#define XDCFG_LOCK_AES_EFUSE_MASK   0x00000010
 Lock AES Efuse bit. More...
 
#define XDCFG_LOCK_AES_EN_MASK   0x00000008
 Lock AES_EN update. More...
 
#define XDCFG_LOCK_SEU_MASK   0x00000004
 Lock SEU_En update. More...
 
#define XDCFG_LOCK_SEC_MASK   0x00000002
 Lock SEC_EN and USER_MODE. More...
 
#define XDCFG_LOCK_DBG_MASK   0x00000001
 This bit locks security config including: DAP_En, DBGEN,, NIDEN, SPNIEN. More...
 

Config Register Bit definitions

#define XDCFG_CFG_RFIFO_TH_MASK   0x00000C00
 Read FIFO Threshold Mask. More...
 
#define XDCFG_CFG_WFIFO_TH_MASK   0x00000300
 Write FIFO Threshold Mask. More...
 
#define XDCFG_CFG_RCLK_EDGE_MASK   0x00000080
 Read data active clock edge. More...
 
#define XDCFG_CFG_WCLK_EDGE_MASK   0x00000040
 Write data active clock edge. More...
 
#define XDCFG_CFG_DISABLE_SRC_INC_MASK   0x00000020
 Disable Source address increment mask. More...
 
#define XDCFG_CFG_DISABLE_DST_INC_MASK   0x00000010
 Disable Destination address increment mask. More...
 

Interrupt Status/Mask Register Bit definitions

#define XDCFG_IXR_PSS_GTS_USR_B_MASK   0x80000000
 Tri-state IO during HIZ. More...
 
#define XDCFG_IXR_PSS_FST_CFG_B_MASK   0x40000000
 First configuration done. More...
 
#define XDCFG_IXR_PSS_GPWRDWN_B_MASK   0x20000000
 Global power down. More...
 
#define XDCFG_IXR_PSS_GTS_CFG_B_MASK   0x10000000
 Tri-state IO during configuration. More...
 
#define XDCFG_IXR_PSS_CFG_RESET_B_MASK   0x08000000
 PL configuration reset. More...
 
#define XDCFG_IXR_AXI_WTO_MASK   0x00800000
 AXI Write Address or Data or response timeout. More...
 
#define XDCFG_IXR_AXI_WERR_MASK   0x00400000
 AXI Write response error. More...
 
#define XDCFG_IXR_AXI_RTO_MASK   0x00200000
 AXI Read Address or response timeout. More...
 
#define XDCFG_IXR_AXI_RERR_MASK   0x00100000
 AXI Read response error. More...
 
#define XDCFG_IXR_RX_FIFO_OV_MASK   0x00040000
 Rx FIFO Overflow. More...
 
#define XDCFG_IXR_WR_FIFO_LVL_MASK   0x00020000
 Tx FIFO less than threshold. More...
 
#define XDCFG_IXR_RD_FIFO_LVL_MASK   0x00010000
 Rx FIFO greater than threshold. More...
 
#define XDCFG_IXR_DMA_CMD_ERR_MASK   0x00008000
 Illegal DMA command. More...
 
#define XDCFG_IXR_DMA_Q_OV_MASK   0x00004000
 DMA command queue overflow. More...
 
#define XDCFG_IXR_DMA_DONE_MASK   0x00002000
 DMA Command Done. More...
 
#define XDCFG_IXR_D_P_DONE_MASK   0x00001000
 DMA and PCAP transfers Done. More...
 
#define XDCFG_IXR_P2D_LEN_ERR_MASK   0x00000800
 PCAP to DMA transfer length error. More...
 
#define XDCFG_IXR_PCFG_HMAC_ERR_MASK   0x00000040
 HMAC error mask. More...
 
#define XDCFG_IXR_PCFG_SEU_ERR_MASK   0x00000020
 SEU Error mask. More...
 
#define XDCFG_IXR_PCFG_POR_B_MASK   0x00000010
 FPGA POR mask. More...
 
#define XDCFG_IXR_PCFG_CFG_RST_MASK   0x00000008
 FPGA Reset mask. More...
 
#define XDCFG_IXR_PCFG_DONE_MASK   0x00000004
 Done Signal Mask. More...
 
#define XDCFG_IXR_PCFG_INIT_PE_MASK   0x00000002
 Detect Positive edge of Init Signal. More...
 
#define XDCFG_IXR_PCFG_INIT_NE_MASK   0x00000001
 Detect Negative edge of Init Signal. More...
 
#define XDCFG_IXR_ERROR_FLAGS_MASK
 
#define XDCFG_IXR_ALL_MASK   0x00F7F8EF
 

Status Register Bit definitions

#define XDCFG_STATUS_DMA_CMD_Q_F_MASK   0x80000000
 DMA command Queue full. More...
 
#define XDCFG_STATUS_DMA_CMD_Q_E_MASK   0x40000000
 DMA command Queue empty. More...
 
#define XDCFG_STATUS_DMA_DONE_CNT_MASK   0x30000000
 Number of completed DMA transfers. More...
 
#define XDCFG_STATUS_RX_FIFO_LVL_MASK   0x01F000000
 Rx FIFO level. More...
 
#define XDCFG_STATUS_TX_FIFO_LVL_MASK   0x0007F000
 Tx FIFO level. More...
 
#define XDCFG_STATUS_PSS_GTS_USR_B   0x00000800
 Tri-state IO during HIZ. More...
 
#define XDCFG_STATUS_PSS_FST_CFG_B   0x00000400
 First PL config done. More...
 
#define XDCFG_STATUS_PSS_GPWRDWN_B   0x00000200
 Global power down. More...
 
#define XDCFG_STATUS_PSS_GTS_CFG_B   0x00000100
 Tri-state IO during config. More...
 
#define XDCFG_STATUS_SECURE_RST_MASK   0x00000080
 Secure Reset POR Status. More...
 
#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK   0x00000040
 Illegal APB access. More...
 
#define XDCFG_STATUS_PSS_CFG_RESET_B   0x00000020
 PL config reset status. More...
 
#define XDCFG_STATUS_PCFG_INIT_MASK   0x00000010
 FPGA Init Status. More...
 
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK   0x00000008
 BBRAM key disable. More...
 
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK   0x00000004
 Efuse Security Enable Status. More...
 
#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK   0x00000002
 EFuse JTAG Disable status. More...
 

DMA Source/Destination Transfer Length Register Bit definitions

#define XDCFG_DMA_LEN_MASK   0x7FFFFFF
 Length Mask. More...
 

Miscellaneous Control Register Bit definitions

#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK   0xF0000000
 PS Version Mask. More...
 
#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT   28
 PS Version Shift. More...
 
#define XDCFG_MCTRL_PCAP_LPBK_MASK   0x00000010
 PCAP loopback mask. More...
 

FIFO Threshold Bit definitions

#define XDCFG_CFG_FIFO_QUARTER   0x0
 Quarter empty. More...
 
#define XDCFG_CFG_FIFO_HALF   0x1
 Half empty. More...
 
#define XDCFG_CFG_FIFO_3QUARTER   0x2
 3/4 empty More...
 
#define XDCFG_CFG_FIFO_EMPTY   0x4
 Empty. More...
 

Macro Definition Documentation

◆ XDCFG_BASE_ADDRESS

#define XDCFG_BASE_ADDRESS   0xF8007000

#include <xdevcfg_hw.h>

Device Config base address.

◆ XDCFG_CFG_DISABLE_DST_INC_MASK

#define XDCFG_CFG_DISABLE_DST_INC_MASK   0x00000010

#include <xdevcfg_hw.h>

Disable Destination address increment mask.

◆ XDCFG_CFG_DISABLE_SRC_INC_MASK

#define XDCFG_CFG_DISABLE_SRC_INC_MASK   0x00000020

#include <xdevcfg_hw.h>

Disable Source address increment mask.

◆ XDCFG_CFG_FIFO_3QUARTER

#define XDCFG_CFG_FIFO_3QUARTER   0x2

#include <xdevcfg_hw.h>

3/4 empty

◆ XDCFG_CFG_FIFO_EMPTY

#define XDCFG_CFG_FIFO_EMPTY   0x4

#include <xdevcfg_hw.h>

Empty.

◆ XDCFG_CFG_FIFO_HALF

#define XDCFG_CFG_FIFO_HALF   0x1

#include <xdevcfg_hw.h>

Half empty.

◆ XDCFG_CFG_FIFO_QUARTER

#define XDCFG_CFG_FIFO_QUARTER   0x0

#include <xdevcfg_hw.h>

Quarter empty.

◆ XDCFG_CFG_OFFSET

#define XDCFG_CFG_OFFSET   0x08

#include <xdevcfg_hw.h>

Configuration Register.

Referenced by XDcfg_GetConfigRegister(), and XDcfg_SetConfigRegister().

◆ XDCFG_CFG_RCLK_EDGE_MASK

#define XDCFG_CFG_RCLK_EDGE_MASK   0x00000080

#include <xdevcfg_hw.h>

Read data active clock edge.

◆ XDCFG_CFG_RFIFO_TH_MASK

#define XDCFG_CFG_RFIFO_TH_MASK   0x00000C00

#include <xdevcfg_hw.h>

Read FIFO Threshold Mask.

◆ XDCFG_CFG_WCLK_EDGE_MASK

#define XDCFG_CFG_WCLK_EDGE_MASK   0x00000040

#include <xdevcfg_hw.h>

Write data active clock edge.

◆ XDCFG_CFG_WFIFO_TH_MASK

#define XDCFG_CFG_WFIFO_TH_MASK   0x00000300

#include <xdevcfg_hw.h>

Write FIFO Threshold Mask.

◆ XDCFG_CONFIG_RESET_VALUE

#define XDCFG_CONFIG_RESET_VALUE   0x508

#include <xdevcfg_hw.h>

Config reg reset value.

◆ XDCFG_CTRL_DAP_EN_MASK

#define XDCFG_CTRL_DAP_EN_MASK   0x00000007

#include <xdevcfg_hw.h>

DAP Enable Mask.

◆ XDCFG_CTRL_DBGEN_MASK

#define XDCFG_CTRL_DBGEN_MASK   0x00000008

#include <xdevcfg_hw.h>

Invasive Debug Enable.

◆ XDCFG_CTRL_FORCE_RST_MASK

#define XDCFG_CTRL_FORCE_RST_MASK   0x80000000

#include <xdevcfg_hw.h>

Force into Secure Reset.

◆ XDCFG_CTRL_JTAG_CHAIN_DIS_MASK

#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK   0x00800000

#include <xdevcfg_hw.h>

JTAG Chain Disable.

◆ XDCFG_CTRL_MULTIBOOT_EN_MASK

#define XDCFG_CTRL_MULTIBOOT_EN_MASK   0x01000000

#include <xdevcfg_hw.h>

Multiboot Enable.

◆ XDCFG_CTRL_NIDEN_MASK

#define XDCFG_CTRL_NIDEN_MASK   0x00000010

#include <xdevcfg_hw.h>

Non-Invasive Debug Enable.

Referenced by XDcfg_SelfTest().

◆ XDCFG_CTRL_OFFSET

#define XDCFG_CTRL_OFFSET   0x00

◆ XDCFG_CTRL_PCAP_MODE_MASK

#define XDCFG_CTRL_PCAP_MODE_MASK   0x04000000

#include <xdevcfg_hw.h>

Enable PCAP.

Referenced by XDcfg_DisablePCAP(), and XDcfg_EnablePCAP().

◆ XDCFG_CTRL_PCAP_PR_MASK

#define XDCFG_CTRL_PCAP_PR_MASK   0x08000000

#include <xdevcfg_hw.h>

Enable PCAP for PR.

◆ XDCFG_CTRL_PCAP_RATE_EN_MASK

#define XDCFG_CTRL_PCAP_RATE_EN_MASK   0x02000000

#include <xdevcfg_hw.h>

Enable PCAP send data to FPGA every 4 PCAP cycles.

◆ XDCFG_CTRL_PCFG_AES_EN_MASK

#define XDCFG_CTRL_PCFG_AES_EN_MASK   0x00000E00

#include <xdevcfg_hw.h>

AES Enable Mask.

◆ XDCFG_CTRL_PCFG_AES_FUSE_MASK

#define XDCFG_CTRL_PCFG_AES_FUSE_MASK   0x00001000

#include <xdevcfg_hw.h>

AES key source.

◆ XDCFG_CTRL_PCFG_POR_CNT_4K_MASK

#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK   0x20000000

#include <xdevcfg_hw.h>

Control PL POR timer.

◆ XDCFG_CTRL_PCFG_PROG_B_MASK

#define XDCFG_CTRL_PCFG_PROG_B_MASK   0x40000000

#include <xdevcfg_hw.h>

Program signal to Reset FPGA.

◆ XDCFG_CTRL_SEC_EN_MASK

#define XDCFG_CTRL_SEC_EN_MASK   0x00000080

#include <xdevcfg_hw.h>

Secure/Non Secure Status mask.

◆ XDCFG_CTRL_SEU_EN_MASK

#define XDCFG_CTRL_SEU_EN_MASK   0x00000100

#include <xdevcfg_hw.h>

SEU Enable Mask.

◆ XDCFG_CTRL_SPIDEN_MASK

#define XDCFG_CTRL_SPIDEN_MASK   0x00000020

#include <xdevcfg_hw.h>

Secure Invasive Debug Enable.

◆ XDCFG_CTRL_SPNIDEN_MASK

#define XDCFG_CTRL_SPNIDEN_MASK   0x00000040

#include <xdevcfg_hw.h>

Secure Non Invasive Debug Enable.

◆ XDCFG_CTRL_USER_MODE_MASK

#define XDCFG_CTRL_USER_MODE_MASK   0x00008000

#include <xdevcfg_hw.h>

User Mode Mask.

◆ XDCFG_DMA_DEST_ADDR_OFFSET

#define XDCFG_DMA_DEST_ADDR_OFFSET   0x1C

#include <xdevcfg_hw.h>

DMA Destination Address Reg.

Referenced by XDcfg_InitiateDma().

◆ XDCFG_DMA_DEST_LEN_OFFSET

#define XDCFG_DMA_DEST_LEN_OFFSET   0x24

#include <xdevcfg_hw.h>

DMA Destination Transfer.

Referenced by XDcfg_InitiateDma().

◆ XDCFG_DMA_INVALID_ADDRESS

#define XDCFG_DMA_INVALID_ADDRESS   0xFFFFFFFF

#include <xdevcfg_hw.h>

Invalid DMA address.

◆ XDCFG_DMA_LEN_MASK

#define XDCFG_DMA_LEN_MASK   0x7FFFFFF

#include <xdevcfg_hw.h>

Length Mask.

◆ XDCFG_DMA_SRC_ADDR_OFFSET

#define XDCFG_DMA_SRC_ADDR_OFFSET   0x18

#include <xdevcfg_hw.h>

DMA Source Address Register.

Referenced by XDcfg_InitiateDma().

◆ XDCFG_DMA_SRC_LEN_OFFSET

#define XDCFG_DMA_SRC_LEN_OFFSET   0x20

#include <xdevcfg_hw.h>

DMA Source Transfer Length.

Referenced by XDcfg_InitiateDma().

◆ XDcfg_GetPsVersion

#define XDcfg_GetPsVersion (   InstancePtr)

#include <xdevcfg.h>

Value:
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK
PS Version Mask.
Definition: xdevcfg_hw.h:412
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:456
#define XDCFG_MCTRL_OFFSET
Miscellaneous Control Reg.
Definition: xdevcfg_hw.h:91

Get the version number of the PS from the Miscellaneous Control Register.

Parameters
InstancePtris a pointer to the instance of XDcfg driver.
Returns
Version of the PS.
Note
C-style signature: void XDcfg_GetPsVersion(XDcfg* InstancePtr)

◆ XDCFG_INT_MASK_OFFSET

#define XDCFG_INT_MASK_OFFSET   0x10

#include <xdevcfg_hw.h>

Interrupt Mask Register.

Referenced by XDcfg_IntrDisable(), XDcfg_IntrEnable(), XDcfg_IntrGetEnabled(), and XDcfg_ResetHw().

◆ XDCFG_INT_STS_OFFSET

#define XDCFG_INT_STS_OFFSET   0x0C

#include <xdevcfg_hw.h>

Interrupt Status Register.

Referenced by XDcfg_InterruptHandler(), XDcfg_IntrClear(), and XDcfg_IntrGetStatus().

◆ XDCFG_IXR_AXI_RERR_MASK

#define XDCFG_IXR_AXI_RERR_MASK   0x00100000

#include <xdevcfg_hw.h>

AXI Read response error.

◆ XDCFG_IXR_AXI_RTO_MASK

#define XDCFG_IXR_AXI_RTO_MASK   0x00200000

#include <xdevcfg_hw.h>

AXI Read Address or response timeout.

◆ XDCFG_IXR_AXI_WERR_MASK

#define XDCFG_IXR_AXI_WERR_MASK   0x00400000

#include <xdevcfg_hw.h>

AXI Write response error.

◆ XDCFG_IXR_AXI_WTO_MASK

#define XDCFG_IXR_AXI_WTO_MASK   0x00800000

#include <xdevcfg_hw.h>

AXI Write Address or Data or response timeout.

◆ XDCFG_IXR_D_P_DONE_MASK

#define XDCFG_IXR_D_P_DONE_MASK   0x00001000

#include <xdevcfg_hw.h>

DMA and PCAP transfers Done.

Referenced by XDcfg_GetConfigReg().

◆ XDCFG_IXR_DMA_CMD_ERR_MASK

#define XDCFG_IXR_DMA_CMD_ERR_MASK   0x00008000

#include <xdevcfg_hw.h>

Illegal DMA command.

◆ XDCFG_IXR_DMA_DONE_MASK

#define XDCFG_IXR_DMA_DONE_MASK   0x00002000

#include <xdevcfg_hw.h>

DMA Command Done.

Referenced by XDcfg_GetConfigReg().

◆ XDCFG_IXR_DMA_Q_OV_MASK

#define XDCFG_IXR_DMA_Q_OV_MASK   0x00004000

#include <xdevcfg_hw.h>

DMA command queue overflow.

◆ XDCFG_IXR_P2D_LEN_ERR_MASK

#define XDCFG_IXR_P2D_LEN_ERR_MASK   0x00000800

#include <xdevcfg_hw.h>

PCAP to DMA transfer length error.

◆ XDCFG_IXR_PCFG_CFG_RST_MASK

#define XDCFG_IXR_PCFG_CFG_RST_MASK   0x00000008

#include <xdevcfg_hw.h>

FPGA Reset mask.

◆ XDCFG_IXR_PCFG_DONE_MASK

#define XDCFG_IXR_PCFG_DONE_MASK   0x00000004

#include <xdevcfg_hw.h>

Done Signal Mask.

Referenced by XDcfg_GetConfigReg().

◆ XDCFG_IXR_PCFG_HMAC_ERR_MASK

#define XDCFG_IXR_PCFG_HMAC_ERR_MASK   0x00000040

#include <xdevcfg_hw.h>

HMAC error mask.

◆ XDCFG_IXR_PCFG_INIT_NE_MASK

#define XDCFG_IXR_PCFG_INIT_NE_MASK   0x00000001

#include <xdevcfg_hw.h>

Detect Negative edge of Init Signal.

◆ XDCFG_IXR_PCFG_INIT_PE_MASK

#define XDCFG_IXR_PCFG_INIT_PE_MASK   0x00000002

#include <xdevcfg_hw.h>

Detect Positive edge of Init Signal.

◆ XDCFG_IXR_PCFG_POR_B_MASK

#define XDCFG_IXR_PCFG_POR_B_MASK   0x00000010

#include <xdevcfg_hw.h>

FPGA POR mask.

◆ XDCFG_IXR_PCFG_SEU_ERR_MASK

#define XDCFG_IXR_PCFG_SEU_ERR_MASK   0x00000020

#include <xdevcfg_hw.h>

SEU Error mask.

◆ XDCFG_IXR_PSS_CFG_RESET_B_MASK

#define XDCFG_IXR_PSS_CFG_RESET_B_MASK   0x08000000

#include <xdevcfg_hw.h>

PL configuration reset.

◆ XDCFG_IXR_PSS_FST_CFG_B_MASK

#define XDCFG_IXR_PSS_FST_CFG_B_MASK   0x40000000

#include <xdevcfg_hw.h>

First configuration done.

◆ XDCFG_IXR_PSS_GPWRDWN_B_MASK

#define XDCFG_IXR_PSS_GPWRDWN_B_MASK   0x20000000

#include <xdevcfg_hw.h>

Global power down.

◆ XDCFG_IXR_PSS_GTS_CFG_B_MASK

#define XDCFG_IXR_PSS_GTS_CFG_B_MASK   0x10000000

#include <xdevcfg_hw.h>

Tri-state IO during configuration.

◆ XDCFG_IXR_PSS_GTS_USR_B_MASK

#define XDCFG_IXR_PSS_GTS_USR_B_MASK   0x80000000

#include <xdevcfg_hw.h>

Tri-state IO during HIZ.

◆ XDCFG_IXR_RD_FIFO_LVL_MASK

#define XDCFG_IXR_RD_FIFO_LVL_MASK   0x00010000

#include <xdevcfg_hw.h>

Rx FIFO greater than threshold.

◆ XDCFG_IXR_RX_FIFO_OV_MASK

#define XDCFG_IXR_RX_FIFO_OV_MASK   0x00040000

#include <xdevcfg_hw.h>

Rx FIFO Overflow.

◆ XDCFG_IXR_WR_FIFO_LVL_MASK

#define XDCFG_IXR_WR_FIFO_LVL_MASK   0x00020000

#include <xdevcfg_hw.h>

Tx FIFO less than threshold.

◆ XDCFG_LOCK_AES_EFUSE_MASK

#define XDCFG_LOCK_AES_EFUSE_MASK   0x00000010

#include <xdevcfg_hw.h>

Lock AES Efuse bit.

◆ XDCFG_LOCK_AES_EN_MASK

#define XDCFG_LOCK_AES_EN_MASK   0x00000008

#include <xdevcfg_hw.h>

Lock AES_EN update.

◆ XDCFG_LOCK_DBG_MASK

#define XDCFG_LOCK_DBG_MASK   0x00000001

#include <xdevcfg_hw.h>

This bit locks security config including: DAP_En, DBGEN,, NIDEN, SPNIEN.

◆ XDCFG_LOCK_OFFSET

#define XDCFG_LOCK_OFFSET   0x04

#include <xdevcfg_hw.h>

Lock Register.

Referenced by XDcfg_GetLockRegister(), and XDcfg_SetLockRegister().

◆ XDCFG_LOCK_SEC_MASK

#define XDCFG_LOCK_SEC_MASK   0x00000002

#include <xdevcfg_hw.h>

Lock SEC_EN and USER_MODE.

◆ XDCFG_LOCK_SEU_MASK

#define XDCFG_LOCK_SEU_MASK   0x00000004

#include <xdevcfg_hw.h>

Lock SEU_En update.

◆ XDCFG_MCTRL_OFFSET

#define XDCFG_MCTRL_OFFSET   0x80

#include <xdevcfg_hw.h>

Miscellaneous Control Reg.

Referenced by XDcfg_GetMiscControlRegister(), and XDcfg_SetMiscControlRegister().

◆ XDCFG_MCTRL_PCAP_LPBK_MASK

#define XDCFG_MCTRL_PCAP_LPBK_MASK   0x00000010

#include <xdevcfg_hw.h>

PCAP loopback mask.

◆ XDCFG_MCTRL_PCAP_PS_VERSION_MASK

#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK   0xF0000000

#include <xdevcfg_hw.h>

PS Version Mask.

◆ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT

#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT   28

#include <xdevcfg_hw.h>

PS Version Shift.

◆ XDCFG_MULTIBOOT_ADDR_OFFSET

#define XDCFG_MULTIBOOT_ADDR_OFFSET   0x2C

#include <xdevcfg_hw.h>

Multi BootAddress Pointer.

◆ XDcfg_ReadMultiBootConfig

#define XDcfg_ReadMultiBootConfig (   InstancePtr)

#include <xdevcfg.h>

Value:
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
#define XDCFG_MULTIBOOT_ADDR_OFFSET
Multi BootAddress Pointer.
Definition: xdevcfg_hw.h:88
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:456

Read the multiboot config register value.

Parameters
InstancePtris a pointer to the instance of XDcfg driver.
Returns
None.
Note
C-style signature: u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)

◆ XDcfg_ReadReg

#define XDcfg_ReadReg (   BaseAddr,
  RegOffset 
)    Xil_In32((BaseAddr) + (RegOffset))

◆ XDCFG_ROM_SHADOW_OFFSET

#define XDCFG_ROM_SHADOW_OFFSET   0x28

#include <xdevcfg_hw.h>

DMA ROM Shadow Register.

Referenced by XDcfg_SetRomShadowRegister().

◆ XDcfg_SelectIcapInterface

#define XDcfg_SelectIcapInterface (   InstancePtr)

#include <xdevcfg.h>

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
#define XDCFG_CTRL_OFFSET
Control Register.
Definition: xdevcfg_hw.h:77
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:456
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:474
#define XDCFG_CTRL_PCAP_PR_MASK
Enable PCAP for PR.
Definition: xdevcfg_hw.h:110

Selects ICAP interface for reconfiguration after the initial configuration of the PL.

Parameters
InstancePtris a pointer to the instance of XDcfg driver.
Returns
None.
Note
C-style signature: void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)

◆ XDcfg_SelectPcapInterface

#define XDcfg_SelectPcapInterface (   InstancePtr)

#include <xdevcfg.h>

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
#define XDCFG_CTRL_OFFSET
Control Register.
Definition: xdevcfg_hw.h:77
#define XDcfg_ReadReg(BaseAddr, RegOffset)
Read the given register.
Definition: xdevcfg_hw.h:456
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:474
#define XDCFG_CTRL_PCAP_PR_MASK
Enable PCAP for PR.
Definition: xdevcfg_hw.h:110

Selects PCAP interface for reconfiguration after the initial configuration of the PL.

Parameters
InstancePtris a pointer to the instance of XDcfg driver.
Returns
None.
Note
C-style signature: void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)

◆ XDCFG_STATUS_DMA_CMD_Q_E_MASK

#define XDCFG_STATUS_DMA_CMD_Q_E_MASK   0x40000000

#include <xdevcfg_hw.h>

DMA command Queue empty.

◆ XDCFG_STATUS_DMA_CMD_Q_F_MASK

#define XDCFG_STATUS_DMA_CMD_Q_F_MASK   0x80000000

#include <xdevcfg_hw.h>

DMA command Queue full.

Referenced by XDcfg_GetConfigReg(), and XDcfg_IsDmaBusy().

◆ XDCFG_STATUS_DMA_DONE_CNT_MASK

#define XDCFG_STATUS_DMA_DONE_CNT_MASK   0x30000000

#include <xdevcfg_hw.h>

Number of completed DMA transfers.

◆ XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK

#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK   0x00000008

#include <xdevcfg_hw.h>

BBRAM key disable.

◆ XDCFG_STATUS_EFUSE_JTAG_DIS_MASK

#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK   0x00000002

#include <xdevcfg_hw.h>

EFuse JTAG Disable status.

◆ XDCFG_STATUS_EFUSE_SEC_EN_MASK

#define XDCFG_STATUS_EFUSE_SEC_EN_MASK   0x00000004

#include <xdevcfg_hw.h>

Efuse Security Enable Status.

◆ XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK

#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK   0x00000040

#include <xdevcfg_hw.h>

Illegal APB access.

◆ XDCFG_STATUS_OFFSET

#define XDCFG_STATUS_OFFSET   0x14

◆ XDCFG_STATUS_PCFG_INIT_MASK

#define XDCFG_STATUS_PCFG_INIT_MASK   0x00000010

#include <xdevcfg_hw.h>

FPGA Init Status.

Referenced by XDcfg_Transfer().

◆ XDCFG_STATUS_PSS_CFG_RESET_B

#define XDCFG_STATUS_PSS_CFG_RESET_B   0x00000020

#include <xdevcfg_hw.h>

PL config reset status.

◆ XDCFG_STATUS_PSS_FST_CFG_B

#define XDCFG_STATUS_PSS_FST_CFG_B   0x00000400

#include <xdevcfg_hw.h>

First PL config done.

◆ XDCFG_STATUS_PSS_GPWRDWN_B

#define XDCFG_STATUS_PSS_GPWRDWN_B   0x00000200

#include <xdevcfg_hw.h>

Global power down.

◆ XDCFG_STATUS_PSS_GTS_CFG_B

#define XDCFG_STATUS_PSS_GTS_CFG_B   0x00000100

#include <xdevcfg_hw.h>

Tri-state IO during config.

◆ XDCFG_STATUS_PSS_GTS_USR_B

#define XDCFG_STATUS_PSS_GTS_USR_B   0x00000800

#include <xdevcfg_hw.h>

Tri-state IO during HIZ.

◆ XDCFG_STATUS_RX_FIFO_LVL_MASK

#define XDCFG_STATUS_RX_FIFO_LVL_MASK   0x01F000000

#include <xdevcfg_hw.h>

Rx FIFO level.

◆ XDCFG_STATUS_SECURE_RST_MASK

#define XDCFG_STATUS_SECURE_RST_MASK   0x00000080

#include <xdevcfg_hw.h>

Secure Reset POR Status.

◆ XDCFG_STATUS_TX_FIFO_LVL_MASK

#define XDCFG_STATUS_TX_FIFO_LVL_MASK   0x0007F000

#include <xdevcfg_hw.h>

Tx FIFO level.

◆ XDCFG_SW_ID_OFFSET

#define XDCFG_SW_ID_OFFSET   0x30

#include <xdevcfg_hw.h>

Software ID Register.

Referenced by XDcfg_GetSoftwareIdRegister().

◆ XDcfg_Unlock

#define XDcfg_Unlock (   InstancePtr)

#include <xdevcfg.h>

Value:
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
#define XDCFG_UNLOCK_DATA
First APB access data.
Definition: xdevcfg_hw.h:430
#define XDCFG_UNLOCK_OFFSET
Unlock Register.
Definition: xdevcfg_hw.h:90
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)
Write to the given register.
Definition: xdevcfg_hw.h:474

Unlock the Device Config Interface block.

Parameters
InstancePtris a pointer to the instance of XDcfg driver.
Returns
None.
Note
C-style signature: void XDcfg_Unlock(XDcfg* InstancePtr)

Referenced by XDcfg_CfgInitialize().

◆ XDCFG_UNLOCK_DATA

#define XDCFG_UNLOCK_DATA   0x757BDF0D

#include <xdevcfg_hw.h>

First APB access data.

◆ XDCFG_UNLOCK_OFFSET

#define XDCFG_UNLOCK_OFFSET   0x34

#include <xdevcfg_hw.h>

Unlock Register.

◆ XDcfg_WriteReg

#define XDcfg_WriteReg (   BaseAddr,
  RegOffset,
  Data 
)    Xil_Out32((BaseAddr) + (RegOffset), (Data))

#include <xdevcfg_hw.h>

Write to the given register.

Parameters
BaseAddris the base address of the device
RegOffsetis the register offset to be written
Datais the 32-bit value to write to the register
Returns
None.
Note
C-style signature: void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)

Referenced by XDcfg_ClearControlRegister(), XDcfg_DisablePCAP(), XDcfg_EnablePCAP(), XDcfg_InitiateDma(), XDcfg_InterruptHandler(), XDcfg_IntrClear(), XDcfg_ResetHw(), XDcfg_SetConfigRegister(), XDcfg_SetControlRegister(), XDcfg_SetLockRegister(), XDcfg_SetMiscControlRegister(), XDcfg_SetRomShadowRegister(), and XDcfg_SetStatusRegister().

Typedef Documentation

◆ XDcfg_IntrHandler

typedef void(* XDcfg_IntrHandler) (void *CallBackRef, u32 Status)

#include <xdevcfg.h>

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters
CallBackRefis the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver component, so it is a void pointer.
Statusis the Interrupt status of the XDcfg device.

Function Documentation

◆ XDcfg_CfgInitialize()

int XDcfg_CfgInitialize ( XDcfg InstancePtr,
XDcfg_Config ConfigPtr,
u32  EffectiveAddress 
)

#include <xdevcfg.c>

Initialize the Device Config Interface driver.

This function must be called before other functions of the driver are called.

Parameters
InstancePtris a pointer to the XDcfg instance.
ConfigPtris the config structure.
EffectiveAddressis the base address for the device. It could be a virtual address if address translation is supported in the system, otherwise it is the physical address.
Returns
  • XST_SUCCESS if initialization was successful.
  • XST_DEVICE_IS_STARTED if the device has already been started.
Note
The very first APB access to the Device Configuration Interface block needs to be a write to the UNLOCK register with the value of 0x757BDF0D. This step is to be done once after reset, any other APB access has to come after this. The APB access is considered illegal if the step is not done or if it is done incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, the following additional actions would be carried out. In other words, if all bits are low, the following steps are not done.
  1. AES is disabled
  2. All APB writes disabled
  3. SoC debug fully enabled

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg_Config::DeviceId, XDcfg::IsReady, XDcfg::IsStarted, and XDcfg_Unlock.

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), and XDcfgRegReadExample().

◆ XDcfg_ClearControlRegister()

void XDcfg_ClearControlRegister ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.c>

The function Clears the specified bit positions of the Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the 32 bit value which holds the bit positions to be cleared.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

◆ XDcfg_DisablePCAP()

void XDcfg_DisablePCAP ( XDcfg InstancePtr)

#include <xdevcfg.c>

The functions disables the PCAP interface by clearing the PCAP mode bit in the control register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_MODE_MASK, XDcfg_ReadReg, and XDcfg_WriteReg.

◆ XDcfg_EnablePCAP()

void XDcfg_EnablePCAP ( XDcfg InstancePtr)

#include <xdevcfg.c>

The functions enables the PCAP interface by setting the PCAP mode bit in the control register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
None.
Note
Enable FPGA programming from PCAP interface. Enabling this bit disables all the external interfaces from programming of FPGA except for ICAP. The user needs to ensure that the FPGA is programmed through either PCAP or ICAP.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDCFG_CTRL_PCAP_MODE_MASK, XDcfg_ReadReg, and XDcfg_WriteReg.

◆ XDcfg_GetConfigRegister()

u32 XDcfg_GetConfigRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Configuration Register with the given value.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the Config Register. Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CFG_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_GetControlRegister()

u32 XDcfg_GetControlRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the Control Register. Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, and XDcfg_ReadReg.

Referenced by XDcfg_SelfTest().

◆ XDcfg_GetLockRegister()

u32 XDcfg_GetLockRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Lock Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the Lock Register. Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_LOCK_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_GetMiscControlRegister()

u32 XDcfg_GetMiscControlRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Miscellaneous Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
32 Bit boot software ID.
Note
This register is locked for write once the system enters usermode. Hence API to reading the register only is provided.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_MCTRL_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_GetSoftwareIdRegister()

u32 XDcfg_GetSoftwareIdRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Software ID Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
32 Bit boot software ID.
Note
This register is locked for write once the system enters usermode. Hence API for reading the register only is provided.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, and XDCFG_SW_ID_OFFSET.

◆ XDcfg_GetStatusRegister()

u32 XDcfg_GetStatusRegister ( XDcfg InstancePtr)

#include <xdevcfg.c>

The function reads the contents of the Status Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the Status Register. Use the XDCFG_STATUS_*_MASK constants defined in xdevcfg_hw.h to interpret the returned value.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, and XDCFG_STATUS_OFFSET.

◆ XDcfg_InitiateDma()

void XDcfg_InitiateDma ( XDcfg InstancePtr,
u32  SourcePtr,
u32  DestPtr,
u32  SrcWordLength,
u32  DestWordLength 
)

#include <xdevcfg.c>

This function initiates the DMA transfer.

Parameters
InstancePtris a pointer to the XDcfg instance.
SourcePtrcontains a pointer to the source memory where the data is to be transferred from.
SrcWordLengthis the number of words (32 bit) to be transferred for the source transfer.
DestPtrcontains a pointer to the destination memory where the data is to be transferred to.
DestWordLengthis the number of words (32 bit) to be transferred for the Destination transfer.
Returns
None.
Note
It is the responsibility of the caller function to ensure that correct values are passed to this function.
    The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
address when equal to 2�b01 indicates the last DMA command of an overall transfer.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDCFG_DMA_DEST_ADDR_OFFSET, XDCFG_DMA_DEST_LEN_OFFSET, XDCFG_DMA_SRC_ADDR_OFFSET, XDCFG_DMA_SRC_LEN_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_InterruptHandler()

void XDcfg_InterruptHandler ( XDcfg InstancePtr)

#include <xdevcfg.h>

The interrupt handler for the Device Config Interface.

Events are signaled to upper layer for proper handling.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

◆ XDcfg_IntrClear()

void XDcfg_IntrClear ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.h>

This function clears the specified interrupts in the Interrupt Status Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the bit-mask of the interrupts to be cleared. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, and XDcfg_WriteReg.

Referenced by XDcfg_GetConfigReg().

◆ XDcfg_IntrDisable()

void XDcfg_IntrDisable ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.h>

This function disables the specified interrupts in the device.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the bit-mask of the interrupts to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XDCFG_INT_* bits defined in xdevcfg_hw.h.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_IntrEnable()

void XDcfg_IntrEnable ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.h>

This function enables the specified interrupts in the device.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the bit-mask of the interrupts to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XDCFG_INT_* bits defined in xdevcfg_hw.h.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_IntrGetEnabled()

u32 XDcfg_IntrGetEnabled ( XDcfg InstancePtr)

#include <xdevcfg.h>

This function returns the enabled interrupts read from the Interrupt Mask Register.

Use the XDCFG_INT_* constants defined in xdevcfg_hw.h to interpret the returned value.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the IMR.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_MASK_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_IntrGetStatus()

u32 XDcfg_IntrGetStatus ( XDcfg InstancePtr)

#include <xdevcfg.h>

This function returns the interrupt status read from Interrupt Status Register.

Use the XDCFG_INT_* constants defined in xdevcfg_hw.h to interpret the returned value.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
A 32-bit value representing the contents of the Interrupt Status register.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_INT_STS_OFFSET, and XDcfg_ReadReg.

◆ XDcfg_IsDmaBusy()

u32 XDcfg_IsDmaBusy ( XDcfg InstancePtr)

#include <xdevcfg.c>

This function checks if DMA command queue is full.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
XST_SUCCESS is the DMA is busy XST_FAILURE if the DMA is idle
Note
The DMA queue has a depth of two.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_ReadReg, XDCFG_STATUS_DMA_CMD_Q_F_MASK, and XDCFG_STATUS_OFFSET.

Referenced by XDcfg_Transfer().

◆ XDcfg_LookupConfig()

XDcfg_Config * XDcfg_LookupConfig ( u16  DeviceId)

#include <xdevcfg.h>

Lookup the device configuration based on the unique device ID.

The table contains the configuration info for each device in the system.

Parameters
DeviceIdis the unique device ID of the device being looked up.
Returns
A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
Note
None.

References XDcfg_ConfigTable.

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), and XDcfgRegReadExample().

◆ XDcfg_ResetHw()

void XDcfg_ResetHw ( u32  BaseAddr)

#include <xdevcfg_hw.c>

This function perform the reset sequence to the given devcfg interface by configuring the appropriate control bits in the devcfg specifc registers the devcfg reset squence involves the following steps Disable all the interuupts Clear the status Update relevant config registers with reset values Disbale the looopback mode and pcap rate enable.

Parameters
BaseAddressof the interface
Returns
N/A
Note
This function will not modify the slcr registers that are relavant for devcfg controller

References XDCFG_INT_MASK_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_SelfTest()

int XDcfg_SelfTest ( XDcfg InstancePtr)

#include <xdevcfg.h>

Run a self-test on the Device Configuration Interface.

This test does a control register write and reads back the same value.

Parameters
InstancePtris a pointer to the XDcfg instance.
Returns
  • XST_SUCCESS if self-test was successful.
  • XST_FAILURE if fails.
Note
None.

References XDcfg::IsReady, XDCFG_CTRL_NIDEN_MASK, XDcfg_GetControlRegister(), and XDcfg_SetControlRegister().

Referenced by DcfgSelfTestExample(), XDcfgInterruptExample(), and XDcfgRegReadExample().

◆ XDcfg_SetConfigRegister()

void XDcfg_SetConfigRegister ( XDcfg InstancePtr,
u32  Data 
)

#include <xdevcfg.c>

The function sets the contents of the Configuration Register with the given value.

Parameters
InstancePtris a pointer to the XDcfg instance.
Datais the 32 bit data to be written to the Register.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CFG_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_SetControlRegister()

void XDcfg_SetControlRegister ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.c>

The function sets the contents of the Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the 32 bit mask data to be written to the Register. The mask definitions are defined in the xdevcfg_hw.h file.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_CTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

Referenced by XDcfg_SelfTest().

◆ XDcfg_SetHandler()

void XDcfg_SetHandler ( XDcfg InstancePtr,
void *  CallBackFunc,
void *  CallBackRef 
)

#include <xdevcfg.h>

This function sets the handler that will be called when an event (interrupt) occurs that needs application's attention.

Parameters
InstancePtris a pointer to the XDcfg instance
CallBackFuncis the address of the callback function.
CallBackRefis a user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDcfg::IsReady.

◆ XDcfg_SetLockRegister()

void XDcfg_SetLockRegister ( XDcfg InstancePtr,
u32  Data 
)

#include <xdevcfg.c>

The function sets the contents of the Lock Register.

These bits can only be set to a 1. They will be cleared after a Power On Reset.

Parameters
InstancePtris a pointer to the XDcfg instance.
Datais the 32 bit data to be written to the Register.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_LOCK_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_SetMiscControlRegister()

void XDcfg_SetMiscControlRegister ( XDcfg InstancePtr,
u32  Mask 
)

#include <xdevcfg.c>

The function sets the bit mask for the feature in Miscellaneous Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Maskis the bit-mask of the feature to be set.
Returns
None.
Note
None

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_MCTRL_OFFSET, XDcfg_ReadReg, and XDcfg_WriteReg.

◆ XDcfg_SetRomShadowRegister()

void XDcfg_SetRomShadowRegister ( XDcfg InstancePtr,
u32  Data 
)

#include <xdevcfg.c>

The function sets the contents of the ROM Shadow Control Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Datais the 32 bit data to be written to the Register.
Returns
None.
Note
This register is can only be written and is used to control the RAM shadow of 32 bit 4K page ROM pages in user mode

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_ROM_SHADOW_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_SetStatusRegister()

void XDcfg_SetStatusRegister ( XDcfg InstancePtr,
u32  Data 
)

#include <xdevcfg.c>

The function sets the contents of the Status Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
Datais the 32 bit data to be written to the Register.
Returns
None.
Note
None.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDCFG_STATUS_OFFSET, and XDcfg_WriteReg.

◆ XDcfg_Transfer()

u32 XDcfg_Transfer ( XDcfg InstancePtr,
void *  SourcePtr,
u32  SrcWordLength,
void *  DestPtr,
u32  DestWordLength,
u32  TransferType 
)

#include <xdevcfg.c>

This function starts the DMA transfer.

This function only starts the operation and returns before the operation may be completed. If the interrupt is enabled, an interrupt will be generated when the operation is completed, otherwise it is necessary to poll the Status register to determine when it is completed. It is the responsibility of the caller to determine when the operation is completed by handling the generated interrupt or polling the Status Register.

Parameters
InstancePtris a pointer to the XDcfg instance.
SourcePtrcontains a pointer to the source memory where the data is to be transferred from.
SrcWordLengthis the number of words (32 bit) to be transferred for the source transfer.
DestPtrcontains a pointer to the destination memory where the data is to be transferred to.
DestWordLengthis the number of words (32 bit) to be transferred for the Destination transfer.
TransferTypecontains the type of PCAP transfer being requested. The definitions can be found in the xdevcfg.h file.
Returns
  • XST_SUCCESS.if DMA transfer initiated successfully
  • XST_DEVICE_BUSY if DMA is busy
  • XST_INVALID_PARAM if invalid Source / Destination address is sent or an invalid Source / Destination length is sent
Note
It is the responsibility of the caller to ensure that the cache is flushed and invalidated both before the DMA operation is started and after the DMA operation completes if the memory pointed to is cached. The caller must also ensure that the pointers contain physical address rather than a virtual address if address translation is being used.
    The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
address when equal to 2�b01 indicates the last DMA command of an overall transfer.

References XDcfg_Config::BaseAddr, XDcfg::Config, XDcfg::IsReady, XDcfg_IsDmaBusy(), XDcfg_ReadReg, XDCFG_STATUS_OFFSET, and XDCFG_STATUS_PCFG_INIT_MASK.

Variable Documentation

◆ XDcfg_ConfigTable

XDcfg_Config XDcfg_ConfigTable[1]

#include <xdevcfg_g.c>

Initial value:
= {
{
XPAR_XDCFG_0_DEVICE_ID,
XPAR_XDCFG_0_BASEADDR,
}
}

This table contains configuration information for each Device Config Interface instance in the system.

Referenced by XDcfg_LookupConfig().