![]() |
cfa
Xilinx SDK Drivers API Documentation
|
Macros | |
#define | XCFA_HW_H_ |
Prevent circular inclusions by using protection macros. More... | |
#define | XCfa_In32 Xil_In32 |
Cfa Input Operation. More... | |
#define | XCfa_Out32 Xil_Out32 |
Cfa Output Operation. More... | |
#define | XCfa_ReadReg(BaseAddress, RegOffset) XCfa_In32((BaseAddress) + (u32)(RegOffset)) |
This function macro reads the given register. More... | |
#define | XCfa_WriteReg(BaseAddress, RegOffset, Data) XCfa_Out32((BaseAddress) + (u32)(RegOffset), (Data)) |
This function macro writes the given register. More... | |
General control registers offsets | |
#define | XCFA_CONTROL_OFFSET 0x000 |
Control. More... | |
#define | XCFA_STATUS_OFFSET 0x004 |
Status. More... | |
#define | XCFA_ERROR_OFFSET 0x008 |
Error. More... | |
#define | XCFA_IRQ_EN_OFFSET 0x00C |
IRQ Enable. More... | |
#define | XCFA_VERSION_OFFSET 0x010 |
Version. More... | |
#define | XCFA_SYSDEBUG0_OFFSET 0x014 |
System Debug 0. More... | |
#define | XCFA_SYSDEBUG1_OFFSET 0x018 |
System Debug 1. More... | |
#define | XCFA_SYSDEBUG2_OFFSET 0x01C |
System Debug 2. More... | |
#define | XCFA_ACTIVE_SIZE_OFFSET 0x020 |
Active Size (V x H) More... | |
#define | XCFA_BAYER_PHASE_OFFSET 0x100 |
Bayer_phase RW user register. More... | |
Control register bit mask definition | |
#define | XCFA_CTL_SW_EN_MASK 0x00000001 |
Enable Mask. More... | |
#define | XCFA_CTL_RUE_MASK 0x00000002 |
Register Update Mask. More... | |
#define | XCFA_CTL_BPE_MASK 0x00000010 |
Bypass Mask. More... | |
#define | XCFA_CTL_TPE_MASK 0x00000020 |
Test pattern Mask. More... | |
#define | XCFA_CTL_AUTORESET_MASK 0x40000000 |
Software Reset - Auto-synchronize to SOF Mask. More... | |
#define | XCFA_CTL_RESET_MASK 0x80000000 |
Software Reset - Instantaneous Mask. More... | |
Interrupt Register Bit Masks. It is applicable for | |
Status and Irq_Enable Registers | |
#define | XCFA_IXR_PROCS_STARTED_MASK 0x00000001 |
Process Started Mask. More... | |
#define | XCFA_IXR_EOF_MASK 0x00000002 |
End-Of-Frame Mask. More... | |
#define | XCFA_IXR_SE_MASK 0x00010000 |
Slave Error Mask. More... | |
#define | XCFA_IXR_ALLINTR_MASK 0x00010003 |
Interrupt All Error Mask (ORing of all Interrupt Mask) More... | |
Error Register bit mask definitions | |
#define | XCFA_ERR_EOL_EARLY_MASK 0x00000001 |
Error: End of line Early Mask. More... | |
#define | XCFA_ERR_EOL_LATE_MASK 0x00000002 |
Error: End of line Late Mask. More... | |
#define | XCFA_ERR_SOF_EARLY_MASK 0x00000004 |
Error: Start of frame Early Mask. More... | |
#define | XCFA_ERR_SOF_LATE_MASK 0x00000008 |
Error: Start of frame Late Mask. More... | |
Version register bit definition and shifts | |
#define | XCFA_VER_REV_NUM_MASK 0x000000FF |
Revision Number Mask. More... | |
#define | XCFA_VER_PID_MASK 0x00000F00 |
Patch ID Mask. More... | |
#define | XCFA_VER_MINOR_MASK 0x00FF0000 |
Version Minor Mask. More... | |
#define | XCFA_VER_MAJOR_MASK 0xFF000000 |
Version Major Mask. More... | |
#define | XCFA_VER_REV_MASK 0x0000F000 |
Version revision Mask. More... | |
#define | XCFA_VER_MAJOR_SHIFT 24 |
Version Major Shift. More... | |
#define | XCFA_VER_MINOR_SHIFT 16 |
Version Minor Shift. More... | |
#define | XCFA_VER_INTERNAL_SHIFT 8 |
Version Internal Shift. More... | |
#define | XCFA_VER_REV_SHIFT 12 |
Version Revision Shift. More... | |
Active size register bit mask definition and shifts | |
#define | XCFA_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF |
Active size Mask. More... | |
#define | XCFA_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 |
Number of Active lines per Frame (Vertical) More... | |
#define | XCFA_ACTSIZE_NUM_LINE_SHIFT 16 |
Active size Shift. More... | |
Bayer Phase | |
#define | XCFA_BAYER_PHASE_MASK 0x00000003 |
Bayer Phase Mask. More... | |
General purpose masks | |
#define | XCFA_8_BIT_MASK 0x0FF |
Generic 8 bit Mask. More... | |
Backward compatibility macros | |
#define | CFA_CONTROL XCFA_CONTROL_OFFSET |
#define | CFA_STATUS XCFA_STATUS_OFFSET |
#define | CFA_ERROR XCFA_ERROR_OFFSET |
#define | CFA_IRQ_EN XCFA_IRQ_EN_OFFSET |
#define | CFA_VERSION XCFA_VERSION_OFFSET |
#define | CFA_SYSDEBUG0 XCFA_SYSDEBUG0_OFFSET |
#define | CFA_SYSDEBUG1 XCFA_SYSDEBUG1_OFFSET |
#define | CFA_SYSDEBUG2 XCFA_SYSDEBUG2_OFFSET |
#define | CFA_ACTIVE_SIZE XCFA_ACTIVE_SIZE_OFFSET |
#define | CFA_BAYER_PHASE XCFA_BAYER_PHASE_OFFSET |
#define | CFA_CTL_EN_MASK XCFA_CTL_SW_EN_MASK |
#define | CFA_CTL_RUE_MASK XCFA_CTL_RUE_MASK |
#define | CFA_CTL_CS_MASK XCFA_CTL_CS_MASK |
#define | CFA_RST_RESET XCFA_CTL_RESET_MASK |
#define | CFA_RST_AUTORESET XCFA_CTL_AUTORESET_MASK |
#define | CFA_In32 XCfa_In32 |
#define | CFA_Out32 XCfa_Out32 |
#define | CFA_ReadReg XCfa_ReadReg |
#define | CFA_WriteReg XCfa_WriteReg |
Interrupt Enable and Status Registers Offsets | |
#define | XCFA_ISR_OFFSET XCFA_STATUS_OFFSET |
Interrupt status register generates a interrupt if the corresponding bits of interrupt enable register bits are set. More... | |
#define | XCFA_IER_OFFSET XCFA_IRQ_EN_OFFSET |
Interrupt Enable Offset. More... | |