axidma
Xilinx SDK Drivers API Documentation
XAxiDma_BdRing Struct Reference

Container structure for descriptor storage control. More...

Data Fields

u32 ChanBase
 physical base address More...
 
int IsRxChannel
 Is this a receive channel. More...
 
volatile int RunState
 Whether channel is running. More...
 
int HasStsCntrlStrm
 Whether has stscntrl stream. More...
 
UINTPTR FirstBdPhysAddr
 Physical address of 1st BD in list. More...
 
UINTPTR FirstBdAddr
 Virtual address of 1st BD in list. More...
 
UINTPTR LastBdAddr
 Virtual address of last BD in the list. More...
 
u32 Length
 Total size of ring in bytes. More...
 
UINTPTR Separation
 Number of bytes between the starting address of adjacent BDs. More...
 
XAxiDma_BdFreeHead
 First BD in the free group. More...
 
XAxiDma_BdPreHead
 First BD in the pre-work group. More...
 
XAxiDma_BdHwHead
 First BD in the work group. More...
 
XAxiDma_BdHwTail
 Last BD in the work group. More...
 
XAxiDma_BdPostHead
 First BD in the post-work group. More...
 
XAxiDma_BdBdaRestart
 BD to load when channel is started. More...
 
XAxiDma_BdCyclicBd
 Useful for Cyclic DMA operations. More...
 
int FreeCnt
 Number of allocatable BDs in free group. More...
 
int PreCnt
 Number of BDs in pre-work group. More...
 
int HwCnt
 Number of BDs in work group. More...
 
int PostCnt
 Number of BDs in post-work group. More...
 
int AllCnt
 Total Number of BDs for channel. More...
 
int RingIndex
 Ring Index. More...
 
int Cyclic
 Check for cyclic DMA Mode. More...
 

Detailed Description

Container structure for descriptor storage control.

If address translation is enabled, then all addresses and pointers excluding FirstBdPhysAddr are expressed in terms of the virtual address.

Field Documentation

◆ AllCnt

int XAxiDma_BdRing::AllCnt

◆ BdaRestart

XAxiDma_Bd* XAxiDma_BdRing::BdaRestart

BD to load when channel is started.

◆ ChanBase

◆ Cyclic

int XAxiDma_BdRing::Cyclic

Check for cyclic DMA Mode.

Referenced by XAxiDma_BdRingCreate().

◆ CyclicBd

XAxiDma_Bd* XAxiDma_BdRing::CyclicBd

Useful for Cyclic DMA operations.

◆ FirstBdAddr

UINTPTR XAxiDma_BdRing::FirstBdAddr

Virtual address of 1st BD in list.

◆ FirstBdPhysAddr

UINTPTR XAxiDma_BdRing::FirstBdPhysAddr

Physical address of 1st BD in list.

◆ FreeCnt

int XAxiDma_BdRing::FreeCnt

Number of allocatable BDs in free group.

Referenced by XAxiDma_BdRingAlloc(), XAxiDma_BdRingCreate(), and XAxiDma_BdRingFree().

◆ FreeHead

XAxiDma_Bd* XAxiDma_BdRing::FreeHead

First BD in the free group.

Referenced by XAxiDma_BdRingAlloc().

◆ HasStsCntrlStrm

int XAxiDma_BdRing::HasStsCntrlStrm

Whether has stscntrl stream.

Referenced by XAxiDma_BdRingCreate().

◆ HwCnt

int XAxiDma_BdRing::HwCnt

Number of BDs in work group.

Referenced by XAxiDma_BdRingCreate(), and XAxiDma_BdRingFromHw().

◆ HwHead

XAxiDma_Bd* XAxiDma_BdRing::HwHead

First BD in the work group.

Referenced by XAxiDma_BdRingFromHw().

◆ HwTail

XAxiDma_Bd* XAxiDma_BdRing::HwTail

Last BD in the work group.

◆ IsRxChannel

int XAxiDma_BdRing::IsRxChannel

Is this a receive channel.

Referenced by XAxiDma_BdRingToHw().

◆ LastBdAddr

UINTPTR XAxiDma_BdRing::LastBdAddr

Virtual address of last BD in the list.

◆ Length

u32 XAxiDma_BdRing::Length

Total size of ring in bytes.

◆ PostCnt

int XAxiDma_BdRing::PostCnt

Number of BDs in post-work group.

Referenced by XAxiDma_BdRingCreate(), and XAxiDma_BdRingFree().

◆ PostHead

XAxiDma_Bd* XAxiDma_BdRing::PostHead

First BD in the post-work group.

Referenced by XAxiDma_BdRingFree().

◆ PreCnt

int XAxiDma_BdRing::PreCnt

Number of BDs in pre-work group.

Referenced by XAxiDma_BdRingCreate(), XAxiDma_BdRingToHw(), and XAxiDma_BdRingUnAlloc().

◆ PreHead

XAxiDma_Bd* XAxiDma_BdRing::PreHead

First BD in the pre-work group.

Referenced by XAxiDma_BdRingToHw().

◆ RingIndex

int XAxiDma_BdRing::RingIndex

◆ RunState

volatile int XAxiDma_BdRing::RunState

◆ Separation

UINTPTR XAxiDma_BdRing::Separation

Number of bytes between the starting address of adjacent BDs.

Referenced by XAxiDma_BdRingCreate().