mcdma
Xilinx SDK Drivers API Documentation
xmcdma_polled_example.c File Reference

Overview

This file demonstrates how to use the mcdma driver on the Xilinx AXI MCDMA core (AXI MCDMA) to transfer packets in polling mode.

This examples shows how to do multiple packets transfers, as well as how to do multiple show how to do multiple packets transfers, as well as how to do multiple BD's per packet transfers.

H/W Requirments: In order to test this example at the h/w level AXI MCDMA MM2S should connect with the S2MM.

System level Considerations for ZynqUltrascale+ designs: On ZU+ MPSOC for PL IP's 3 differnet ports are availble HP, HPC and ACP.

The explanation below talks about HPC and HP port.

HPC design considerations: ZU+ MPSOC has in-built cache coherent interconnect(CCI) to take care of coherency through HPC port. Following needs to be done by the users before running the examples. 1) Snooping should be enabled in the S3 (0xFD6E4000) 2) Mark the DDR memory being used for buffers as outer sharable. To do that please modify baremetal bsp file translation_table.S. Change .set Memory, 0x405 | (3 << 8) | (0x0). to .set Memory, 0x405 | (2 << 8) | (0x0).

Please uncomment below define for HPC design so that applicaiton won't do Any Cache flush/invalidation.

//#define HPC_DESIGN

It is recomended to use HPC to make use of H/W coherency feature.

HP design considerations: The example uses un-cached memory for buffer descriptors and uses Normal memory for buffers..

A53 does not provide seperate instruction for cache invalidation. It supports flush (clean + invalidation). Before a DMA starts, Application is expected to do a cache flush for the relevant memory. Once DMA ends, the data can simply be read from memory. However, there will be occasions when A53 L1 cache system can prefetch memory locations Which were earlier flushed. On such scenarios there is high probablity that CPU reads Memory from cache and DMA is still not complete for this memory. This leads lost Coherency between cache and memory. Subsequent data verification(after DMA is complete) thus fails.

It is generally an unpredictable behavior. It is highly unlikely to happen for a single buffer usecase. But for multiple buffers staying in adjacent cache locations, There is a high probability that users can get into such failures.

The L1 prefetch is a feature of the L1 cache system for improving performance. The L1 cache has its own algorithm to prefetch. The prefetch stops when: -> the memory accesses cross a 4KB page boundary. -> a dsb or PRFM instruction is executed. -> the program execution does not hit the prefetched data lines.

Accordingly the solution for the above problem is:

1) Use dsb The location of the dsb is crucial. The programmer needs to predict the maximum probabilty When the L1 prefetch will happen for relevant DMA addresses. It will be typically in the DMA done interrupt (where the data verification happens for a buffer). The cache line size is 64 bytes. The prefetch obviously will happen in chunks of 64 bytes. However, because of the unpredictability nature of the prefetch, it is difficult to find out the exact point of dsb. To be at a safer side, the dsb can be put for every memory location fetched.

There will be heavy performance penalty. Every dsb clears the store buffers. Executing dsbs very frequently will degrade the performance significantly.

2) Disable Prefetch of L1 Cahe This can be done by setting the CPUACTLR_EL1 register.

3) Put buffers from 4k apart

MODIFICATION HISTORY:
Ver   Who  Date       Changes
----- ---- --------   -------------------------------------------------------
1.0      adk  18/07/2017 Initial Version.

Functions

int main (void)
 Main function. More...
 

Function Documentation

◆ main()

int main ( void  )

Main function.

This function is the main entry of the tests on DMA core. It sets up DMA engine to be ready to receive and send packets, then a packet is transmitted and will be verified after it is received via the DMA.

Parameters
None
Returns
  • XST_SUCCESS if test passes
  • XST_FAILURE if test fails.
Note
None.