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Xilinx SDK Drivers API Documentation
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Data Structures | |
struct | XDp_Config |
This typedef contains configuration information for the DisplayPort core. More... | |
struct | XDp_TxSinkConfig |
This typedef contains configuration information about the RX device. More... | |
struct | XDp_TxLinkConfig |
This typedef contains configuration information about the main link settings. More... | |
struct | XDp_TxMainStreamAttributes |
This typedef contains the main stream attributes which determine how the video will be displayed. More... | |
struct | XDp_TxMstStream |
This typedef describes a stream when the driver is running in multi-stream transport (MST) mode. More... | |
struct | XDp_TxBoardChar |
This typedef describes some board characteristics information that affects link training. More... | |
struct | XDp_TxTopologyNode |
This typedef describes a downstream DisplayPort device when the driver is running in multi-stream transport (MST) mode. More... | |
struct | XDp_TxTopology |
This typedef describes a the entire topology of connected downstream DisplayPort devices (from the DisplayPort TX) when the driver is operating in multi-stream transport (MST) mode. More... | |
struct | XDp_SbMsgLinkAddressReplyPortDetail |
This typedef describes a port that is connected to a DisplayPort branch device. More... | |
struct | XDp_SbMsgLinkAddressReplyDeviceInfo |
This typedef describes a DisplayPort branch device. More... | |
struct | XDp_RxLinkConfig |
This typedef contains configuration information about the main link settings. More... | |
struct | XDp_RxIicMapEntry |
This typedef represents one I2C map entry for a device. More... | |
struct | XDp_RxDpcdMap |
This typedef represents the DPCD address map for a device. More... | |
struct | XDp_RxPort |
This typedef contains information on the directly connected ports to the RX branch. More... | |
struct | XDp_RxTopology |
This typedef contains topology information on directly connected sinks and of the RX branch itself. More... | |
struct | XDp_Tx |
The XDp driver instance data representing the TX mode of operation. More... | |
struct | XDp_Rx |
The XDp driver instance data representing the RX mode of operation. More... | |
struct | XDp |
The XDp instance data. More... | |
Macros | |
#define | XDp_GetCoreType(InstancePtr) |
This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX). More... | |
#define | XDp_TxCfgSetRGB(InstancePtr, Stream) |
The following functions set the color encoding scheme for a given stream. More... | |
#define | XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x800 |
Virtual channel payload table (0xFF bytes). More... | |
#define | XDP_RX_HSYNC_WIDTH 0x050 |
Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG). More... | |
#define | XDP_RX_VSYNC_WIDTH 0x058 |
Controls the timing of the active-high vertical sync pulse generated by the display timing generator (DTG). More... | |
#define | XDP_RX_FAST_I2C_DIVIDER 0x060 |
Fast I2C mode clock divider value. More... | |
#define | XDP_RX_MST_ALLOC 0x06C |
Represents the content from the DPCD registers related to payload allocation. More... | |
#define | XDP_RX_NUM_I2C_ENTRIES_PER_PORT 3 |
The number of I2C user- defined entries in the I2C map of each port. More... | |
#define | XDP_GUID_NBYTES 16 |
The number of bytes for the global unique ID. More... | |
#define | XDP_MAX_NPORTS 16 |
The maximum number of ports connected to a DisplayPort device. More... | |
#define | XDp_ReadReg(BaseAddress, RegOffset) XDp_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register. More... | |
#define | XDp_WriteReg(BaseAddress, RegOffset, Data) XDp_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register. More... | |
#define | XDp_TxIsEdidExtBlockDispId(Ext) (Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID) |
Check if an Extended Display Identification Data (EDID) extension block is of type DisplayID. More... | |
#define | XDp_TxGetDispIdTdtHTotal(Tdt) |
Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the tiled display. More... | |
#define | XDp_TxGetDispIdTdtVTotal(Tdt) |
Given a Tiled Display Topology (TDT) data block, retrieve the total number of vertical tiles in the tiled display. More... | |
#define | XDp_TxGetDispIdTdtHLoc(Tdt) |
Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled display. More... | |
#define | XDp_TxGetDispIdTdtVLoc(Tdt) |
Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled display. More... | |
#define | XDp_TxGetDispIdTdtNumTiles(Tdt) (XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt)) |
Given a Tiled Display Topology (TDT) data block, retrieve the total number of tiles in the tiled display. More... | |
#define | XDp_TxGetDispIdTdtTileOrder(Tdt) |
Given a Tiled Display Topology (TDT) data block, calculate the tiling order of the associated tile. More... | |
Typedefs | |
typedef void(* | XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds) |
Callback type which represents a custom timer wait handler. More... | |
typedef void(* | XDp_IntrHandler) (void *InstancePtr) |
Callback type which represents the handler for interrupts. More... | |
Enumerations | |
enum | XDp_TxTrainingState |
This typedef enumerates the list of training states used in the state machine during the link training process. More... | |
enum | XDp_CoreType |
This typedef enumerates the RX and TX modes of operation for the DisplayPort core. More... | |
enum | XDp_DynamicRange |
This typedef enumerates the dynamic ranges available to the DisplayPort core. More... | |
Functions | |
void | XDp_CfgInitialize (XDp *InstancePtr, XDp_Config *ConfigPtr, UINTPTR EffectiveAddr) |
This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure. More... | |
u32 | XDp_Initialize (XDp *InstancePtr) |
This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode. More... | |
u32 | XDp_TxGetRxCapabilities (XDp *InstancePtr) |
This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD). More... | |
u32 | XDp_TxCfgMainLinkMax (XDp *InstancePtr) |
This function determines the common capabilities between the DisplayPort TX core and the RX device. More... | |
u32 | XDp_TxEstablishLink (XDp *InstancePtr) |
This function checks if the link needs training and runs the training sequence if training is required. More... | |
u32 | XDp_TxCheckLinkStatus (XDp *InstancePtr, u8 LaneCount) |
This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates the receiver has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use. More... | |
void | XDp_TxEnableTrainAdaptive (XDp *InstancePtr, u8 Enable) |
This function enables or disables downshifting during the training process. More... | |
void | XDp_TxSetHasRedriverInPath (XDp *InstancePtr, u8 Set) |
This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. More... | |
void | XDp_TxCfgTxVsOffset (XDp *InstancePtr, u8 Offset) |
This function sets the voltage swing offset to use during training when no redriver exists. More... | |
void | XDp_TxCfgTxVsLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level. More... | |
void | XDp_TxCfgTxPeLevel (XDp *InstancePtr, u8 Level, u8 TxLevel) |
This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level. More... | |
u32 | XDp_TxIsConnected (XDp *InstancePtr) |
This function checks if there is a connected RX device. More... | |
u32 | XDp_TxAuxRead (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData) |
This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space. More... | |
u32 | XDp_TxAuxWrite (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData) |
This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space. More... | |
u32 | XDp_TxIicRead (XDp *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData) |
This function performs an I2C read over the AUX channel. More... | |
u32 | XDp_TxIicWrite (XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData) |
This function performs an I2C write over the AUX channel. More... | |
u32 | XDp_TxSetDownspread (XDp *InstancePtr, u8 Enable) |
This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device. More... | |
u32 | XDp_TxSetEnhancedFrameMode (XDp *InstancePtr, u8 Enable) |
This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device. More... | |
u32 | XDp_TxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device. More... | |
u32 | XDp_TxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device. More... | |
u32 | XDp_TxSetScrambler (XDp *InstancePtr, u8 Enable) |
This function enables or disables scrambling of symbols for both the DisplayPort and the RX device. More... | |
void | XDp_TxEnableMainLink (XDp *InstancePtr) |
This function enables the main link. More... | |
void | XDp_TxDisableMainLink (XDp *InstancePtr) |
This function disables the main link. More... | |
void | XDp_TxResetPhy (XDp *InstancePtr, u32 Reset) |
This function does a PHY reset. More... | |
void | XDp_TxSetPhyPolarityAll (XDp *InstancePtr, u8 Polarity) |
This function sets the PHY polarity on all lanes. More... | |
void | XDp_TxSetPhyPolarityLane (XDp *InstancePtr, u8 Lane, u8 Polarity) |
This function sets the PHY polarity on a specified lane. More... | |
u32 | XDp_RxCheckLinkStatus (XDp *InstancePtr) |
This function checks if the receiver's internal registers indicate that link training has complete. More... | |
void | XDp_RxDtgEn (XDp *InstancePtr) |
This function enables the display timing generator (DTG). More... | |
void | XDp_RxDtgDis (XDp *InstancePtr) |
This function disables the display timing generator (DTG). More... | |
void | XDp_RxSetLinkRate (XDp *InstancePtr, u8 LinkRate) |
This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers. More... | |
void | XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount) |
This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers. More... | |
void | XDp_RxAudioEn (XDp *InstancePtr) |
This function enables audio stream packets on the main link. More... | |
void | XDp_RxAudioDis (XDp *InstancePtr) |
This function disables audio stream packets on the main link. More... | |
void | XDp_RxAudioReset (XDp *InstancePtr) |
This function resets the RX core's reception of audio stream packets on the main link. More... | |
void | XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef) |
This function installs a custom delay/sleep function to be used by the XDp driver. More... | |
void | XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds) |
This function is the delay/sleep function for the XDp driver. More... | |
void | XDp_TxSetLaneCountChangeCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the driver's lane count change function is called either directly by the user or during link training. More... | |
void | XDp_TxSetLinkRateChangeCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the driver's link rate change function is called either directly by the user or during link training. More... | |
void | XDp_TxSetPeVsAdjustCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the driver's link rate change function is called during link training. More... | |
u8 | XDp_IsLinkRateValid (XDp *InstancePtr, u8 LinkRate) |
This function checks the validity of the link rate. More... | |
u8 | XDp_IsLaneCountValid (XDp *InstancePtr, u8 LaneCount) |
This function checks the validity of the lane count. More... | |
XDp_Config * | XDp_LookupConfig (u16 DeviceId) |
This function looks for the device configuration based on the unique device ID. More... | |
u32 | XDp_TxGetEdid (XDp *InstancePtr, u8 *Edid) |
This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure. More... | |
u32 | XDp_TxGetRemoteEdid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid) |
This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure. More... | |
u32 | XDp_TxGetEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum) |
Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number. More... | |
u32 | XDp_TxGetRemoteEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress) |
Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number. More... | |
u32 | XDp_TxGetRemoteEdidDispIdExt (XDp *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress) |
Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID. More... | |
u32 | XDp_TxGetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr) |
Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure. More... | |
u32 | XDp_TxGetRemoteTiledDisplayDb (XDp *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr) |
Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure. More... | |
void | XDp_InterruptHandler (XDp *InstancePtr) |
This function is the interrupt handler for the XDp driver. More... | |
void | XDp_TxSetHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a hot-plug-detect event interrupt occurs. More... | |
void | XDp_TxSetHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a hot-plug-detect pulse interrupt occurs. More... | |
void | XDp_TxSetDrvHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a driver's internal callback function for when a hot-plug-detect event interrupt occurs. More... | |
void | XDp_TxSetDrvHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a driver's internal callback function for when a hot-plug-detect pulse interrupt occurs. More... | |
void | XDp_TxSetMsaHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the main stream attribute (MSA) values are updated. More... | |
void | XDp_RxGenerateHpdInterrupt (XDp *InstancePtr, u16 DurationUs) |
This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration. More... | |
void | XDp_RxInterruptEnable (XDp *InstancePtr, u32 Mask) |
This function enables interrupts associated with the specified mask. More... | |
void | XDp_RxInterruptDisable (XDp *InstancePtr, u32 Mask) |
This function disables interrupts associated with the specified mask. More... | |
void | XDp_RxSetIntrVmChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a video mode change interrupt occurs. More... | |
void | XDp_RxSetIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the power state interrupt occurs. More... | |
void | XDp_RxSetIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a no video interrupt occurs. More... | |
void | XDp_RxSetIntrVBlankHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a vertical blanking interrupt occurs. More... | |
void | XDp_RxSetIntrTrainingLostHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a training lost interrupt occurs. More... | |
void | XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a valid video interrupt occurs. More... | |
void | XDp_RxSetIntrInfoPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when an audio info packet interrupt occurs. More... | |
void | XDp_RxSetIntrExtPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when an audio extension packet interrupt occurs. More... | |
void | XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a training done interrupt occurs. More... | |
void | XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a bandwidth change interrupt occurs. More... | |
void | XDp_RxSetIntrTp1Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a training pattern 1 interrupt occurs. More... | |
void | XDp_RxSetIntrTp2Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a training pattern 2 interrupt occurs. More... | |
void | XDp_RxSetIntrTp3Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a training pattern 3 interrupt occurs. More... | |
void | XDp_RxSetIntrDownReqHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a down request interrupt occurs. More... | |
void | XDp_RxSetIntrDownReplyHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a down reply interrupt occurs. More... | |
void | XDp_RxSetIntrAudioOverHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when an audio packet overflow interrupt occurs. More... | |
void | XDp_RxSetIntrPayloadAllocHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when the RX's DPCD payload allocation registers have been written for allocation, de-allocation, or partial deletion. More... | |
void | XDp_RxSetIntrActRxHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when an ACT received interrupt occurs. More... | |
void | XDp_RxSetIntrCrcTestHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a CRC test start interrupt occurs. More... | |
void | XDp_RxSetIntrHdcpDebugWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a write to any hdcp debug register occurs. More... | |
void | XDp_RxSetIntrHdcpAksvWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a write to the hdcp Aksv MSB register occurs. More... | |
void | XDp_RxSetIntrHdcpAnWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a write to the hdcp An MSB register occurs. More... | |
void | XDp_RxSetIntrHdcpAinfoWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a write to the hdcp Ainfo MSB register occurs. More... | |
void | XDp_RxSetIntrHdcpRoReadHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a read of the hdcp Ro/Ri MSB register occurs. More... | |
void | XDp_RxSetIntrHdcpBinfoReadHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when a read of the hdcp Binfo register occurs. More... | |
void | XDp_RxSetIntrUnplugHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a callback function for when an unplug event interrupt occurs. More... | |
void | XDp_RxSetDrvIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a driver callback function for when a valid video interrupt occurs. More... | |
void | XDp_RxSetDrvIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs a driver callback function for when the power state interrupt occurs. More... | |
void | XDp_RxSetDrvIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef) |
This function installs driver callback function for when a no video interrupt occurs. More... | |
void | XDp_TxMstCfgModeEnable (XDp *InstancePtr) |
This function will enable multi-stream transport (MST) mode for the driver. More... | |
void | XDp_TxMstCfgModeDisable (XDp *InstancePtr) |
This function will disable multi-stream transport (MST) mode for the driver. More... | |
u32 | XDp_TxMstCapable (XDp *InstancePtr) |
This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode. More... | |
u32 | XDp_TxMstEnable (XDp *InstancePtr) |
This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device. More... | |
u32 | XDp_TxMstDisable (XDp *InstancePtr) |
This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device. More... | |
void | XDp_TxMstCfgStreamEnable (XDp *InstancePtr, u8 Stream) |
This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream. More... | |
void | XDp_TxMstCfgStreamDisable (XDp *InstancePtr, u8 Stream) |
This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream. More... | |
u8 | XDp_TxMstStreamIsEnabled (XDp *InstancePtr, u8 Stream) |
This function will check whether. More... | |
void | XDp_TxSetStreamSelectFromSinkList (XDp *InstancePtr, u8 Stream, u8 SinkNum) |
This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList. More... | |
void | XDp_TxSetStreamSinkRad (XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress) |
This function will map a stream to a downstream DisplayPort TX device determined by the relative address. More... | |
u32 | XDp_TxDiscoverTopology (XDp *InstancePtr) |
This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. More... | |
u32 | XDp_TxFindAccessibleDpDevices (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress) |
This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. More... | |
void | XDp_TxTopologySwapSinks (XDp *InstancePtr, u8 Index0, u8 Index1) |
Swap the ordering of the sinks in the topology's sink list. More... | |
void | XDp_TxTopologySortSinksByTiling (XDp *InstancePtr) |
Order the sink list with all sinks of the same tiled display being sorted by 'tile order'. More... | |
u32 | XDp_TxRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message. More... | |
u32 | XDp_TxRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message. More... | |
u32 | XDp_TxRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData) |
This function performs a remote I2C read by sending a sideband message. More... | |
u32 | XDp_TxRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData) |
This function performs a remote I2C write by sending a sideband message. More... | |
u32 | XDp_TxAllocatePayloadStreams (XDp *InstancePtr) |
This function will allocate bandwidth for all enabled stream. More... | |
u32 | XDp_TxAllocatePayloadVcIdTable (XDp *InstancePtr, u8 VcId, u8 Ts, u8 StartTs) |
This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress. More... | |
u32 | XDp_TxClearPayloadVcIdTable (XDp *InstancePtr) |
This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices. More... | |
u32 | XDp_TxSendSbMsgRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData) |
This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device. More... | |
u32 | XDp_TxSendSbMsgRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData) |
This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device. More... | |
u32 | XDp_TxSendSbMsgRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData) |
This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device. More... | |
u32 | XDp_TxSendSbMsgRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData) |
This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device. More... | |
u32 | XDp_TxSendSbMsgLinkAddress (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDp_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo) |
This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device. More... | |
u32 | XDp_TxSendSbMsgEnumPathResources (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn) |
This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device. More... | |
u32 | XDp_TxSendSbMsgAllocatePayload (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn) |
This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device. More... | |
u32 | XDp_TxSendSbMsgClearPayloadIdTable (XDp *InstancePtr) |
This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables. More... | |
void | XDp_TxWriteGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Guid) |
This function will write a global unique identifier (GUID) to the target DisplayPort device. More... | |
void | XDp_TxGetGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Guid) |
This function will obtain the global unique identifier (GUID) for the target DisplayPort device. More... | |
u32 | XDp_RxHandleDownReq (XDp *InstancePtr) |
This function will handle incoming sideband messages. More... | |
XDp_RxIicMapEntry * | XDp_RxGetIicMapEntry (XDp *InstancePtr, u8 PortNum, u8 IicAddress) |
This function returns a pointer to the I2C map entry at the supplied I2C address for the specified port. More... | |
u32 | XDp_RxSetIicMapEntry (XDp *InstancePtr, u8 PortNum, u8 IicAddress, u8 ReadNumBytes, u8 *ReadData) |
This function adds an entry into the I2C map for a given port. More... | |
void | XDp_RxSetDpcdMap (XDp *InstancePtr, u8 PortNum, u32 StartAddr, u32 NumBytes, u8 *DpcdMap) |
This function specified the DPCD address space for a given port. More... | |
void | XDp_RxMstExposePort (XDp *InstancePtr, u8 PortNum, u8 Expose) |
This function allows the user to select which ports will be exposed when replying to a LINK_ADDRESS sideband message. More... | |
void | XDp_RxMstSetPort (XDp *InstancePtr, u8 PortNum, XDp_SbMsgLinkAddressReplyPortDetail *PortDetails) |
This function sets the port information that is contained in the driver instance structure for the specified port number, to be copied from the supplied port details structure. More... | |
void | XDp_RxMstSetInputPort (XDp *InstancePtr, u8 PortNum, XDp_SbMsgLinkAddressReplyPortDetail *PortOverride) |
This function, for an input port, sets the port information that is contained in the driver instance structure for the specified port number. More... | |
void | XDp_RxMstSetPbn (XDp *InstancePtr, u8 PortNum, u16 PbnVal) |
This function will set the available payload bandwidth number (PBN) of the specified port that is available for allocation, and the full PBN that the port is capable of using. More... | |
u32 | XDp_SelfTest (XDp *InstancePtr) |
This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. More... | |
void | XDp_TxCfgMsaRecalculate (XDp *InstancePtr, u8 Stream) |
This function calculates the following Main Stream Attributes (MSA): More... | |
void | XDp_TxCfgMsaUseStandardVideoMode (XDp *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode) |
This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table. More... | |
void | XDp_TxCfgMsaUseEdidPreferredTiming (XDp *InstancePtr, u8 Stream, u8 *Edid) |
This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. More... | |
void | XDp_TxCfgMsaUseCustom (XDp *InstancePtr, u8 Stream, XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate) |
This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig. More... | |
u32 | XDp_TxCfgSetColorEncode (XDp *InstancePtr, u8 Stream, XVidC_ColorFormat Format, XVidC_ColorStd ColorCoeffs, XDp_DynamicRange Range) |
This function will set the color encoding scheme for a given stream. More... | |
void | XDp_TxCfgMsaSetBpc (XDp *InstancePtr, u8 Stream, u8 BitsPerColor) |
This function sets the bits per color value of the video stream. More... | |
void | XDp_TxCfgMsaEnSynchClkMode (XDp *InstancePtr, u8 Stream, u8 Enable) |
This function enables or disables synchronous clock mode for a video stream. More... | |
void | XDp_TxSetVideoMode (XDp *InstancePtr, u8 Stream) |
This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure. More... | |
void | XDp_TxClearMsaValues (XDp *InstancePtr, u8 Stream) |
This function clears the main stream attributes registers of the DisplayPort TX core. More... | |
void | XDp_TxSetMsaValues (XDp *InstancePtr, u8 Stream) |
This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure. More... | |
void | XDp_TxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth) |
This function configures the number of pixels output through the user data interface for DisplayPort TX core. More... | |
void | XDp_RxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth) |
This function configures the number of pixels output through the user data interface. More... | |
XVidC_ColorDepth | XDp_RxGetBpc (XDp *InstancePtr, u8 Stream) |
This function extracts the bits per color from MISC0 of the stream. More... | |
XVidC_ColorFormat | XDp_RxGetColorComponent (XDp *InstancePtr, u8 Stream) |
This function extracts the color component format from MISC0 of the stream. More... | |
void | XDp_RxSetLineReset (XDp *InstancePtr, u8 Stream) |
Disable/enables the end of line reset to the internal video pipe in case of reduced blanking as required. More... | |
void | XDp_RxAllocatePayloadStream (XDp *InstancePtr) |
This function will set the virtual channel payload table both in software and in the DisplayPort RX core's hardware registers based on the MST allocation values from ALLOCATE_PAYLOAD and CLEAR_PAYLOAD sideband message requests. More... | |
Variables | |
u8 | GuidTable [16][XDP_GUID_NBYTES] |
This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function. More... | |
u32 | TxResetValues [2][2] |
This table contains the default values for the DisplayPort TX core's general usage registers. More... | |
u32 | TxResetValuesMsa [20][2] |
This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers. More... | |
u32 | RxResetValues [2][2] |
This table contains the default values for the DisplayPort RX core's general usage registers. More... | |
XDp_Config | XDp_ConfigTable [XPAR_XDP_NUM_INSTANCES] |
A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. More... | |
DPTX core registers: Link configuration field. | |
#define | XDP_TX_LINK_BW_SET 0x000 |
Set main link bandwidth setting. More... | |
#define | XDP_TX_LANE_COUNT_SET 0x004 |
Set lane count setting. More... | |
#define | XDP_TX_ENHANCED_FRAME_EN 0x008 |
Enable enhanced framing symbol sequence. More... | |
#define | XDP_TX_TRAINING_PATTERN_SET 0x00C |
Set the link training pattern. More... | |
#define | XDP_TX_LINK_QUAL_PATTERN_SET 0x010 |
Transmit the link quality pattern. More... | |
#define | XDP_TX_SCRAMBLING_DISABLE 0x014 |
Disable scrambler and transmit all symbols. More... | |
#define | XDP_TX_DOWNSPREAD_CTRL 0x018 |
Enable a 0.5% spreading of the clock. More... | |
#define | XDP_TX_SOFT_RESET 0x01C |
Software reset. More... | |
DPTX core registers: Core enables. | |
#define | XDP_TX_ENABLE 0x080 |
Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. More... | |
#define | XDP_TX_ENABLE_MAIN_STREAM 0x084 |
Enable transmission of main link video info. More... | |
#define | XDP_TX_ENABLE_SEC_STREAM 0x088 |
Enable the transmission of secondary link info. More... | |
#define | XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 |
Force a scrambler reset. More... | |
#define | XDP_TX_MST_CONFIG 0x0D0 |
Enable MST. More... | |
#define | XDP_TX_LINE_RESET_DISABLE 0x0F0 |
TX line reset disable. More... | |
DPTX core registers: Core ID. | |
#define | XDP_TX_VERSION 0x0F8 |
Version and revision of the DisplayPort core. More... | |
#define | XDP_TX_CORE_ID 0x0FC |
DisplayPort protocol version and revision. More... | |
DPTX core registers: AUX channel interface. | |
#define | XDP_TX_AUX_CMD 0x100 |
Initiates AUX commands. More... | |
#define | XDP_TX_AUX_WRITE_FIFO 0x104 |
Write data for the current AUX command. More... | |
#define | XDP_TX_AUX_ADDRESS 0x108 |
Specifies the address of current AUX command. More... | |
#define | XDP_TX_AUX_CLK_DIVIDER 0x10C |
Clock divider value for generating the internal 1MHz clock. More... | |
#define | XDP_TX_USER_FIFO_OVERFLOW 0x110 |
Indicates an overflow in user FIFO. More... | |
#define | XDP_TX_INTERRUPT_SIG_STATE 0x130 |
The raw signal values for interrupt events. More... | |
#define | XDP_TX_AUX_REPLY_DATA 0x134 |
Reply data received during the AUX reply. More... | |
#define | XDP_TX_AUX_REPLY_CODE 0x138 |
Reply code received from the most recent AUX command. More... | |
#define | XDP_TX_AUX_REPLY_COUNT 0x13C |
Number of reply transactions received over AUX. More... | |
#define | XDP_TX_INTERRUPT_STATUS 0x140 |
Status for interrupt events. More... | |
#define | XDP_TX_INTERRUPT_MASK 0x144 |
Masks the specified interrupt sources. More... | |
#define | XDP_TX_REPLY_DATA_COUNT 0x148 |
Total number of data bytes actually received during a transaction. More... | |
#define | XDP_TX_REPLY_STATUS 0x14C |
Reply status of most recent AUX transaction. More... | |
#define | XDP_TX_HPD_DURATION 0x150 |
Duration of the HPD pulse in microseconds. More... | |
DPTX core registers: Main stream attributes for SST / MST STREAM1. | |
#define | XDP_TX_STREAM1_MSA_START 0x180 |
Start of the MSA registers for stream 1. More... | |
#define | XDP_TX_MAIN_STREAM_HTOTAL 0x180 |
Total number of clocks in the horizontal framing period. More... | |
#define | XDP_TX_MAIN_STREAM_VTOTAL 0x184 |
Total number of lines in the video frame. More... | |
#define | XDP_TX_MAIN_STREAM_POLARITY 0x188 |
Polarity for the video sync signals. More... | |
#define | XDP_TX_MAIN_STREAM_HSWIDTH 0x18C |
Width of the horizontal sync pulse. More... | |
#define | XDP_TX_MAIN_STREAM_VSWIDTH 0x190 |
Width of the vertical sync pulse. More... | |
#define | XDP_TX_MAIN_STREAM_HRES 0x194 |
Number of active pixels per line (the horizontal resolution). More... | |
#define | XDP_TX_MAIN_STREAM_VRES 0x198 |
Number of active lines (the vertical resolution). More... | |
#define | XDP_TX_MAIN_STREAM_HSTART 0x19C |
Number of clocks between the leading edge of the horizontal sync and the start of active data. More... | |
#define | XDP_TX_MAIN_STREAM_VSTART 0x1A0 |
Number of lines between the leading edge of the vertical sync and the first line of active data. More... | |
#define | XDP_TX_MAIN_STREAM_MISC0 0x1A4 |
Miscellaneous stream attributes. More... | |
#define | XDP_TX_MAIN_STREAM_MISC1 0x1A8 |
Miscellaneous stream attributes. More... | |
#define | XDP_TX_M_VID 0x1AC |
M value for the video stream as computed by the source core in asynchronous clock mode. More... | |
#define | XDP_TX_TU_SIZE 0x1B0 |
Size of a transfer unit in the framing logic. More... | |
#define | XDP_TX_N_VID 0x1B4 |
N value for the video stream as computed by the source core in asynchronous clock mode. More... | |
#define | XDP_TX_USER_PIXEL_WIDTH 0x1B8 |
Selects the width of the user data input port. More... | |
#define | XDP_TX_USER_DATA_COUNT_PER_LANE 0x1BC |
Used to translate the number of pixels per line to the native internal 16-bit datapath. More... | |
#define | XDP_TX_MAIN_STREAM_INTERLACED 0x1C0 |
Video is interlaced. More... | |
#define | XDP_TX_MIN_BYTES_PER_TU 0x1C4 |
The minimum number of bytes per transfer unit. More... | |
#define | XDP_TX_FRAC_BYTES_PER_TU 0x1C8 |
The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value. More... | |
#define | XDP_TX_INIT_WAIT 0x1CC |
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. More... | |
#define | XDP_TX_STREAM1 0x1D0 |
Average stream symbol timeslots per MTP config. More... | |
#define | XDP_TX_STREAM2 0x1D4 |
Average stream symbol timeslots per MTP config. More... | |
#define | XDP_TX_STREAM3 0x1D8 |
Average stream symbol timeslots per MTP config. More... | |
#define | XDP_TX_STREAM4 0x1DC |
Average stream symbol timeslots per MTP config. More... | |
DPTX core registers: PHY configuration status. | |
#define | XDP_TX_PHY_CONFIG 0x200 |
Transceiver PHY reset and configuration. More... | |
#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220 |
Controls the differential voltage swing. More... | |
#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224 |
Controls the differential voltage swing. More... | |
#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228 |
Controls the differential voltage swing. More... | |
#define | XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22C |
Controls the differential voltage swing. More... | |
#define | XDP_TX_PHY_TRANSMIT_PRBS7 0x230 |
Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. More... | |
#define | XDP_TX_PHY_CLOCK_SELECT 0x234 |
Instructs the PHY PLL to generate the proper clock frequency for the required link rate. More... | |
#define | XDP_TX_PHY_POWER_DOWN 0x238 |
Controls PHY power down. More... | |
#define | XDP_TX_PHY_PRECURSOR_LANE_0 0x23C |
Controls the pre-cursor level. More... | |
#define | XDP_TX_PHY_PRECURSOR_LANE_1 0x240 |
Controls the pre-cursor level. More... | |
#define | XDP_TX_PHY_PRECURSOR_LANE_2 0x244 |
Controls the pre-cursor level. More... | |
#define | XDP_TX_PHY_PRECURSOR_LANE_3 0x248 |
Controls the pre-cursor level. More... | |
#define | XDP_TX_PHY_POSTCURSOR_LANE_0 0x24C |
Controls the post-cursor level. More... | |
#define | XDP_TX_PHY_POSTCURSOR_LANE_1 0x250 |
Controls the post-cursor level. More... | |
#define | XDP_TX_PHY_POSTCURSOR_LANE_2 0x254 |
Controls the post-cursor level. More... | |
#define | XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 |
Controls the post-cursor level. More... | |
#define | XDP_TX_PHY_STATUS 0x280 |
Current PHY status. More... | |
#define | XDP_TX_GT_DRP_COMMAND 0x2A0 |
Provides access to the GT DRP ports. More... | |
#define | XDP_TX_GT_DRP_READ_DATA 0x2A4 |
Provides access to GT DRP read data. More... | |
#define | XDP_TX_GT_DRP_CHANNEL_STATUS 0x2A8 |
Provides access to GT DRP channel status. More... | |
DPTX core registers: DisplayPort audio. | |
#define | XDP_TX_AUDIO_CONTROL 0x300 |
Enables audio stream packets in main link and buffer control. More... | |
#define | XDP_TX_AUDIO_CHANNELS 0x304 |
Used to input active channel count. More... | |
#define | XDP_TX_AUDIO_INFO_DATA(NUM) (0x308 + 4 * (NUM - 1)) |
Word formatted as per CEA 861-C info frame. More... | |
#define | XDP_TX_AUDIO_MAUD 0x328 |
M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. More... | |
#define | XDP_TX_AUDIO_NAUD 0x32C |
N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. More... | |
#define | XDP_TX_AUDIO_EXT_DATA(NUM) (0x330 + 4 * (NUM - 1)) |
Word formatted as per extension packet. More... | |
DPTX core registers: DisplayPort video. | |
#define | XDP_TX_VIDEO_PACKING_CLOCK_CONTROL 0x90 |
DPTX core registers: HDCP. | |
#define | XDP_TX_HDCP_ENABLE 0x400 |
Enables HDCP core. More... | |
DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4. | |
#define | XDP_TX_STREAM2_MSA_START 0x500 |
Start of the MSA registers for stream 2. More... | |
#define | XDP_TX_STREAM2_MSA_START_OFFSET |
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. More... | |
#define | XDP_TX_STREAM3_MSA_START 0x550 |
Start of the MSA registers for stream 3. More... | |
#define | XDP_TX_STREAM3_MSA_START_OFFSET |
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. More... | |
#define | XDP_TX_STREAM4_MSA_START 0x5A0 |
Start of the MSA registers for stream 4. More... | |
#define | XDP_TX_STREAM4_MSA_START_OFFSET |
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. More... | |
DPTX core masks, shifts, and register values. | |
#define | XDP_TX_LINK_BW_SET_162GBPS 0x06 |
1.62 Gbps link rate. More... | |
#define | XDP_TX_LINK_BW_SET_270GBPS 0x0A |
2.70 Gbps link rate. More... | |
#define | XDP_TX_LINK_BW_SET_540GBPS 0x14 |
5.40 Gbps link rate. More... | |
#define | XDP_TX_LANE_COUNT_SET_1 0x01 |
Lane count of 1. More... | |
#define | XDP_TX_LANE_COUNT_SET_2 0x02 |
Lane count of 2. More... | |
#define | XDP_TX_LANE_COUNT_SET_4 0x04 |
Lane count of 4. More... | |
#define | XDP_TX_TRAINING_PATTERN_SET_OFF 0x0 |
Training off. More... | |
#define | XDP_TX_TRAINING_PATTERN_SET_TP1 0x1 |
Training pattern 1 used for clock recovery. More... | |
#define | XDP_TX_TRAINING_PATTERN_SET_TP2 0x2 |
Training pattern 2 used for channel equalization. More... | |
#define | XDP_TX_TRAINING_PATTERN_SET_TP3 0x3 |
Training pattern 3 used for channel equalization for cores with DP v1.2. More... | |
#define | XDP_TX_LINK_QUAL_PATTERN_SET_OFF 0x0 |
Link quality test pattern not transmitted. More... | |
#define | XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST 0x1 |
D10.2 unscrambled test pattern transmitted. More... | |
#define | XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES 0x2 |
Symbol error rate measurement pattern transmitted. More... | |
#define | XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7 0x3 |
Pseudo random bit sequence 7 transmitted. More... | |
#define | XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK 0x00000001 |
Reset video logic. More... | |
#define | XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK 0x00000002 |
Reset video logic. More... | |
#define | XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK 0x00000004 |
Reset video logic. More... | |
#define | XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK 0x00000008 |
Reset video logic. More... | |
#define | XDP_TX_SOFT_RESET_AUX_MASK 0x00000080 |
Reset AUX logic. More... | |
#define | XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK 0x0000000F |
Reset video logic for all streams. More... | |
#define | XDP_TX_MST_CONFIG_MST_EN_MASK 0x00000001 |
Enable MST. More... | |
#define | XDP_TX_MST_CONFIG_VCP_UPDATED_MASK 0x00000002 |
The VC payload has been updated in the sink. More... | |
#define | XDP_TX_LINE_RESET_DISABLE_MASK(Stream) (1 << ((Stream) - XDP_TX_STREAM_ID1)) |
Used to disable the end of the line reset to the internal video pipe. More... | |
#define | XDP_TX_VERSION_INTER_REV_MASK 0x0000000F |
Internal revision. More... | |
#define | XDP_TX_VERSION_CORE_PATCH_MASK 0x00000030 |
Core patch details. More... | |
#define | XDP_TX_VERSION_CORE_PATCH_SHIFT 8 |
Shift bits for core patch details. More... | |
#define | XDP_TX_VERSION_CORE_VER_REV_MASK 0x000000C0 |
Core version revision. More... | |
#define | XDP_TX_VERSION_CORE_VER_REV_SHIFT 12 |
Shift bits for core version revision. More... | |
#define | XDP_TX_VERSION_CORE_VER_MNR_MASK 0x00000F00 |
Core minor version. More... | |
#define | XDP_TX_VERSION_CORE_VER_MNR_SHIFT 16 |
Shift bits for core minor version. More... | |
#define | XDP_TX_VERSION_CORE_VER_MJR_MASK 0x0000F000 |
Core major version. More... | |
#define | XDP_TX_VERSION_CORE_VER_MJR_SHIFT 24 |
Shift bits for core major version. More... | |
#define | XDP_TX_CORE_ID_TYPE_MASK 0x0000000F |
Core type. More... | |
#define | XDP_TX_CORE_ID_TYPE_TX 0x0 |
Core is a transmitter. More... | |
#define | XDP_TX_CORE_ID_TYPE_RX 0x1 |
Core is a receiver. More... | |
#define | XDP_TX_CORE_ID_DP_REV_MASK 0x000000F0 |
DisplayPort protocol revision. More... | |
#define | XDP_TX_CORE_ID_DP_REV_SHIFT 8 |
Shift bits for DisplayPort protocol revision. More... | |
#define | XDP_TX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 |
DisplayPort protocol minor version. More... | |
#define | XDP_TX_CORE_ID_DP_MNR_VER_SHIFT 16 |
Shift bits for DisplayPort protocol major version. More... | |
#define | XDP_TX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 |
DisplayPort protocol major version. More... | |
#define | XDP_TX_CORE_ID_DP_MJR_VER_SHIFT 24 |
Shift bits for DisplayPort protocol major version. More... | |
#define | XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F |
Number of bytes to transfer with the current AUX command. More... | |
#define | XDP_TX_AUX_CMD_MASK 0x00000F00 |
AUX command. More... | |
#define | XDP_TX_AUX_CMD_SHIFT 8 |
Shift bits for command. More... | |
#define | XDP_TX_AUX_CMD_I2C_WRITE 0x0 |
I2C-over-AUX write command. More... | |
#define | XDP_TX_AUX_CMD_I2C_READ 0x1 |
I2C-over-AUX read command. More... | |
#define | XDP_TX_AUX_CMD_I2C_WRITE_STATUS 0x2 |
I2C-over-AUX write status command. More... | |
#define | XDP_TX_AUX_CMD_I2C_WRITE_MOT 0x4 |
I2C-over-AUX write MOT (middle-of-transaction) command. More... | |
#define | XDP_TX_AUX_CMD_I2C_READ_MOT 0x5 |
I2C-over-AUX read MOT (middle-of-transaction) command. More... | |
#define | XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT 0x6 |
I2C-over-AUX write status MOT (middle-of- transaction) command. More... | |
#define | XDP_TX_AUX_CMD_WRITE 0x8 |
AUX write command. More... | |
#define | XDP_TX_AUX_CMD_READ 0x9 |
AUX read command. More... | |
#define | XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 |
Address only transfer enable (STOP will be sent after command). More... | |
#define | XDP_TX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
Clock divider value. More... | |
#define | XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
AUX (noise) signal width filter. More... | |
#define | XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
Shift bits for AUX signal width filter. More... | |
#define | XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 |
Raw state of the HPD pin on the DP connector. More... | |
#define | XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK 0x00000002 |
A request is currently being sent. More... | |
#define | XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK 0x00000004 |
A reply is currently being received. More... | |
#define | XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK 0x00000008 |
A reply timeout has occurred. More... | |
#define | XDP_TX_AUX_REPLY_CODE_ACK 0x0 |
AUX command ACKed. More... | |
#define | XDP_TX_AUX_REPLY_CODE_I2C_ACK 0x0 |
I2C-over-AUX command not ACKed. More... | |
#define | XDP_TX_AUX_REPLY_CODE_NACK 0x1 |
AUX command not ACKed. More... | |
#define | XDP_TX_AUX_REPLY_CODE_DEFER 0x2 |
AUX command deferred. More... | |
#define | XDP_TX_AUX_REPLY_CODE_I2C_NACK 0x4 |
I2C-over-AUX command not ACKed. More... | |
#define | XDP_TX_AUX_REPLY_CODE_I2C_DEFER 0x8 |
I2C-over-AUX command deferred. More... | |
#define | XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK 0x00000001 |
Detected an IRQ framed with the proper timing on the HPD signal. More... | |
#define | XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK 0x00000002 |
Detected the presence of the HPD signal. More... | |
#define | XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK 0x00000004 |
An AUX reply transaction has been detected. More... | |
#define | XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK 0x00000008 |
A reply timeout has occurred. More... | |
#define | XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK 0x00000010 |
A pulse on the HPD line was detected. More... | |
#define | XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK 0x00000020 |
Extended packet has been transmitted and the core is ready to accept a new packet. More... | |
#define | XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK 0x00000001 |
Mask HPD IRQ interrupt. More... | |
#define | XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK 0x00000002 |
Mask HPD event interrupt. More... | |
#define | XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK 0x00000004 |
Mask reply received interrupt. More... | |
#define | XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK 0x00000008 |
Mask reply received interrupt. More... | |
#define | XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK 0x00000010 |
Mask HPD pulse detected interrupt. More... | |
#define | XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK 0x00000020 |
Mask extended packet transmit interrupt. More... | |
#define | XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 |
AUX transaction is complete and a valid reply transaction received. More... | |
#define | XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 |
AUX reply is currently being received. More... | |
#define | XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 |
AUX request is currently being transmitted. More... | |
#define | XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 |
Detected an error in the AUX reply of the most recent transaction. More... | |
#define | XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 |
Internal AUX reply state machine status bits. More... | |
#define | XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 |
Shift bits for the internal AUX reply state machine status. More... | |
#define | XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK 0x00000001 |
Polarity of the horizontal sync pulse. More... | |
#define | XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK 0x00000002 |
Polarity of the vertical sync pulse. More... | |
#define | XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 |
Shift bits for polarity of the vertical sync pulse. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK 0x00000001 |
Synchronous clock. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 |
Component format. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 |
Shift bits for component format. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB 0x0 |
Stream's component format is RGB. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 0x5 |
Stream's component format is YcbCr 4:2:2. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 0x6 |
Stream's component format is YcbCr 4:4:4. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 |
Dynamic range. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 |
Shift bits for dynamic range. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_VESA 0 |
VESA range. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_CEA 1 |
CEA range. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 |
YCbCr colorimetry. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 |
Shift bits for YCbCr colorimetry. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT601 0 |
ITU BT601 YCbCr coefficients. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT709 1 |
ITU BT709 YCbCr coefficients. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 |
Bit depth per color component (BDC). More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT 5 |
Shift bits for BDC. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC 0x0 |
6 bits per component. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC 0x1 |
8 bits per component. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC 0x2 |
10 bits per component. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC 0x3 |
12 bits per component. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC 0x4 |
16 bits per component. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_OVERRIDE_CLOCKING_MODE_MASK 0x00000100 |
Override Audio clk Mode. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_AUD_MODE_MASK 0x00000200 |
Audio clock modes, Setting this bit to 1 enables sync mode. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_AUD_INSERT_TIMESTAMP_MASK 0x00000400 |
Inserts info/timestamp every 512 BS symbols. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC0_AUD_UNMASK_LOWER_MAUD_BITS_MASK 0x00000800 |
Unmasks lower 2-bits of Maud value. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK 0x00000001 |
Interlaced vertical total even. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK 0x00000006 |
Stereo video attribute. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT 1 |
Shift bits for stereo video attribute. More... | |
#define | XDP_TX_MAIN_STREAMX_MISC1_Y_ONLY_EN_MASK 0x00000080 /* Y-only enable. */ |
#define | XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x0000000 |
Release reset. More... | |
#define | XDP_TX_PHY_CONFIG_PHY_RESET_MASK 0x0000001 |
Hold the PHY in reset. More... | |
#define | XDP_TX_PHY_CONFIG_GTTX_RESET_MASK 0x0000002 |
Hold GTTXRESET in reset. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK 0x0000100 |
Hold TX_PHY_PMA reset. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0000200 |
Hold TX_PHY_PCS reset. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000800 |
Set TX_PHY_POLARITY. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0001000 |
Set TX_PHY_PRBSFORCEERR. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 |
Set TX_PHY_LOOPBACK. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 |
Shift bits for TX_PHY_LOOPBACK. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK 0x0010000 |
Set to enable individual lane polarity. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK 0x0020000 |
Set TX_PHY_POLARITY for lane 0. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK 0x0040000 |
Set TX_PHY_POLARITY for lane 1. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK 0x0080000 |
Set TX_PHY_POLARITY for lane 2. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK 0x0100000 |
Set TX_PHY_POLARITY for lane 3. More... | |
#define | XDP_TX_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0200000 |
8B10B encoding enable. More... | |
#define | XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 |
Reset GT and PHY. More... | |
#define | XDP_TX_PHY_CLOCK_SELECT_162GBPS 0x1 |
1.62 Gbps link. More... | |
#define | XDP_TX_PHY_CLOCK_SELECT_270GBPS 0x3 |
2.70 Gbps link. More... | |
#define | XDP_TX_PHY_CLOCK_SELECT_540GBPS 0x5 |
5.40 Gbps link. More... | |
#define | XDP_TX_VS_LEVEL_0 0x2 |
Voltage swing level 0. More... | |
#define | XDP_TX_VS_LEVEL_1 0x5 |
Voltage swing level 1. More... | |
#define | XDP_TX_VS_LEVEL_2 0x8 |
Voltage swing level 2. More... | |
#define | XDP_TX_VS_LEVEL_3 0xF |
Voltage swing level 3. More... | |
#define | XDP_TX_VS_LEVEL_OFFSET 0x4 |
Voltage swing compensation offset used when there's no redriver in display path. More... | |
#define | XDP_TX_PE_LEVEL_0 0x00 |
Pre-emphasis level 0. More... | |
#define | XDP_TX_PE_LEVEL_1 0x0E |
Pre-emphasis level 1. More... | |
#define | XDP_TX_PE_LEVEL_2 0x14 |
Pre-emphasis level 2. More... | |
#define | XDP_TX_PE_LEVEL_3 0x1B |
Pre-emphasis level 3. More... | |
#define | XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001 |
Reset done for lane 0. More... | |
#define | XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK 0x00000002 |
Reset done for lane 1. More... | |
#define | XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C |
Reset done for lanes 2 and 3. More... | |
#define | XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 |
Shift bits for reset done for lanes 2 and 3. More... | |
#define | XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 |
PLL locked for lanes 0 and 1. More... | |
#define | XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 |
PLL locked for lanes 2 and 3. More... | |
#define | XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 |
FPGA fabric clock PLL locked. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK 0x00030000 |
TX buffer status lane 0. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT 16 |
Shift bits for TX buffer status lane 0. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK 0x000C0000 |
TX error on lane 0. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT 18 |
Shift bits for TX error on lane 0. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK 0x00300000 |
TX buffer status lane 1. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT 20 |
Shift bits for TX buffer status lane 1. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK 0x00C00000 |
TX error on lane 1. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT 22 |
Shift bits for TX error on lane 1. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK 0x03000000 |
TX buffer status lane 2. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT 24 |
Shift bits for TX buffer status lane 2. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK 0x0C000000 |
TX error on lane 2. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT 26 |
Shift bits for TX error on lane 2. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK 0x30000000 |
TX buffer status lane 3. More... | |
#define | XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT 28 |
Shift bits for TX buffer status lane 3. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK 0xC0000000 |
TX error on lane 3. More... | |
#define | XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT 30 |
Shift bits for TX error on lane 3. More... | |
#define | XDP_TX_PHY_STATUS_LANE_0_READY_MASK |
Lane 0 is ready. More... | |
#define | XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK |
Lanes 0-1 are ready. More... | |
#define | XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK |
Lanes 0-3 are ready. More... | |
#define | XDP_TX_PHY_STATUS_LANES_READY_MASK(n) |
Macro for lanes ready mask with number of lanes as the argument. More... | |
#define | XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F |
DRP address. More... | |
#define | XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 |
DRP read/write command (Read=0, Write=1). More... | |
#define | XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 |
DRP write data. More... | |
#define | XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 |
Shift bits for DRP write data. More... | |
#define | XDP_TX_HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001 |
Disables bypass of the HDCP core. More... | |
DPRX core registers: Receiver core configuration. | |
#define | XDP_RX_LINK_ENABLE 0x000 |
Enable the receiver core. More... | |
#define | XDP_RX_AUX_CLK_DIVIDER 0x004 |
Clock divider value for generating the internal 1MHz clock. More... | |
#define | XDP_RX_AUX_DEFER_SHIFT 24 |
Aux defer. More... | |
#define | XDP_RX_LINE_RESET_DISABLE 0x008 |
RX line reset disable. More... | |
#define | XDP_RX_DTG_ENABLE 0x00C |
Enables the display timing generator (DTG). More... | |
#define | XDP_RX_USER_PIXEL_WIDTH 0x010 |
Selects the width of the user data input port. More... | |
#define | XDP_RX_INTERRUPT_MASK 0x014 |
Masks the specified interrupt sources for stream 1. More... | |
#define | XDP_RX_MISC_CTRL 0x018 |
Miscellaneous control of RX behavior. More... | |
#define | XDP_RX_SOFT_RESET 0x01C |
Software reset. More... | |
DPRX core registers: AUX channel status. | |
#define | XDP_RX_AUX_REQ_IN_PROGRESS 0x020 |
Indicates the receipt of an AUX channel request. More... | |
#define | XDP_RX_REQ_ERROR_COUNT 0x024 |
Provides a running total of errors detected on inbound AUX channel requests. More... | |
#define | XDP_RX_REQ_COUNT 0x028 |
Provides a running total of the number of AUX requests received. More... | |
#define | XDP_RX_HPD_INTERRUPT 0x02C |
Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal. More... | |
#define | XDP_RX_REQ_CLK_WIDTH 0x030 |
Holds the half period of the recovered AUX clock. More... | |
#define | XDP_RX_REQ_CMD 0x034 |
Provides the most recent AUX command received. More... | |
#define | XDP_RX_REQ_ADDRESS 0x038 |
Contains the address field of the most recent AUX request. More... | |
#define | XDP_RX_REQ_LENGTH 0x03C |
Contains length of the most recent AUX request. More... | |
DPRX core registers: Interrupt registers. | |
#define | XDP_RX_INTERRUPT_CAUSE 0x040 |
Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel. More... | |
#define | XDP_RX_INTERRUPT_MASK_1 0x044 |
Masks the specified interrupt sources for streams 2, 3, 4. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1 0x048 |
Indicates the cause of a pending host interrupts for streams 2, 3, 4. More... | |
DPRX core registers: DPCD fields. | |
#define | XDP_RX_LOCAL_EDID_VIDEO 0x084 |
Indicates the presence of EDID information for the video stream. More... | |
#define | XDP_RX_LOCAL_EDID_AUDIO 0x088 |
Indicates the presence of EDID information for the audio stream. More... | |
#define | XDP_RX_REMOTE_CMD 0x08C |
Used for passing remote information to the DisplayPort TX. More... | |
#define | XDP_RX_DEVICE_SERVICE_IRQ 0x090 |
Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state. More... | |
#define | XDP_RX_VIDEO_UNSUPPORTED 0x094 |
DPCD register bit to inform the DisplayPort TX that video data is not supported. More... | |
#define | XDP_RX_AUDIO_UNSUPPORTED 0x098 |
DPCD register bit to inform the DisplayPort TX that audio data is not supported. More... | |
#define | XDP_RX_OVER_LINK_BW_SET 0x09C |
Used to override the main link bandwidth setting in the DPCD. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET 0x0A0 |
Used to override the lane count setting in the DPCD. More... | |
#define | XDP_RX_OVER_TP_SET 0x0A4 |
Used to override the link training pattern in the DPCD. More... | |
#define | XDP_RX_OVER_TRAINING_LANE0_SET 0x0A8 |
Used to override the TRAINING_LANE0_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_TRAINING_LANE1_SET 0x0AC |
Used to override the TRAINING_LANE1_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_TRAINING_LANE2_SET 0x0B0 |
Used to override the TRAINING_LANE2_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_TRAINING_LANE3_SET 0x0B4 |
Used to override the TRAINING_LANE3_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_CTRL_DPCD 0x0B8 |
Used to enable AXI/APB write access to the DPCD capability structure. More... | |
#define | XDP_RX_OVER_DOWNSPREAD_CTRL 0x0BC |
Used to override downspread control in the DPCD. More... | |
#define | XDP_RX_OVER_LINK_QUAL_LANE0_SET 0x0C0 |
Used to override the LINK_QUAL_LANE0_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_LINK_QUAL_LANE1_SET 0x0C4 |
Used to override the LINK_QUAL_LANE1_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_LINK_QUAL_LANE2_SET 0x0C8 |
Used to override the LINK_QUAL_LANE2_SET register in the DPCD. More... | |
#define | XDP_RX_OVER_LINK_QUAL_LANE3_SET 0x0CC |
Used to override the LINK_QUAL_LANE3_SET register in the DPCD. More... | |
#define | XDP_RX_MST_CAP 0x0D0 |
Used to enable or disable MST capability. More... | |
#define | XDP_RX_SINK_COUNT 0x0D4 |
The sink device count. More... | |
#define | XDP_RX_GUID0 0x0E0 |
Lower 4 bytes of the DPCD's GUID field. More... | |
#define | XDP_RX_GUID1 0x0E4 |
Bytes 4 to 7 of the DPCD's GUID field. More... | |
#define | XDP_RX_GUID2 0x0E8 |
Bytes 8 to 11 of the DPCD's GUID field. More... | |
#define | XDP_RX_GUID3 0x0EC |
Upper 4 bytes of the DPCD's GUID field. More... | |
#define | XDP_RX_OVER_GUID 0x0F0 |
Used to override the GUID field in the DPCD with what is stored in XDP_RX_GUID[0-3]. More... | |
DPRX core registers: Core ID. | |
#define | XDP_RX_VERSION 0x0F8 |
Version and revision of the DisplayPort core. More... | |
#define | XDP_RX_CORE_ID 0x0FC |
DisplayPort protocol version and revision. More... | |
DPRX core registers: User video status. | |
#define | XDP_RX_USER_FIFO_OVERFLOW 0x110 |
Indicates an overflow in user FIFO. More... | |
#define | XDP_RX_USER_VSYNC_STATE 0x114 |
Provides a mechanism for the host processor to monitor the state of the video data path. More... | |
DPRX core registers: PHY configuration and status. | |
#define | XDP_RX_PHY_CONFIG 0x200 |
Transceiver PHY reset and configuration. More... | |
#define | XDP_RX_PHY_STATUS 0x208 |
Current PHY status. More... | |
#define | XDP_RX_PHY_POWER_DOWN 0x210 |
Control PHY power down. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING 0x214 |
Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training. More... | |
#define | XDP_RX_CDR_CONTROL_CONFIG 0x21C |
Control the configuration for clock and data recovery. More... | |
#define | XDP_RX_BS_IDLE_TIME 0x220 |
Blanking start symbol idle time - this value is loaded as a timeout counter for detecting cable disconnect or unplug events. More... | |
#define | XDP_RX_GT_DRP_COMMAND 0x2A0 |
Provides access to the GT DRP ports. More... | |
#define | XDP_RX_GT_DRP_READ_DATA 0x2A4 |
Provides access to GT DRP read data. More... | |
#define | XDP_RX_GT_DRP_CH_STATUS 0x2A8 |
Provides access to GT DRP channel status. More... | |
DPRX core registers: Audio. | |
#define | XDP_RX_AUDIO_CONTROL 0x300 |
Enables audio stream packets in main link. More... | |
#define | XDP_RX_AUDIO_INFO_DATA(NUM) (0x304 + 4 * (NUM - 1)) |
Word formatted as per CEA 861-C info frame. More... | |
#define | XDP_RX_AUDIO_MAUD 0x324 |
M value of audio stream as decoded from audio time stamp packet. More... | |
#define | XDP_RX_AUDIO_NAUD 0x328 |
N value of audio stream as decoded from audio time stamp packet. More... | |
#define | XDP_RX_AUDIO_STATUS 0x32C |
Status of audio stream. More... | |
#define | XDP_RX_AUDIO_EXT_DATA(NUM) (0x330 + 4 * (NUM - 1)) |
Word formatted as per extension packet. More... | |
DPRX core registers: DPCD configuration space. | |
#define | XDP_RX_DPCD_LINK_BW_SET 0x400 |
Current link bandwidth setting as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_LANE_COUNT_SET 0x404 |
Current lane count setting as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_ENHANCED_FRAME_EN 0x408 |
Current setting for enhanced framing symbol mode as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_TRAINING_PATTERN_SET 0x40C |
Current training pattern setting as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 |
Current value of the link quality pattern field as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 |
Value of the output clock enable field as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_SCRAMBLING_DISABLE 0x418 |
Value of the scrambling disable field as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C |
Current value of the symbol error count select field as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_TRAINING_LANE_0_SET 0x420 |
The RX DPCD value used by the TX during link training to configure the RX PHY lane 0. More... | |
#define | XDP_RX_DPCD_TRAINING_LANE_1_SET 0x424 |
The RX DPCD value used by the TX during link training to configure the RX PHY lane 1. More... | |
#define | XDP_RX_DPCD_TRAINING_LANE_2_SET 0x428 |
The RX DPCD value used by the TX during link training to configure the RX PHY lane 2. More... | |
#define | XDP_RX_DPCD_TRAINING_LANE_3_SET 0x42C |
The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3. More... | |
#define | XDP_RX_DPCD_DOWNSPREAD_CONTROL 0x430 |
The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled. More... | |
#define | XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 |
8B/10B encoding setting as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_SET_POWER_STATE 0x438 |
Power state requested by the TX as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_LANE01_STATUS 0x43C |
Link training status for lanes 0 and 1 as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_LANE23_STATUS 0x440 |
Link training status for lanes 2 and 3 as exposed in the RX DPCD. More... | |
#define | XDP_RX_DPCD_SOURCE_OUI_VALUE |
#define | XDP_RX_DPCD_SYM_ERR_CNT01 |
#define | XDP_RX_DPCD_SYM_ERR_CNT23 |
DPRX core registers: Main stream attributes for SST / MST STREAM1. | |
#define | XDP_RX_STREAM1_MSA_START 0x500 |
Start of the MSA registers for stream 1. More... | |
#define | XDP_RX_MSA_HRES 0x500 |
Number of active pixels per line (the horizontal resolution). More... | |
#define | XDP_RX_MSA_HSPOL 0x504 |
The horizontal sync polarity. More... | |
#define | XDP_RX_MSA_HSWIDTH 0x508 |
Width of the horizontal sync pulse. More... | |
#define | XDP_RX_MSA_HSTART 0x50C |
Number of clocks between the leading edge of the horizontal sync and the start of active data. More... | |
#define | XDP_RX_MSA_HTOTAL 0x510 |
Total number of clocks in the horizontal framing period. More... | |
#define | XDP_RX_MSA_VHEIGHT 0x514 |
Number of active lines (the vertical resolution). More... | |
#define | XDP_RX_MSA_VSPOL 0x518 |
The vertical sync polarity. More... | |
#define | XDP_RX_MSA_VSWIDTH 0x51C |
Width of the vertical sync pulse. More... | |
#define | XDP_RX_MSA_VSTART 0x520 |
Number of lines between the leading edge of the vertical sync and the first line of active data. More... | |
#define | XDP_RX_MSA_VTOTAL 0x524 |
Total number of lines in the video frame. More... | |
#define | XDP_RX_MSA_MISC0 0x528 |
Miscellaneous stream attributes. More... | |
#define | XDP_RX_MSA_MISC1 0x52C |
Miscellaneous stream attributes. More... | |
#define | XDP_RX_MSA_MVID 0x530 |
Used to recover the video clock from the link clock. More... | |
#define | XDP_RX_MSA_NVID 0x534 |
Used to recover the video clock from the link clock. More... | |
#define | XDP_RX_MSA_VBID 0x538 |
The most recently received VB-ID value. More... | |
DPRX core registers: Main stream attributes for MST STREAM2, 3, and 4. | |
#define | XDP_RX_STREAM2_MSA_START 0x540 |
Start of the MSA registers for stream 2. More... | |
#define | XDP_RX_STREAM2_MSA_START_OFFSET |
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. More... | |
#define | XDP_RX_STREAM3_MSA_START 0x580 |
Start of the MSA registers for stream 3. More... | |
#define | XDP_RX_STREAM3_MSA_START_OFFSET |
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. More... | |
#define | XDP_RX_STREAM4_MSA_START 0x5C0 |
Start of the MSA registers for stream 4. More... | |
#define | XDP_RX_STREAM4_MSA_START_OFFSET |
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. More... | |
DPRX core registers: DPCD registers for HDCP. | |
#define | XDP_RX_DPCD_HDCP_TABLE 0x900 |
HDCP register table (0x100 bytes). More... | |
DPRX core registers: MST field for sideband message buffers and the | |
#define | XDP_RX_DOWN_REQ 0xA00 |
Down request buffer address space. More... | |
#define | XDP_RX_DOWN_REP 0xB00 |
Down reply buffer address space. More... | |
#define | XDP_RX_VC_PAYLOAD_TABLE 0x800 |
Virtual channel payload table (0xFF bytes). More... | |
#define | XDP_RX_VC_PAYLOAD_TABLE_ID_SLOT(SlotNum) (XDP_RX_VC_PAYLOAD_TABLE + SlotNum) |
DPRX core registers: Vendor specific DPCD. | |
#define | XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 |
User access to the source specific field as exposed in the RX DPCD (0xFF bytes). More... | |
#define | XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD_REG(RegNum) (XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) |
#define | XDP_RX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 |
User access to the sink specific field as exposed in the RX DPCD (0xFF bytes). More... | |
#define | XDP_RX_SINK_DEVICE_SPECIFIC_FIELD_REG(RegNum) (XDP_RX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum)) |
DPRX core masks, shifts, and register values. | |
#define | XDP_RX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
Clock divider value. More... | |
#define | XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
AUX (noise) signal width filter. More... | |
#define | XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
Shift bits for AUX signal width filter. More... | |
#define | XDP_RX_LINE_RESET_DISABLE_MASK(Stream) (1 << ((Stream) - XDP_TX_STREAM_ID1)) |
Used to disable the end of the line reset to the internal video pipe. More... | |
#define | XDP_RX_USER_PIXEL_WIDTH_1 0x1 |
Single pixel wide interface. More... | |
#define | XDP_RX_USER_PIXEL_WIDTH_2 0x2 |
Dual pixel output mode. More... | |
#define | XDP_RX_USER_PIXEL_WIDTH_4 0x4 |
Quad pixel output mode. More... | |
#define | XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK 0x00000001 |
Mask the interrupt assertion for a resolution change, as detected from the MSA fields. More... | |
#define | XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK 0x00000002 |
Mask the interrupt assertion for a power state change. More... | |
#define | XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK 0x00000004 |
Mask the interrupt assertion for the no-video condition being detected after active video received. More... | |
#define | XDP_RX_INTERRUPT_MASK_VBLANK_MASK 0x00000008 |
Mask the interrupt assertion for the start of the blanking interval. More... | |
#define | XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK 0x00000010 |
Mask the interrupt assertion for training loss on active lanes. More... | |
#define | XDP_RX_INTERRUPT_MASK_VIDEO_MASK 0x00000040 |
Mask the interrupt assertion for a valid video frame being detected on the main link. More... | |
#define | XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK 0x00000100 |
Mask the interrupt assertion for an audio info packet being received. More... | |
#define | XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK 0x00000200 |
Mask the interrupt assertion for an audio extension packet being received. More... | |
#define | XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK 0x00000400 |
Mask the interrupt assertion for a virtual channel payload being allocated. More... | |
#define | XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK 0x00000800 |
Mask the interrupt assertion for a virtual channel payload being allocated. More... | |
#define | XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK 0x00001000 |
Mask the interrupt assertion for a downstream reply being ready. More... | |
#define | XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK 0x00002000 |
Mask the interrupt assertion for a downstream request being ready. More... | |
#define | XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK 0x00004000 |
Mask the interrupt assertion for link training completion. More... | |
#define | XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK 0x00008000 |
Mask the interrupt assertion for a change in bandwidth. More... | |
#define | XDP_RX_INTERRUPT_MASK_TP1_MASK 0x00010000 |
Mask the interrupt assertion for start of training pattern 1. More... | |
#define | XDP_RX_INTERRUPT_MASK_TP2_MASK 0x00020000 |
Mask the interrupt assertion for start of training pattern 2. More... | |
#define | XDP_RX_INTERRUPT_MASK_TP3_MASK 0x00040000 |
Mask the interrupt assertion for start of training pattern 3. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_DEBUG_WRITE_MASK 0x00080000 |
Mask the interrupt for a write to any HDCP debug register. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_AKSV_WRITE_MASK 0x00100000 |
Mask the interrupt for a write to the HDCP AKSV MSB register. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_AN_WRITE_MASK 0x00200000 |
Mask the interrupt for a write to the HDCP An MSB register. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_AINFO_WRITE_MASK 0x00400000 |
Mask the interrupt for a write to the HDCP AInfo register. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_RO_READ_MASK 0x00800000 |
Mask the interrupt for a read of the HDCP Ro register. More... | |
#define | XDP_RX_INTERRUPT_MASK_HDCP_BINFO_READ_MASK 0x01000000 |
Mask the interrupt for a read of the HDCP BInfo register. More... | |
#define | XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK 0x08000000 |
Mask the interrupt assertion caused for an audio packet overflow. More... | |
#define | XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK 0x10000000 |
Mask the interrupt assertion for the RX's DPCD payload allocation registers that have been updated as part of (de-)allocation or partial deletion. More... | |
#define | XDP_RX_INTERRUPT_MASK_ACT_RX_MASK 0x20000000 |
Mask the interrupt assertion for the ACT sequence being received. More... | |
#define | XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK 0x40000000 |
Mask the interrupt assertion for the start of a CRC test. More... | |
#define | XDP_RX_INTERRUPT_MASK_UNPLUG_MASK 0x80000000 |
Mask the unplug event interrupt. More... | |
#define | XDP_RX_INTERRUPT_MASK_ALL_MASK 0xF9FFFFFF |
Mask all interrupts. More... | |
#define | XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK 0x1 |
When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally. More... | |
#define | XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK 0x2 |
When set, the long I2C write data transfers are responded to using DEFER instead of partial ACKs. More... | |
#define | XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK 0x4 |
When set, I2C DEFERs will be sent as AUX DEFERs to the source device. More... | |
#define | XDP_RX_SOFT_RESET_VIDEO_MASK 0x01 |
Reset the video logic. More... | |
#define | XDP_RX_SOFT_RESET_AUX_MASK 0x80 |
Reset the AUX logic. More... | |
#define | XDP_RX_HPD_INTERRUPT_ASSERT_MASK 0x00000001 |
Instructs the RX core to assert an interrupt to the TX using the HPD signal. More... | |
#define | XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK 0xFFFF0000 |
The length of the HPD pulse to generate (in microseconds). More... | |
#define | XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 |
Shift bits for the HPD pulse length. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK |
Interrupt caused by a resolution change, as detected from the MSA fields. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK |
Interrupt caused by a power state change. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK |
Interrupt caused by the no-video condition being detected after active video received. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK XDP_RX_INTERRUPT_MASK_VBLANK_MASK |
Interrupt caused by the start of the blanking interval. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK |
Interrupt caused by training loss on active lanes. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK XDP_RX_INTERRUPT_MASK_VIDEO_MASK |
Interrupt caused by a valid video frame being detected on the main link. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK |
Interrupt caused by an audio info packet being received. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK |
Interrupt caused by an audio extension packet being received. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK |
Interrupt caused by a virtual channel payload being allocated. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK |
Interrupt caused by a virtual channel payload being allocated. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK |
Interrupt caused by a downstream reply being ready. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK |
Interrupt caused by a downstream request being ready. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK |
Interrupt caused by link training completion. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK |
Interrupt caused by a change in bandwidth. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_TP1_MASK XDP_RX_INTERRUPT_MASK_TP1_MASK |
Interrupt caused by the start of training pattern 1. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_TP2_MASK XDP_RX_INTERRUPT_MASK_TP2_MASK |
Interrupt caused by the start of training pattern 2. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_TP3_MASK XDP_RX_INTERRUPT_MASK_TP3_MASK |
Interrupt caused by the start of training pattern 3. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_AUDIO_OVER_MASK XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK |
Interrupt caused by an audio packet overflow. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_PAYLOAD_ALLOC_MASK XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK |
Interrupt caused by the RX's DPCD payload allocation registers has been updated as part of (de-)allocation or partial deletion. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_ACT_RX_MASK XDP_RX_INTERRUPT_MASK_ACT_RX_MASK |
Interrupt caused by the ACT sequence being received. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_CRC_TEST_MASK XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK |
Interrupt caused by the start of a CRC test. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_UNPLUG_MASK XDP_RX_INTERRUPT_MASK_UNPLUG_MASK |
Interrupt caused by the an unplug event. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK(Stream) (0x00001 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK(Stream) (0x00002 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK(Stream) (0x00004 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK(Stream) (0x00008 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK(Stream) (0x00010 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or. More... | |
#define | XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK(Stream) (0x00020 << ((Stream - 2) * 6)) |
Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) |
Interrupt caused by an audio extension packet being received for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) |
Interrupt caused by an audio info packet being received for stream 2, 3, or. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) |
Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) |
Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) |
Interrupt caused by the start of the blanking interval for stream 2, 3, or. More... | |
#define | XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) |
Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4. More... | |
#define | XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK 0x00FF |
Specifies the number of clock cycles the horizontal sync pulse is asserted. More... | |
#define | XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK 0xFF00 |
Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch). More... | |
#define | XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 |
Shift bits for the front porch. More... | |
#define | XDP_RX_MST_ALLOC_VCP_ID_MASK 0x00003F |
The virtual channel payload ID that was issued as part of the most recent ALLOCATE_PAYLOAD down request. More... | |
#define | XDP_RX_MST_ALLOC_START_TS_MASK 0x003F00 |
The starting time slot that was issued as part of the most recent ALLOCATE_PAYLOAD down request. More... | |
#define | XDP_RX_MST_ALLOC_START_TS_SHIFT 8 |
Shift bits for the starting time slot. More... | |
#define | XDP_RX_MST_ALLOC_COUNT_TS_MASK 0x3F0000 |
The time slot count that was issued as part of part of the most recent ALLOCATE_PAYLOAD down request. More... | |
#define | XDP_RX_MST_ALLOC_COUNT_TS_SHIFT 16 |
Shift bits for the time slot count. More... | |
#define | XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK 0x01 |
Indicates that a new command is present in the REMOTE_CMD register. More... | |
#define | XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK 0x02 |
Reflects the SINK_SPECIFIC_IRQ state. More... | |
#define | XDP_RX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK 0x04 |
Generates a CP IRQ event. More... | |
#define | XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK 0x10 |
Indicates a new DOWN_REPLY buffer message is ready. More... | |
#define | XDP_RX_OVER_LINK_BW_SET_162GBPS 0x06 |
1.62 Gbps link rate. More... | |
#define | XDP_RX_OVER_LINK_BW_SET_270GBPS 0x0A |
2.70 Gbps link rate. More... | |
#define | XDP_RX_OVER_LINK_BW_SET_540GBPS 0x14 |
5.40 Gbps link rate. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_MASK 0x1F |
The lane count override value. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_1 0x1 |
Lane count of 1. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_2 0x2 |
Lane count of 2. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_4 0x4 |
Lane count of 4. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK 0x40 |
Capability override for training pattern 3. More... | |
#define | XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK 0x80 |
Capability override for enhanced framing. More... | |
#define | XDP_RX_OVER_TP_SET_TP_SELECT_MASK 0x0003 |
Training pattern select override. More... | |
#define | XDP_RX_OVER_TP_SET_LQP_SET_MASK 0x000C |
Link quality pattern set override. More... | |
#define | XDP_RX_OVER_TP_SET_LQP_SET_SHIFT 2 |
Shift bits for link quality pattern set override. More... | |
#define | XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK 0x0010 |
Recovered clock output enable override. More... | |
#define | XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK 0x0020 |
Scrambling disable override. More... | |
#define | XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK 0x00C0 |
Symbol error count override. More... | |
#define | XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT 6 |
Shift bits for symbol error count override. More... | |
#define | XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK 0xFF00 |
Training AUX read interval override. More... | |
#define | XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT 8 |
Shift bits for training AUX read interval override. More... | |
#define | XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK 0x03 |
Voltage swing set override. More... | |
#define | XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 |
Maximum voltage swing override. More... | |
#define | XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK 0x18 |
Pre-emphasis set override. More... | |
#define | XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT 3 |
Shift bits for pre-emphasis set override. More... | |
#define | XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 |
Maximum pre-emphasis override. More... | |
#define | XDP_RX_MST_CAP_ENABLE_MASK 0x001 |
When set to 1, enables MST mode in the RX, or disables it when 0. More... | |
#define | XDP_RX_MST_CAP_SOFT_VCP_MASK 0x002 |
When set to 1, enables software control over the virtual channel payload table. More... | |
#define | XDP_RX_MST_CAP_OVER_ACT_MASK 0x004 |
When set to 1, overrides the ACT trigger. More... | |
#define | XDP_RX_MST_CAP_VCP_UPDATE_MASK 0x010 |
When set to 1, indicates to the upstream device that the virtual channel payload table has been updated. More... | |
#define | XDP_RX_MST_CAP_VCP_CLEAR_MASK 0x100 |
When set to 1, clears the virtual channel payload table. More... | |
#define | XDP_RX_VERSION_INTER_REV_MASK 0x0000000F |
Internal revision. More... | |
#define | XDP_RX_VERSION_CORE_PATCH_MASK 0x00000030 |
Core patch details. More... | |
#define | XDP_RX_VERSION_CORE_PATCH_SHIFT 8 |
Shift bits for core patch details. More... | |
#define | XDP_RX_VERSION_CORE_VER_REV_MASK 0x000000C0 |
Core version revision. More... | |
#define | XDP_RX_VERSION_CORE_VER_REV_SHIFT 12 |
Shift bits for core version revision. More... | |
#define | XDP_RX_VERSION_CORE_VER_MNR_MASK 0x00000F00 |
Core minor version. More... | |
#define | XDP_RX_VERSION_CORE_VER_MNR_SHIFT 16 |
Shift bits for core minor version. More... | |
#define | XDP_RX_VERSION_CORE_VER_MJR_MASK 0x0000F000 |
Core major version. More... | |
#define | XDP_RX_VERSION_CORE_VER_MJR_SHIFT 24 |
Shift bits for core major version. More... | |
#define | XDP_RX_CORE_ID_TYPE_MASK 0x0000000F |
Core type. More... | |
#define | XDP_RX_CORE_ID_TYPE_TX 0x0 |
Core is a transmitter. More... | |
#define | XDP_RX_CORE_ID_TYPE_RX 0x1 |
Core is a receiver. More... | |
#define | XDP_RX_CORE_ID_DP_REV_MASK 0x000000F0 |
DisplayPort protocol revision. More... | |
#define | XDP_RX_CORE_ID_DP_REV_SHIFT 8 |
Shift bits for DisplayPort protocol revision. More... | |
#define | XDP_RX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 |
DisplayPort protocol minor version. More... | |
#define | XDP_RX_CORE_ID_DP_MNR_VER_SHIFT 16 |
Shift bits for DisplayPort protocol major version. More... | |
#define | XDP_RX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 |
DisplayPort protocol major version. More... | |
#define | XDP_RX_CORE_ID_DP_MJR_VER_SHIFT 24 |
Shift bits for DisplayPort protocol major version. More... | |
#define | XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK(Stream) (Stream) |
Indicates that the internal FIFO has detected on overflow condition for the specified stream. More... | |
#define | XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK(Stream) (Stream << 4) |
Indicates that the video unpack FIFO has overflown for the specified stream. More... | |
#define | XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK(Stream) (Stream << 8) |
Indicates that the video timing FIFO has overflown for the specified stream. More... | |
#define | XDP_RX_USER_VSYNC_STATE_STREAMX_MASK(Stream) (Stream) |
The state of the vertical sync pulse for the specified stream. More... | |
#define | XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x00000000 |
Release reset. More... | |
#define | XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK 0x00000001 |
Hold the GTPLL in reset. More... | |
#define | XDP_RX_PHY_CONFIG_GTRX_RESET_MASK 0x00000002 |
Hold GTRXRESET in reset. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK 0x00000100 |
Hold RX_PHY_PMA reset. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK 0x00000200 |
Hold RX_PHY_PCS reset. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK 0x00000400 |
Hold RX_PHY_BUF reset. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK 0x00000800 |
Hold RX_PHY_DFE_LPM reset. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK 0x00001000 |
Set RX_PHY_POLARITY. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK 0x0000E000 |
Set RX_PHY_LOOPBACK. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK 0x00010000 |
Set RX_PHY_EYESCANRESET. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK 0x00020000 |
Set RX_PHY_ EYESCANTRIGGER. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK 0x00040000 |
Set RX_PHY_PRBSCNTRESET. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK 0x00080000 |
Set RX_PHY_RXLPMHFHOLD. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK 0x00100000 |
Set RX_PHY_RXLPMLFHOLD. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK 0x00200000 |
Set RX_PHY_ RXLPMHFOVERDEN. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK 0x00400000 |
Set RX_PHY_CDRHOLD. More... | |
#define | XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK 0x00800000 |
Issue reset at every training iteration. More... | |
#define | XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK 0x01000000 |
Issue reset at every link rate change. More... | |
#define | XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK 0x02000000 |
Issue reset at start of training pattern 1. More... | |
#define | XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK 0x04000000 |
Enable the individual lane polarity. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK 0x08000000 |
Configure RX_PHY_POLARITY for lane 0. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK 0x10000000 |
Configure RX_PHY_POLARITY for lane 1. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK 0x20000000 |
Configure RX_PHY_POLARITY for lane 2. More... | |
#define | XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK 0x40000000 |
Configure RX_PHY_POLARITY for lane 3. More... | |
#define | XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK 0x00000003 |
Reset GT and PHY. More... | |
#define | XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 |
Reset done for lanes 0 and 1. More... | |
#define | XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C |
Reset done for lanes 2 and 3. More... | |
#define | XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 |
Shift bits for reset done for lanes 2 and 3. More... | |
#define | XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 |
PLL locked for lanes 0 and 1. More... | |
#define | XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 |
PLL locked for lanes 2 and 3. More... | |
#define | XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 |
FPGA fabric clock PLL locked. More... | |
#define | XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK 0x00000080 |
Receiver clock locked. More... | |
#define | XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK 0x00000100 |
PRBS error on lane 0. More... | |
#define | XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK 0x00000200 |
PRBS error on lane 1. More... | |
#define | XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK 0x00000400 |
PRBS error on lane 2. More... | |
#define | XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK 0x00000800 |
PRBS error on lane 3. More... | |
#define | XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK 0x00001000 |
RX voltage low on lane 0. More... | |
#define | XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK 0x00002000 |
RX voltage low on lane. More... | |
#define | XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK 0x00004000 |
RX voltage low on lane. More... | |
#define | XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK 0x00008000 |
RX voltage low on lane. More... | |
#define | XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK 0x00010000 |
Lane alignment status for lane 0. More... | |
#define | XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK 0x00020000 |
Lane alignment status for lane 1. More... | |
#define | XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK 0x00040000 |
Lane alignment status for lane 2. More... | |
#define | XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK 0x00080000 |
Lane alignment status for lane 3. More... | |
#define | XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK 0x00100000 |
Symbol lock status for lane 0. More... | |
#define | XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK 0x00200000 |
Symbol lock status for lane 1. More... | |
#define | XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK 0x00400000 |
Symbol lock status for lane 2. More... | |
#define | XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK 0x00800000 |
Symbol lock status for lane 3. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK 0x03000000 |
RX buffer status lane 0. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT 24 |
Shift bits for RX buffer status lane 0. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK 0x0C000000 |
RX buffer status lane 1. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT 26 |
Shift bits for RX buffer status lane 1. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK 0x30000000 |
RX buffer status lane 2. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT 28 |
Shift bits for RX buffer status lane 2. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK 0xC0000000 |
RX buffer status lane 3. More... | |
#define | XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT 30 |
Shift bits for RX buffer status lane 3. More... | |
#define | XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK 0x00000013 |
Lanes 0 and 1 are ready. More... | |
#define | XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F |
All lanes are ready. More... | |
#define | XDP_RX_PHY_POWER_DOWN_LANE_0_MASK 0x1 |
Power down the PHY for lane 0. More... | |
#define | XDP_RX_PHY_POWER_DOWN_LANE_1_MASK 0x2 |
Power down the PHY for lane. More... | |
#define | XDP_RX_PHY_POWER_DOWN_LANE_2_MASK 0x4 |
Power down the PHY for lane. More... | |
#define | XDP_RX_PHY_POWER_DOWN_LANE_3_MASK 0x8 |
Power down the PHY for lane. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_MIN_MASK 0x000003 |
The minimum voltage swing level. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_MASK 0x00000C |
Clock recovery options. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_SHIFT 2 |
Shift bits for clock recovery options. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC 0x0 |
Increment voltage swing adjust request every training iteration. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC_4CNT 0x1 |
Increment voltage swing adjust request every 4 or VS_SWEEP_CNT iterations. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_HOLD 0x2 |
Hold adjust request to SET_VS. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_NA 0x3 |
Not applicable. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_MASK 0x000070 |
Voltage swing sweep count. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_SHIFT 4 |
Shift bits for voltage swing sweep count. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_SET_VS_MASK 0x000300 |
Set voltage swing level. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_SET_VS_SHIFT 8 |
Shift bits for voltage swing setting. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_MASK 0x000C00 |
Channel equalization options. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_SHIFT 10 |
Shift bits for channel equalization options. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_INC 0x0 |
Increment pre-emphasis adjust request every training iteration until maximum level, SET_PE, is reached. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_HOLD 0x1 |
Hold adjust request to SET_PE. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_TABLE 0x2 |
Pick pre-emphasis values from PE_TABLE. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_VS_NA 0x3 |
Not applicable. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_SET_PE_MASK 0x003000 |
Set pre-emphasis level. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_SET_PE_SHIFT 12 |
Shift bits for pre-emphasis setting. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_MASK(Iteration) (0x3 << (14 + ((Iteration - 1) * 2))) |
Table specifying what pre-emphasis level to request for each training iteration. More... | |
#define | XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_SHIFT(Iteration) (14 + ((Iteration - 1) * 2)) |
Shift bits for pre-emphasis table. More... | |
#define | XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_TO_MASK 0x000FFFFF |
Controls the CDR tDLOCK timeout value. More... | |
#define | XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_DP159 0x1388 |
CDR tDLOCK calibration value using DP159. More... | |
#define | XDP_RX_CDR_CONTROL_CONFIG_DFE_CTRL_MASK 0x80000000 |
Use DFE control. More... | |
#define | XDP_RX_CDR_CONTROL_CONFIG_DISABLE_TIMEOUT 0X40000000 |
Timeout for MST mode. More... | |
DisplayPort Configuration Data: Sink control field. | |
#define | XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 |
DisplayPort Configuration Data: Sideband message buffers. | |
#define | XDP_DPCD_DOWN_REQ 0x01000 |
#define | XDP_DPCD_UP_REP 0x01200 |
#define | XDP_DPCD_DOWN_REP 0x01400 |
#define | XDP_DPCD_UP_REQ 0x01600 |
Stream identification. | |
#define | XDP_TX_STREAM_ID1 1 |
#define | XDP_TX_STREAM_ID2 2 |
#define | XDP_TX_STREAM_ID3 3 |
#define | XDP_TX_STREAM_ID4 4 |
Register access macro definitions. | |
#define | XDp_In32 Xil_In32 |
#define | XDp_Out32 Xil_Out32 |
#define XDp_GetCoreType | ( | InstancePtr | ) |
#include <xdp.h>
This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX).
InstancePtr | is a pointer to the XDp instance. |
Referenced by XDp_CfgInitialize(), XDp_Initialize(), XDp_InterruptHandler(), XDp_RxAudioDis(), XDp_RxAudioEn(), XDp_RxAudioReset(), XDp_RxCheckLinkStatus(), XDp_RxDtgDis(), XDp_RxDtgEn(), XDp_RxGenerateHpdInterrupt(), XDp_RxGetBpc(), XDp_RxGetColorComponent(), XDp_RxGetIicMapEntry(), XDp_RxHandleDownReq(), XDp_RxInterruptDisable(), XDp_RxInterruptEnable(), XDp_RxMstExposePort(), XDp_RxMstSetInputPort(), XDp_RxMstSetPbn(), XDp_RxMstSetPort(), XDp_RxSetDpcdMap(), XDp_RxSetDrvIntrNoVideoHandler(), XDp_RxSetDrvIntrPowerStateHandler(), XDp_RxSetDrvIntrVideoHandler(), XDp_RxSetIicMapEntry(), XDp_RxSetIntrActRxHandler(), XDp_RxSetIntrAudioOverHandler(), XDp_RxSetIntrBwChangeHandler(), XDp_RxSetIntrCrcTestHandler(), XDp_RxSetIntrDownReplyHandler(), XDp_RxSetIntrDownReqHandler(), XDp_RxSetIntrExtPktHandler(), XDp_RxSetIntrHdcpAinfoWriteHandler(), XDp_RxSetIntrHdcpAksvWriteHandler(), XDp_RxSetIntrHdcpAnWriteHandler(), XDp_RxSetIntrHdcpBinfoReadHandler(), XDp_RxSetIntrHdcpDebugWriteHandler(), XDp_RxSetIntrHdcpRoReadHandler(), XDp_RxSetIntrInfoPktHandler(), XDp_RxSetIntrNoVideoHandler(), XDp_RxSetIntrPayloadAllocHandler(), XDp_RxSetIntrPowerStateHandler(), XDp_RxSetIntrTp1Handler(), XDp_RxSetIntrTp2Handler(), XDp_RxSetIntrTp3Handler(), XDp_RxSetIntrTrainingDoneHandler(), XDp_RxSetIntrTrainingLostHandler(), XDp_RxSetIntrUnplugHandler(), XDp_RxSetIntrVBlankHandler(), XDp_RxSetIntrVideoHandler(), XDp_RxSetIntrVmChangeHandler(), XDp_RxSetLaneCount(), XDp_RxSetLineReset(), XDp_RxSetLinkRate(), XDp_RxSetUserPixelWidth(), XDp_SelfTest(), XDp_TxAllocatePayloadStreams(), XDp_TxAllocatePayloadVcIdTable(), XDp_TxAuxRead(), XDp_TxAuxWrite(), XDp_TxCfgMainLinkMax(), XDp_TxCfgMsaEnSynchClkMode(), XDp_TxCfgMsaRecalculate(), XDp_TxCfgMsaSetBpc(), XDp_TxCfgMsaUseCustom(), XDp_TxCfgMsaUseEdidPreferredTiming(), XDp_TxCfgMsaUseStandardVideoMode(), XDp_TxCfgSetColorEncode(), XDp_TxCfgTxPeLevel(), XDp_TxCfgTxVsLevel(), XDp_TxCfgTxVsOffset(), XDp_TxCheckLinkStatus(), XDp_TxClearMsaValues(), XDp_TxClearPayloadVcIdTable(), XDp_TxDisableMainLink(), XDp_TxEnableMainLink(), XDp_TxEnableTrainAdaptive(), XDp_TxEstablishLink(), XDp_TxFindAccessibleDpDevices(), XDp_TxGetEdid(), XDp_TxGetEdidBlock(), XDp_TxGetGuid(), XDp_TxGetRemoteEdid(), XDp_TxGetRemoteEdidBlock(), XDp_TxGetRemoteEdidDispIdExt(), XDp_TxGetRemoteTiledDisplayDb(), XDp_TxGetRxCapabilities(), XDp_TxIicRead(), XDp_TxIicWrite(), XDp_TxIsConnected(), XDp_TxMstCapable(), XDp_TxMstCfgModeDisable(), XDp_TxMstCfgModeEnable(), XDp_TxMstCfgStreamDisable(), XDp_TxMstCfgStreamEnable(), XDp_TxMstDisable(), XDp_TxMstEnable(), XDp_TxMstStreamIsEnabled(), XDp_TxRemoteDpcdRead(), XDp_TxRemoteDpcdWrite(), XDp_TxRemoteIicRead(), XDp_TxRemoteIicWrite(), XDp_TxResetPhy(), XDp_TxSendSbMsgAllocatePayload(), XDp_TxSendSbMsgClearPayloadIdTable(), XDp_TxSendSbMsgEnumPathResources(), XDp_TxSendSbMsgLinkAddress(), XDp_TxSendSbMsgRemoteDpcdRead(), XDp_TxSendSbMsgRemoteDpcdWrite(), XDp_TxSendSbMsgRemoteIicRead(), XDp_TxSendSbMsgRemoteIicWrite(), XDp_TxSetDownspread(), XDp_TxSetDrvHpdEventHandler(), XDp_TxSetDrvHpdPulseHandler(), XDp_TxSetEnhancedFrameMode(), XDp_TxSetHasRedriverInPath(), XDp_TxSetHpdEventHandler(), XDp_TxSetHpdPulseHandler(), XDp_TxSetLaneCount(), XDp_TxSetLaneCountChangeCallback(), XDp_TxSetLinkRate(), XDp_TxSetLinkRateChangeCallback(), XDp_TxSetMsaHandler(), XDp_TxSetMsaValues(), XDp_TxSetPeVsAdjustCallback(), XDp_TxSetPhyPolarityAll(), XDp_TxSetPhyPolarityLane(), XDp_TxSetScrambler(), XDp_TxSetStreamSelectFromSinkList(), XDp_TxSetStreamSinkRad(), XDp_TxSetUserPixelWidth(), XDp_TxTopologySortSinksByTiling(), XDp_TxTopologySwapSinks(), and XDp_TxWriteGuid().
#define XDP_GUID_NBYTES 16 |
#include <xdp_hw.h>
The number of bytes for the global unique ID.
Referenced by XDp_TxGetGuid(), and XDp_TxWriteGuid().
#define XDP_MAX_NPORTS 16 |
#include <xdp_hw.h>
The maximum number of ports connected to a DisplayPort device.
#define XDp_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XDp_In32((BaseAddress) + (RegOffset)) |
#include <xdp_hw.h>
This is a low-level function that reads from the specified register.
BaseAddress | is the base address of the device. |
RegOffset | is the register offset to be read from. |
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_AUDIO_CONTROL 0x300 |
#include <xdp_hw.h>
Enables audio stream packets in main link.
#define XDP_RX_AUDIO_EXT_DATA | ( | NUM | ) | (0x330 + 4 * (NUM - 1)) |
#include <xdp_hw.h>
Word formatted as per extension packet.
#define XDP_RX_AUDIO_INFO_DATA | ( | NUM | ) | (0x304 + 4 * (NUM - 1)) |
#include <xdp_hw.h>
Word formatted as per CEA 861-C info frame.
#define XDP_RX_AUDIO_MAUD 0x324 |
#include <xdp_hw.h>
M value of audio stream as decoded from audio time stamp packet.
#define XDP_RX_AUDIO_NAUD 0x328 |
#include <xdp_hw.h>
N value of audio stream as decoded from audio time stamp packet.
#define XDP_RX_AUDIO_STATUS 0x32C |
#include <xdp_hw.h>
Status of audio stream.
#define XDP_RX_AUDIO_UNSUPPORTED 0x098 |
#include <xdp_hw.h>
DPCD register bit to inform the DisplayPort TX that audio data is not supported.
#define XDP_RX_AUX_CLK_DIVIDER 0x004 |
#include <xdp_hw.h>
Clock divider value for generating the internal 1MHz clock.
#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
#include <xdp_hw.h>
AUX (noise) signal width filter.
#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for AUX signal width filter.
#define XDP_RX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
#include <xdp_hw.h>
Clock divider value.
#define XDP_RX_AUX_DEFER_SHIFT 24 |
#include <xdp_hw.h>
Aux defer.
#define XDP_RX_AUX_REQ_IN_PROGRESS 0x020 |
#include <xdp_hw.h>
Indicates the receipt of an AUX channel request.
#define XDP_RX_BS_IDLE_TIME 0x220 |
#include <xdp_hw.h>
Blanking start symbol idle time - this value is loaded as a timeout counter for detecting cable disconnect or unplug events.
#define XDP_RX_CDR_CONTROL_CONFIG 0x21C |
#include <xdp_hw.h>
Control the configuration for clock and data recovery.
#define XDP_RX_CDR_CONTROL_CONFIG_DFE_CTRL_MASK 0x80000000 |
#include <xdp_hw.h>
Use DFE control.
#define XDP_RX_CDR_CONTROL_CONFIG_DISABLE_TIMEOUT 0X40000000 |
#include <xdp_hw.h>
Timeout for MST mode.
#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_DP159 0x1388 |
#include <xdp_hw.h>
CDR tDLOCK calibration value using DP159.
#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_TO_MASK 0x000FFFFF |
#include <xdp_hw.h>
Controls the CDR tDLOCK timeout value.
#define XDP_RX_CORE_ID 0x0FC |
#include <xdp_hw.h>
DisplayPort protocol version and revision.
#define XDP_RX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 |
#include <xdp_hw.h>
DisplayPort protocol major version.
#define XDP_RX_CORE_ID_DP_MJR_VER_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol major version.
#define XDP_RX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 |
#include <xdp_hw.h>
DisplayPort protocol minor version.
#define XDP_RX_CORE_ID_DP_MNR_VER_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol major version.
#define XDP_RX_CORE_ID_DP_REV_MASK 0x000000F0 |
#include <xdp_hw.h>
DisplayPort protocol revision.
#define XDP_RX_CORE_ID_DP_REV_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol revision.
#define XDP_RX_CORE_ID_TYPE_MASK 0x0000000F |
#include <xdp_hw.h>
Core type.
#define XDP_RX_CORE_ID_TYPE_RX 0x1 |
#include <xdp_hw.h>
Core is a receiver.
#define XDP_RX_CORE_ID_TYPE_TX 0x0 |
#include <xdp_hw.h>
Core is a transmitter.
#define XDP_RX_DEVICE_SERVICE_IRQ 0x090 |
#include <xdp_hw.h>
Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state.
#define XDP_RX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK 0x04 |
#include <xdp_hw.h>
Generates a CP IRQ event.
#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK 0x10 |
#include <xdp_hw.h>
Indicates a new DOWN_REPLY buffer message is ready.
#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK 0x01 |
#include <xdp_hw.h>
Indicates that a new command is present in the REMOTE_CMD register.
#define XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK 0x02 |
#include <xdp_hw.h>
Reflects the SINK_SPECIFIC_IRQ state.
#define XDP_RX_DOWN_REP 0xB00 |
#include <xdp_hw.h>
Down reply buffer address space.
#define XDP_RX_DOWN_REQ 0xA00 |
#include <xdp_hw.h>
Down request buffer address space.
#define XDP_RX_DPCD_DOWNSPREAD_CONTROL 0x430 |
#include <xdp_hw.h>
The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled.
#define XDP_RX_DPCD_ENHANCED_FRAME_EN 0x408 |
#include <xdp_hw.h>
Current setting for enhanced framing symbol mode as exposed in the RX DPCD.
#define XDP_RX_DPCD_HDCP_TABLE 0x900 |
#include <xdp_hw.h>
HDCP register table (0x100 bytes).
#define XDP_RX_DPCD_LANE01_STATUS 0x43C |
#include <xdp_hw.h>
Link training status for lanes 0 and 1 as exposed in the RX DPCD.
#define XDP_RX_DPCD_LANE23_STATUS 0x440 |
#include <xdp_hw.h>
Link training status for lanes 2 and 3 as exposed in the RX DPCD.
#define XDP_RX_DPCD_LANE_COUNT_SET 0x404 |
#include <xdp_hw.h>
Current lane count setting as exposed in the RX DPCD.
#define XDP_RX_DPCD_LINK_BW_SET 0x400 |
#include <xdp_hw.h>
Current link bandwidth setting as exposed in the RX DPCD.
#define XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET 0x410 |
#include <xdp_hw.h>
Current value of the link quality pattern field as exposed in the RX DPCD.
#define XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x434 |
#include <xdp_hw.h>
8B/10B encoding setting as exposed in the RX DPCD.
#define XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN 0x414 |
#include <xdp_hw.h>
Value of the output clock enable field as exposed in the RX DPCD.
#define XDP_RX_DPCD_SCRAMBLING_DISABLE 0x418 |
#include <xdp_hw.h>
Value of the scrambling disable field as exposed in the RX DPCD.
#define XDP_RX_DPCD_SET_POWER_STATE 0x438 |
#include <xdp_hw.h>
Power state requested by the TX as exposed in the RX DPCD.
#define XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT 0x41C |
#include <xdp_hw.h>
Current value of the symbol error count select field as exposed in the RX DPCD.
#define XDP_RX_DPCD_TRAINING_LANE_0_SET 0x420 |
#include <xdp_hw.h>
The RX DPCD value used by the TX during link training to configure the RX PHY lane 0.
#define XDP_RX_DPCD_TRAINING_LANE_1_SET 0x424 |
#include <xdp_hw.h>
The RX DPCD value used by the TX during link training to configure the RX PHY lane 1.
#define XDP_RX_DPCD_TRAINING_LANE_2_SET 0x428 |
#include <xdp_hw.h>
The RX DPCD value used by the TX during link training to configure the RX PHY lane 2.
#define XDP_RX_DPCD_TRAINING_LANE_3_SET 0x42C |
#include <xdp_hw.h>
The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3.
#define XDP_RX_DPCD_TRAINING_PATTERN_SET 0x40C |
#include <xdp_hw.h>
Current training pattern setting as exposed in the RX DPCD.
#define XDP_RX_DTG_ENABLE 0x00C |
#include <xdp_hw.h>
Enables the display timing generator (DTG).
#define XDP_RX_FAST_I2C_DIVIDER 0x060 |
#include <xdp_hw.h>
Fast I2C mode clock divider value.
#define XDP_RX_GT_DRP_CH_STATUS 0x2A8 |
#include <xdp_hw.h>
Provides access to GT DRP channel status.
#define XDP_RX_GT_DRP_COMMAND 0x2A0 |
#include <xdp_hw.h>
Provides access to the GT DRP ports.
#define XDP_RX_GT_DRP_READ_DATA 0x2A4 |
#include <xdp_hw.h>
Provides access to GT DRP read data.
#define XDP_RX_GUID0 0x0E0 |
#include <xdp_hw.h>
Lower 4 bytes of the DPCD's GUID field.
#define XDP_RX_GUID1 0x0E4 |
#include <xdp_hw.h>
Bytes 4 to 7 of the DPCD's GUID field.
#define XDP_RX_GUID2 0x0E8 |
#include <xdp_hw.h>
Bytes 8 to 11 of the DPCD's GUID field.
#define XDP_RX_GUID3 0x0EC |
#include <xdp_hw.h>
Upper 4 bytes of the DPCD's GUID field.
#define XDP_RX_HPD_INTERRUPT 0x02C |
#include <xdp_hw.h>
Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal.
#define XDP_RX_HPD_INTERRUPT_ASSERT_MASK 0x00000001 |
#include <xdp_hw.h>
Instructs the RX core to assert an interrupt to the TX using the HPD signal.
#define XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK 0xFFFF0000 |
#include <xdp_hw.h>
The length of the HPD pulse to generate (in microseconds).
#define XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for the HPD pulse length.
#define XDP_RX_HSYNC_WIDTH 0x050 |
#include <xdp_hw.h>
Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG).
#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK 0xFF00 |
#include <xdp_hw.h>
Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch).
#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for the front porch.
#define XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK 0x00FF |
#include <xdp_hw.h>
Specifies the number of clock cycles the horizontal sync pulse is asserted.
#define XDP_RX_INTERRUPT_CAUSE 0x040 |
#include <xdp_hw.h>
Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel.
#define XDP_RX_INTERRUPT_CAUSE_1 0x048 |
#include <xdp_hw.h>
Indicates the cause of a pending host interrupts for streams 2, 3, 4.
#define XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) |
#include <xdp_hw.h>
Interrupt caused by an audio extension packet being received for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) |
#define XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) |
#include <xdp_hw.h>
Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) |
#define XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) |
#include <xdp_hw.h>
Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK | ( | Stream | ) | XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) |
#include <xdp_hw.h>
Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_CAUSE_ACT_RX_MASK XDP_RX_INTERRUPT_MASK_ACT_RX_MASK |
#include <xdp_hw.h>
Interrupt caused by the ACT sequence being received.
#define XDP_RX_INTERRUPT_CAUSE_AUDIO_OVER_MASK XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK |
#include <xdp_hw.h>
Interrupt caused by an audio packet overflow.
#define XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK |
#include <xdp_hw.h>
Interrupt caused by a change in bandwidth.
#define XDP_RX_INTERRUPT_CAUSE_CRC_TEST_MASK XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK |
#include <xdp_hw.h>
Interrupt caused by the start of a CRC test.
#define XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK |
#include <xdp_hw.h>
Interrupt caused by a downstream reply being ready.
#define XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK |
#include <xdp_hw.h>
Interrupt caused by a downstream request being ready.
#define XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK |
#include <xdp_hw.h>
Interrupt caused by an audio extension packet being received.
#define XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK |
#include <xdp_hw.h>
Interrupt caused by an audio info packet being received.
#define XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK |
#include <xdp_hw.h>
Interrupt caused by the no-video condition being detected after active video received.
#define XDP_RX_INTERRUPT_CAUSE_PAYLOAD_ALLOC_MASK XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK |
#include <xdp_hw.h>
Interrupt caused by the RX's DPCD payload allocation registers has been updated as part of (de-)allocation or partial deletion.
#define XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK |
#include <xdp_hw.h>
Interrupt caused by a power state change.
#define XDP_RX_INTERRUPT_CAUSE_TP1_MASK XDP_RX_INTERRUPT_MASK_TP1_MASK |
#include <xdp_hw.h>
Interrupt caused by the start of training pattern 1.
#define XDP_RX_INTERRUPT_CAUSE_TP2_MASK XDP_RX_INTERRUPT_MASK_TP2_MASK |
#include <xdp_hw.h>
Interrupt caused by the start of training pattern 2.
#define XDP_RX_INTERRUPT_CAUSE_TP3_MASK XDP_RX_INTERRUPT_MASK_TP3_MASK |
#include <xdp_hw.h>
Interrupt caused by the start of training pattern 3.
#define XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK |
#include <xdp_hw.h>
Interrupt caused by link training completion.
#define XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK |
#include <xdp_hw.h>
Interrupt caused by training loss on active lanes.
#define XDP_RX_INTERRUPT_CAUSE_UNPLUG_MASK XDP_RX_INTERRUPT_MASK_UNPLUG_MASK |
#include <xdp_hw.h>
Interrupt caused by the an unplug event.
#define XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK XDP_RX_INTERRUPT_MASK_VBLANK_MASK |
#include <xdp_hw.h>
Interrupt caused by the start of the blanking interval.
#define XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK |
#include <xdp_hw.h>
Interrupt caused by a virtual channel payload being allocated.
#define XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK |
#include <xdp_hw.h>
Interrupt caused by a virtual channel payload being allocated.
#define XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK XDP_RX_INTERRUPT_MASK_VIDEO_MASK |
#include <xdp_hw.h>
Interrupt caused by a valid video frame being detected on the main link.
Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character.
#define XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK |
#include <xdp_hw.h>
Interrupt caused by a resolution change, as detected from the MSA fields.
#define XDP_RX_INTERRUPT_MASK 0x014 |
#include <xdp_hw.h>
Masks the specified interrupt sources for stream 1.
#define XDP_RX_INTERRUPT_MASK_1 0x044 |
#include <xdp_hw.h>
Masks the specified interrupt sources for streams 2, 3, 4.
#define XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK | ( | Stream | ) | (0x00001 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK | ( | Stream | ) | (0x00002 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK | ( | Stream | ) | (0x00008 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK | ( | Stream | ) | (0x00010 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or.
#define XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK | ( | Stream | ) | (0x00020 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK | ( | Stream | ) | (0x00004 << ((Stream - 2) * 6)) |
#include <xdp_hw.h>
Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4.
#define XDP_RX_INTERRUPT_MASK_ACT_RX_MASK 0x20000000 |
#include <xdp_hw.h>
Mask the interrupt assertion for the ACT sequence being received.
#define XDP_RX_INTERRUPT_MASK_ALL_MASK 0xF9FFFFFF |
#include <xdp_hw.h>
Mask all interrupts.
#define XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK 0x08000000 |
#include <xdp_hw.h>
Mask the interrupt assertion caused for an audio packet overflow.
#define XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK 0x00008000 |
#include <xdp_hw.h>
Mask the interrupt assertion for a change in bandwidth.
#define XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK 0x40000000 |
#include <xdp_hw.h>
Mask the interrupt assertion for the start of a CRC test.
#define XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK 0x00001000 |
#include <xdp_hw.h>
Mask the interrupt assertion for a downstream reply being ready.
#define XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK 0x00002000 |
#include <xdp_hw.h>
Mask the interrupt assertion for a downstream request being ready.
#define XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK 0x00000200 |
#include <xdp_hw.h>
Mask the interrupt assertion for an audio extension packet being received.
#define XDP_RX_INTERRUPT_MASK_HDCP_AINFO_WRITE_MASK 0x00400000 |
#include <xdp_hw.h>
Mask the interrupt for a write to the HDCP AInfo register.
#define XDP_RX_INTERRUPT_MASK_HDCP_AKSV_WRITE_MASK 0x00100000 |
#include <xdp_hw.h>
Mask the interrupt for a write to the HDCP AKSV MSB register.
#define XDP_RX_INTERRUPT_MASK_HDCP_AN_WRITE_MASK 0x00200000 |
#include <xdp_hw.h>
Mask the interrupt for a write to the HDCP An MSB register.
#define XDP_RX_INTERRUPT_MASK_HDCP_BINFO_READ_MASK 0x01000000 |
#include <xdp_hw.h>
Mask the interrupt for a read of the HDCP BInfo register.
#define XDP_RX_INTERRUPT_MASK_HDCP_DEBUG_WRITE_MASK 0x00080000 |
#include <xdp_hw.h>
Mask the interrupt for a write to any HDCP debug register.
#define XDP_RX_INTERRUPT_MASK_HDCP_RO_READ_MASK 0x00800000 |
#include <xdp_hw.h>
Mask the interrupt for a read of the HDCP Ro register.
#define XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK 0x00000100 |
#include <xdp_hw.h>
Mask the interrupt assertion for an audio info packet being received.
#define XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK 0x00000004 |
#include <xdp_hw.h>
Mask the interrupt assertion for the no-video condition being detected after active video received.
#define XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK 0x10000000 |
#include <xdp_hw.h>
Mask the interrupt assertion for the RX's DPCD payload allocation registers that have been updated as part of (de-)allocation or partial deletion.
#define XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK 0x00000002 |
#include <xdp_hw.h>
Mask the interrupt assertion for a power state change.
#define XDP_RX_INTERRUPT_MASK_TP1_MASK 0x00010000 |
#include <xdp_hw.h>
Mask the interrupt assertion for start of training pattern 1.
#define XDP_RX_INTERRUPT_MASK_TP2_MASK 0x00020000 |
#include <xdp_hw.h>
Mask the interrupt assertion for start of training pattern 2.
#define XDP_RX_INTERRUPT_MASK_TP3_MASK 0x00040000 |
#include <xdp_hw.h>
Mask the interrupt assertion for start of training pattern 3.
#define XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK 0x00004000 |
#include <xdp_hw.h>
Mask the interrupt assertion for link training completion.
#define XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK 0x00000010 |
#include <xdp_hw.h>
Mask the interrupt assertion for training loss on active lanes.
#define XDP_RX_INTERRUPT_MASK_UNPLUG_MASK 0x80000000 |
#include <xdp_hw.h>
Mask the unplug event interrupt.
#define XDP_RX_INTERRUPT_MASK_VBLANK_MASK 0x00000008 |
#include <xdp_hw.h>
Mask the interrupt assertion for the start of the blanking interval.
#define XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK 0x00000400 |
#include <xdp_hw.h>
Mask the interrupt assertion for a virtual channel payload being allocated.
#define XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK 0x00000800 |
#include <xdp_hw.h>
Mask the interrupt assertion for a virtual channel payload being allocated.
#define XDP_RX_INTERRUPT_MASK_VIDEO_MASK 0x00000040 |
#include <xdp_hw.h>
Mask the interrupt assertion for a valid video frame being detected on the main link.
Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character.
#define XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK 0x00000001 |
#include <xdp_hw.h>
Mask the interrupt assertion for a resolution change, as detected from the MSA fields.
#define XDP_RX_LINE_RESET_DISABLE 0x008 |
#include <xdp_hw.h>
RX line reset disable.
#define XDP_RX_LINE_RESET_DISABLE_MASK | ( | Stream | ) | (1 << ((Stream) - XDP_TX_STREAM_ID1)) |
#include <xdp_hw.h>
Used to disable the end of the line reset to the internal video pipe.
#define XDP_RX_LINK_ENABLE 0x000 |
#include <xdp_hw.h>
Enable the receiver core.
#define XDP_RX_LOCAL_EDID_AUDIO 0x088 |
#include <xdp_hw.h>
Indicates the presence of EDID information for the audio stream.
#define XDP_RX_LOCAL_EDID_VIDEO 0x084 |
#include <xdp_hw.h>
Indicates the presence of EDID information for the video stream.
#define XDP_RX_MIN_VOLTAGE_SWING 0x214 |
#include <xdp_hw.h>
Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_MASK 0x000C00 |
#include <xdp_hw.h>
Channel equalization options.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_HOLD 0x1 |
#include <xdp_hw.h>
Hold adjust request to SET_PE.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_INC 0x0 |
#include <xdp_hw.h>
Increment pre-emphasis adjust request every training iteration until maximum level, SET_PE, is reached.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_TABLE 0x2 |
#include <xdp_hw.h>
Pick pre-emphasis values from PE_TABLE.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_SHIFT 10 |
#include <xdp_hw.h>
Shift bits for channel equalization options.
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_VS_NA 0x3 |
#include <xdp_hw.h>
Not applicable.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_MASK 0x00000C |
#include <xdp_hw.h>
Clock recovery options.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_SHIFT 2 |
#include <xdp_hw.h>
Shift bits for clock recovery options.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_HOLD 0x2 |
#include <xdp_hw.h>
Hold adjust request to SET_VS.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC 0x0 |
#include <xdp_hw.h>
Increment voltage swing adjust request every training iteration.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC_4CNT 0x1 |
#include <xdp_hw.h>
Increment voltage swing adjust request every 4 or VS_SWEEP_CNT iterations.
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_NA 0x3 |
#include <xdp_hw.h>
Not applicable.
#define XDP_RX_MIN_VOLTAGE_SWING_MIN_MASK 0x000003 |
#include <xdp_hw.h>
The minimum voltage swing level.
#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_MASK | ( | Iteration | ) | (0x3 << (14 + ((Iteration - 1) * 2))) |
#include <xdp_hw.h>
Table specifying what pre-emphasis level to request for each training iteration.
#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_SHIFT | ( | Iteration | ) | (14 + ((Iteration - 1) * 2)) |
#include <xdp_hw.h>
Shift bits for pre-emphasis table.
#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_MASK 0x003000 |
#include <xdp_hw.h>
Set pre-emphasis level.
#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_SHIFT 12 |
#include <xdp_hw.h>
Shift bits for pre-emphasis setting.
#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_MASK 0x000300 |
#include <xdp_hw.h>
Set voltage swing level.
#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for voltage swing setting.
#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_MASK 0x000070 |
#include <xdp_hw.h>
Voltage swing sweep count.
#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_SHIFT 4 |
#include <xdp_hw.h>
Shift bits for voltage swing sweep count.
#define XDP_RX_MISC_CTRL 0x018 |
#include <xdp_hw.h>
Miscellaneous control of RX behavior.
#define XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK 0x4 |
#include <xdp_hw.h>
When set, I2C DEFERs will be sent as AUX DEFERs to the source device.
#define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK 0x2 |
#include <xdp_hw.h>
When set, the long I2C write data transfers are responded to using DEFER instead of partial ACKs.
#define XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK 0x1 |
#include <xdp_hw.h>
When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally.
#define XDP_RX_MSA_HRES 0x500 |
#include <xdp_hw.h>
Number of active pixels per line (the horizontal resolution).
#define XDP_RX_MSA_HSPOL 0x504 |
#include <xdp_hw.h>
The horizontal sync polarity.
#define XDP_RX_MSA_HSTART 0x50C |
#include <xdp_hw.h>
Number of clocks between the leading edge of the horizontal sync and the start of active data.
#define XDP_RX_MSA_HSWIDTH 0x508 |
#include <xdp_hw.h>
Width of the horizontal sync pulse.
#define XDP_RX_MSA_HTOTAL 0x510 |
#include <xdp_hw.h>
Total number of clocks in the horizontal framing period.
#define XDP_RX_MSA_MISC0 0x528 |
#include <xdp_hw.h>
Miscellaneous stream attributes.
#define XDP_RX_MSA_MISC1 0x52C |
#include <xdp_hw.h>
Miscellaneous stream attributes.
#define XDP_RX_MSA_MVID 0x530 |
#include <xdp_hw.h>
Used to recover the video clock from the link clock.
#define XDP_RX_MSA_NVID 0x534 |
#include <xdp_hw.h>
Used to recover the video clock from the link clock.
#define XDP_RX_MSA_VBID 0x538 |
#include <xdp_hw.h>
The most recently received VB-ID value.
#define XDP_RX_MSA_VHEIGHT 0x514 |
#include <xdp_hw.h>
Number of active lines (the vertical resolution).
#define XDP_RX_MSA_VSPOL 0x518 |
#include <xdp_hw.h>
The vertical sync polarity.
#define XDP_RX_MSA_VSTART 0x520 |
#include <xdp_hw.h>
Number of lines between the leading edge of the vertical sync and the first line of active data.
#define XDP_RX_MSA_VSWIDTH 0x51C |
#include <xdp_hw.h>
Width of the vertical sync pulse.
#define XDP_RX_MSA_VTOTAL 0x524 |
#include <xdp_hw.h>
Total number of lines in the video frame.
#define XDP_RX_MST_ALLOC 0x06C |
#include <xdp_hw.h>
Represents the content from the DPCD registers related to payload allocation.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_ALLOC_COUNT_TS_MASK 0x3F0000 |
#include <xdp_hw.h>
The time slot count that was issued as part of part of the most recent ALLOCATE_PAYLOAD down request.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_ALLOC_COUNT_TS_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for the time slot count.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_ALLOC_START_TS_MASK 0x003F00 |
#include <xdp_hw.h>
The starting time slot that was issued as part of the most recent ALLOCATE_PAYLOAD down request.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_ALLOC_START_TS_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for the starting time slot.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_ALLOC_VCP_ID_MASK 0x00003F |
#include <xdp_hw.h>
The virtual channel payload ID that was issued as part of the most recent ALLOCATE_PAYLOAD down request.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_CAP 0x0D0 |
#include <xdp_hw.h>
Used to enable or disable MST capability.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_MST_CAP_ENABLE_MASK 0x001 |
#include <xdp_hw.h>
When set to 1, enables MST mode in the RX, or disables it when 0.
#define XDP_RX_MST_CAP_OVER_ACT_MASK 0x004 |
#include <xdp_hw.h>
When set to 1, overrides the ACT trigger.
This is used when software controls the virtual channel payload table.
#define XDP_RX_MST_CAP_SOFT_VCP_MASK 0x002 |
#include <xdp_hw.h>
When set to 1, enables software control over the virtual channel payload table.
#define XDP_RX_MST_CAP_VCP_CLEAR_MASK 0x100 |
#include <xdp_hw.h>
When set to 1, clears the virtual channel payload table.
#define XDP_RX_MST_CAP_VCP_UPDATE_MASK 0x010 |
#include <xdp_hw.h>
When set to 1, indicates to the upstream device that the virtual channel payload table has been updated.
This is used when software controls the virtual channel payload table.
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT 3 |
#include <xdp_hw.h>
The number of I2C user- defined entries in the I2C map of each port.
#define XDP_RX_OVER_CTRL_DPCD 0x0B8 |
#include <xdp_hw.h>
Used to enable AXI/APB write access to the DPCD capability structure.
#define XDP_RX_OVER_DOWNSPREAD_CTRL 0x0BC |
#include <xdp_hw.h>
Used to override downspread control in the DPCD.
#define XDP_RX_OVER_GUID 0x0F0 |
#include <xdp_hw.h>
Used to override the GUID field in the DPCD with what is stored in XDP_RX_GUID[0-3].
#define XDP_RX_OVER_LANE_COUNT_SET 0x0A0 |
#include <xdp_hw.h>
Used to override the lane count setting in the DPCD.
#define XDP_RX_OVER_LANE_COUNT_SET_1 0x1 |
#include <xdp_hw.h>
Lane count of 1.
#define XDP_RX_OVER_LANE_COUNT_SET_2 0x2 |
#include <xdp_hw.h>
Lane count of 2.
#define XDP_RX_OVER_LANE_COUNT_SET_4 0x4 |
#include <xdp_hw.h>
Lane count of 4.
#define XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK 0x80 |
#include <xdp_hw.h>
Capability override for enhanced framing.
#define XDP_RX_OVER_LANE_COUNT_SET_MASK 0x1F |
#include <xdp_hw.h>
The lane count override value.
#define XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK 0x40 |
#include <xdp_hw.h>
Capability override for training pattern 3.
#define XDP_RX_OVER_LINK_BW_SET 0x09C |
#include <xdp_hw.h>
Used to override the main link bandwidth setting in the DPCD.
#define XDP_RX_OVER_LINK_BW_SET_162GBPS 0x06 |
#include <xdp_hw.h>
1.62 Gbps link rate.
#define XDP_RX_OVER_LINK_BW_SET_270GBPS 0x0A |
#include <xdp_hw.h>
2.70 Gbps link rate.
#define XDP_RX_OVER_LINK_BW_SET_540GBPS 0x14 |
#include <xdp_hw.h>
5.40 Gbps link rate.
#define XDP_RX_OVER_LINK_QUAL_LANE0_SET 0x0C0 |
#include <xdp_hw.h>
Used to override the LINK_QUAL_LANE0_SET register in the DPCD.
#define XDP_RX_OVER_LINK_QUAL_LANE1_SET 0x0C4 |
#include <xdp_hw.h>
Used to override the LINK_QUAL_LANE1_SET register in the DPCD.
#define XDP_RX_OVER_LINK_QUAL_LANE2_SET 0x0C8 |
#include <xdp_hw.h>
Used to override the LINK_QUAL_LANE2_SET register in the DPCD.
#define XDP_RX_OVER_LINK_QUAL_LANE3_SET 0x0CC |
#include <xdp_hw.h>
Used to override the LINK_QUAL_LANE3_SET register in the DPCD.
#define XDP_RX_OVER_TP_SET 0x0A4 |
#include <xdp_hw.h>
Used to override the link training pattern in the DPCD.
#define XDP_RX_OVER_TP_SET_LQP_SET_MASK 0x000C |
#include <xdp_hw.h>
Link quality pattern set override.
#define XDP_RX_OVER_TP_SET_LQP_SET_SHIFT 2 |
#include <xdp_hw.h>
Shift bits for link quality pattern set override.
#define XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK 0x0010 |
#include <xdp_hw.h>
Recovered clock output enable override.
#define XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK 0x0020 |
#include <xdp_hw.h>
Scrambling disable override.
#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK 0x00C0 |
#include <xdp_hw.h>
Symbol error count override.
#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT 6 |
#include <xdp_hw.h>
Shift bits for symbol error count override.
#define XDP_RX_OVER_TP_SET_TP_SELECT_MASK 0x0003 |
#include <xdp_hw.h>
Training pattern select override.
#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK 0xFF00 |
#include <xdp_hw.h>
Training AUX read interval override.
#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for training AUX read interval override.
#define XDP_RX_OVER_TRAINING_LANE0_SET 0x0A8 |
#include <xdp_hw.h>
Used to override the TRAINING_LANE0_SET register in the DPCD.
#define XDP_RX_OVER_TRAINING_LANE1_SET 0x0AC |
#include <xdp_hw.h>
Used to override the TRAINING_LANE1_SET register in the DPCD.
#define XDP_RX_OVER_TRAINING_LANE2_SET 0x0B0 |
#include <xdp_hw.h>
Used to override the TRAINING_LANE2_SET register in the DPCD.
#define XDP_RX_OVER_TRAINING_LANE3_SET 0x0B4 |
#include <xdp_hw.h>
Used to override the TRAINING_LANE3_SET register in the DPCD.
#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 |
#include <xdp_hw.h>
Maximum pre-emphasis override.
#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 |
#include <xdp_hw.h>
Maximum voltage swing override.
#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK 0x18 |
#include <xdp_hw.h>
Pre-emphasis set override.
#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT 3 |
#include <xdp_hw.h>
Shift bits for pre-emphasis set override.
#define XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK 0x03 |
#include <xdp_hw.h>
Voltage swing set override.
#define XDP_RX_PHY_CONFIG 0x200 |
#include <xdp_hw.h>
Transceiver PHY reset and configuration.
#define XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK 0x04000000 |
#include <xdp_hw.h>
Enable the individual lane polarity.
#define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK 0x00000003 |
#include <xdp_hw.h>
Reset GT and PHY.
#define XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK 0x00000001 |
#include <xdp_hw.h>
Hold the GTPLL in reset.
#define XDP_RX_PHY_CONFIG_GTRX_RESET_MASK 0x00000002 |
#include <xdp_hw.h>
Hold GTRXRESET in reset.
#define XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x00000000 |
#include <xdp_hw.h>
Release reset.
#define XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK 0x01000000 |
#include <xdp_hw.h>
Issue reset at every link rate change.
#define XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK 0x02000000 |
#include <xdp_hw.h>
Issue reset at start of training pattern 1.
#define XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK 0x00800000 |
#include <xdp_hw.h>
Issue reset at every training iteration.
#define XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK 0x00000400 |
#include <xdp_hw.h>
Hold RX_PHY_BUF reset.
#define XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK 0x00400000 |
#include <xdp_hw.h>
Set RX_PHY_CDRHOLD.
#define XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK 0x00000800 |
#include <xdp_hw.h>
Hold RX_PHY_DFE_LPM reset.
#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK 0x00010000 |
#include <xdp_hw.h>
Set RX_PHY_EYESCANRESET.
#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK 0x00020000 |
#include <xdp_hw.h>
Set RX_PHY_ EYESCANTRIGGER.
#define XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK 0x0000E000 |
#include <xdp_hw.h>
Set RX_PHY_LOOPBACK.
#define XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK 0x00000200 |
#include <xdp_hw.h>
Hold RX_PHY_PCS reset.
#define XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK 0x00000100 |
#include <xdp_hw.h>
Hold RX_PHY_PMA reset.
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK 0x08000000 |
#include <xdp_hw.h>
Configure RX_PHY_POLARITY for lane 0.
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK 0x10000000 |
#include <xdp_hw.h>
Configure RX_PHY_POLARITY for lane 1.
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK 0x20000000 |
#include <xdp_hw.h>
Configure RX_PHY_POLARITY for lane 2.
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK 0x40000000 |
#include <xdp_hw.h>
Configure RX_PHY_POLARITY for lane 3.
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK 0x00001000 |
#include <xdp_hw.h>
Set RX_PHY_POLARITY.
#define XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK 0x00040000 |
#include <xdp_hw.h>
Set RX_PHY_PRBSCNTRESET.
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK 0x00080000 |
#include <xdp_hw.h>
Set RX_PHY_RXLPMHFHOLD.
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK 0x00200000 |
#include <xdp_hw.h>
Set RX_PHY_ RXLPMHFOVERDEN.
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK 0x00100000 |
#include <xdp_hw.h>
Set RX_PHY_RXLPMLFHOLD.
#define XDP_RX_PHY_POWER_DOWN 0x210 |
#include <xdp_hw.h>
Control PHY power down.
#define XDP_RX_PHY_POWER_DOWN_LANE_0_MASK 0x1 |
#include <xdp_hw.h>
Power down the PHY for lane 0.
#define XDP_RX_PHY_POWER_DOWN_LANE_1_MASK 0x2 |
#define XDP_RX_PHY_POWER_DOWN_LANE_2_MASK 0x4 |
#define XDP_RX_PHY_POWER_DOWN_LANE_3_MASK 0x8 |
#define XDP_RX_PHY_STATUS 0x208 |
#include <xdp_hw.h>
Current PHY status.
#define XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK 0x0000003F |
#include <xdp_hw.h>
All lanes are ready.
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK 0x00010000 |
#include <xdp_hw.h>
Lane alignment status for lane 0.
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK 0x00020000 |
#include <xdp_hw.h>
Lane alignment status for lane 1.
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK 0x00040000 |
#include <xdp_hw.h>
Lane alignment status for lane 2.
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK 0x00080000 |
#include <xdp_hw.h>
Lane alignment status for lane 3.
#define XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK 0x00000013 |
#include <xdp_hw.h>
Lanes 0 and 1 are ready.
#define XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 |
#include <xdp_hw.h>
FPGA fabric clock PLL locked.
#define XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 |
#include <xdp_hw.h>
PLL locked for lanes 0 and 1.
#define XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 |
#include <xdp_hw.h>
PLL locked for lanes 2 and 3.
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK 0x00000100 |
#include <xdp_hw.h>
PRBS error on lane 0.
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK 0x00000200 |
#include <xdp_hw.h>
PRBS error on lane 1.
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK 0x00000400 |
#include <xdp_hw.h>
PRBS error on lane 2.
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK 0x00000800 |
#include <xdp_hw.h>
PRBS error on lane 3.
#define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK 0x00000003 |
#include <xdp_hw.h>
Reset done for lanes 0 and 1.
#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C |
#include <xdp_hw.h>
Reset done for lanes 2 and 3.
#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 |
#include <xdp_hw.h>
Shift bits for reset done for lanes 2 and 3.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT 26 |
#include <xdp_hw.h>
Shift bits for RX buffer status lane 1.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK 0x03000000 |
#include <xdp_hw.h>
RX buffer status lane 0.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for RX buffer status lane 0.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK 0x0C000000 |
#include <xdp_hw.h>
RX buffer status lane 1.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK 0x30000000 |
#include <xdp_hw.h>
RX buffer status lane 2.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT 28 |
#include <xdp_hw.h>
Shift bits for RX buffer status lane 2.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK 0xC0000000 |
#include <xdp_hw.h>
RX buffer status lane 3.
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT 30 |
#include <xdp_hw.h>
Shift bits for RX buffer status lane 3.
#define XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK 0x00000080 |
#include <xdp_hw.h>
Receiver clock locked.
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK 0x00001000 |
#include <xdp_hw.h>
RX voltage low on lane 0.
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK 0x00002000 |
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK 0x00004000 |
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK 0x00008000 |
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK 0x00100000 |
#include <xdp_hw.h>
Symbol lock status for lane 0.
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK 0x00200000 |
#include <xdp_hw.h>
Symbol lock status for lane 1.
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK 0x00400000 |
#include <xdp_hw.h>
Symbol lock status for lane 2.
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK 0x00800000 |
#include <xdp_hw.h>
Symbol lock status for lane 3.
#define XDP_RX_REMOTE_CMD 0x08C |
#include <xdp_hw.h>
Used for passing remote information to the DisplayPort TX.
#define XDP_RX_REQ_ADDRESS 0x038 |
#include <xdp_hw.h>
Contains the address field of the most recent AUX request.
#define XDP_RX_REQ_CLK_WIDTH 0x030 |
#include <xdp_hw.h>
Holds the half period of the recovered AUX clock.
#define XDP_RX_REQ_CMD 0x034 |
#include <xdp_hw.h>
Provides the most recent AUX command received.
#define XDP_RX_REQ_COUNT 0x028 |
#include <xdp_hw.h>
Provides a running total of the number of AUX requests received.
#define XDP_RX_REQ_ERROR_COUNT 0x024 |
#include <xdp_hw.h>
Provides a running total of errors detected on inbound AUX channel requests.
#define XDP_RX_REQ_LENGTH 0x03C |
#include <xdp_hw.h>
Contains length of the most recent AUX request.
#define XDP_RX_SINK_COUNT 0x0D4 |
#include <xdp_hw.h>
The sink device count.
#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD 0xF00 |
#include <xdp_hw.h>
User access to the sink specific field as exposed in the RX DPCD (0xFF bytes).
#define XDP_RX_SOFT_RESET 0x01C |
#include <xdp_hw.h>
Software reset.
#define XDP_RX_SOFT_RESET_AUX_MASK 0x80 |
#include <xdp_hw.h>
Reset the AUX logic.
#define XDP_RX_SOFT_RESET_VIDEO_MASK 0x01 |
#include <xdp_hw.h>
Reset the video logic.
#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD 0xE00 |
#include <xdp_hw.h>
User access to the source specific field as exposed in the RX DPCD (0xFF bytes).
#define XDP_RX_STREAM1_MSA_START 0x500 |
#include <xdp_hw.h>
Start of the MSA registers for stream 1.
#define XDP_RX_STREAM2_MSA_START 0x540 |
#include <xdp_hw.h>
Start of the MSA registers for stream 2.
#define XDP_RX_STREAM2_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().
#define XDP_RX_STREAM3_MSA_START 0x580 |
#include <xdp_hw.h>
Start of the MSA registers for stream 3.
#define XDP_RX_STREAM3_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().
#define XDP_RX_STREAM4_MSA_START 0x5C0 |
#include <xdp_hw.h>
Start of the MSA registers for stream 4.
#define XDP_RX_STREAM4_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().
#define XDP_RX_USER_FIFO_OVERFLOW 0x110 |
#include <xdp_hw.h>
Indicates an overflow in user FIFO.
#define XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK | ( | Stream | ) | (Stream) |
#include <xdp_hw.h>
Indicates that the internal FIFO has detected on overflow condition for the specified stream.
#define XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK | ( | Stream | ) | (Stream << 8) |
#include <xdp_hw.h>
Indicates that the video timing FIFO has overflown for the specified stream.
#define XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK | ( | Stream | ) | (Stream << 4) |
#include <xdp_hw.h>
Indicates that the video unpack FIFO has overflown for the specified stream.
#define XDP_RX_USER_PIXEL_WIDTH 0x010 |
#include <xdp_hw.h>
Selects the width of the user data input port.
#define XDP_RX_USER_PIXEL_WIDTH_1 0x1 |
#include <xdp_hw.h>
Single pixel wide interface.
#define XDP_RX_USER_PIXEL_WIDTH_2 0x2 |
#include <xdp_hw.h>
Dual pixel output mode.
#define XDP_RX_USER_PIXEL_WIDTH_4 0x4 |
#include <xdp_hw.h>
Quad pixel output mode.
#define XDP_RX_USER_VSYNC_STATE 0x114 |
#include <xdp_hw.h>
Provides a mechanism for the host processor to monitor the state of the video data path.
#define XDP_RX_USER_VSYNC_STATE_STREAMX_MASK | ( | Stream | ) | (Stream) |
#include <xdp_hw.h>
The state of the vertical sync pulse for the specified stream.
#define XDP_RX_VC_PAYLOAD_TABLE 0x800 |
#include <xdp_hw.h>
Virtual channel payload table (0xFF bytes).
Referenced by XDp_RxAllocatePayloadStream().
#define XDP_RX_VERSION 0x0F8 |
#include <xdp_hw.h>
Version and revision of the DisplayPort core.
#define XDP_RX_VERSION_CORE_PATCH_MASK 0x00000030 |
#include <xdp_hw.h>
Core patch details.
#define XDP_RX_VERSION_CORE_PATCH_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for core patch details.
#define XDP_RX_VERSION_CORE_VER_MJR_MASK 0x0000F000 |
#include <xdp_hw.h>
Core major version.
#define XDP_RX_VERSION_CORE_VER_MJR_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for core major version.
#define XDP_RX_VERSION_CORE_VER_MNR_MASK 0x00000F00 |
#include <xdp_hw.h>
Core minor version.
#define XDP_RX_VERSION_CORE_VER_MNR_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for core minor version.
#define XDP_RX_VERSION_CORE_VER_REV_MASK 0x000000C0 |
#include <xdp_hw.h>
Core version revision.
#define XDP_RX_VERSION_CORE_VER_REV_SHIFT 12 |
#include <xdp_hw.h>
Shift bits for core version revision.
#define XDP_RX_VERSION_INTER_REV_MASK 0x0000000F |
#include <xdp_hw.h>
Internal revision.
#define XDP_RX_VIDEO_UNSUPPORTED 0x094 |
#include <xdp_hw.h>
DPCD register bit to inform the DisplayPort TX that video data is not supported.
#define XDP_RX_VSYNC_WIDTH 0x058 |
#include <xdp_hw.h>
Controls the timing of the active-high vertical sync pulse generated by the display timing generator (DTG).
#define XDP_TX_AUDIO_CHANNELS 0x304 |
#include <xdp_hw.h>
Used to input active channel count.
#define XDP_TX_AUDIO_CONTROL 0x300 |
#include <xdp_hw.h>
Enables audio stream packets in main link and buffer control.
#define XDP_TX_AUDIO_EXT_DATA | ( | NUM | ) | (0x330 + 4 * (NUM - 1)) |
#include <xdp_hw.h>
Word formatted as per extension packet.
#define XDP_TX_AUDIO_INFO_DATA | ( | NUM | ) | (0x308 + 4 * (NUM - 1)) |
#include <xdp_hw.h>
Word formatted as per CEA 861-C info frame.
#define XDP_TX_AUDIO_MAUD 0x328 |
#include <xdp_hw.h>
M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.
#define XDP_TX_AUDIO_NAUD 0x32C |
#include <xdp_hw.h>
N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.
#define XDP_TX_AUX_ADDRESS 0x108 |
#include <xdp_hw.h>
Specifies the address of current AUX command.
#define XDP_TX_AUX_CLK_DIVIDER 0x10C |
#include <xdp_hw.h>
Clock divider value for generating the internal 1MHz clock.
#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
#include <xdp_hw.h>
AUX (noise) signal width filter.
#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for AUX signal width filter.
#define XDP_TX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
#include <xdp_hw.h>
Clock divider value.
#define XDP_TX_AUX_CMD 0x100 |
#include <xdp_hw.h>
Initiates AUX commands.
#define XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN 0x00001000 |
#include <xdp_hw.h>
Address only transfer enable (STOP will be sent after command).
#define XDP_TX_AUX_CMD_I2C_READ 0x1 |
#include <xdp_hw.h>
I2C-over-AUX read command.
#define XDP_TX_AUX_CMD_I2C_READ_MOT 0x5 |
#include <xdp_hw.h>
I2C-over-AUX read MOT (middle-of-transaction) command.
#define XDP_TX_AUX_CMD_I2C_WRITE 0x0 |
#include <xdp_hw.h>
I2C-over-AUX write command.
#define XDP_TX_AUX_CMD_I2C_WRITE_MOT 0x4 |
#include <xdp_hw.h>
I2C-over-AUX write MOT (middle-of-transaction) command.
#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS 0x2 |
#include <xdp_hw.h>
I2C-over-AUX write status command.
#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT 0x6 |
#include <xdp_hw.h>
I2C-over-AUX write status MOT (middle-of- transaction) command.
#define XDP_TX_AUX_CMD_MASK 0x00000F00 |
#include <xdp_hw.h>
AUX command.
#define XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F |
#include <xdp_hw.h>
Number of bytes to transfer with the current AUX command.
#define XDP_TX_AUX_CMD_READ 0x9 |
#include <xdp_hw.h>
AUX read command.
#define XDP_TX_AUX_CMD_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for command.
#define XDP_TX_AUX_CMD_WRITE 0x8 |
#include <xdp_hw.h>
AUX write command.
#define XDP_TX_AUX_REPLY_CODE 0x138 |
#include <xdp_hw.h>
Reply code received from the most recent AUX command.
#define XDP_TX_AUX_REPLY_CODE_ACK 0x0 |
#include <xdp_hw.h>
AUX command ACKed.
#define XDP_TX_AUX_REPLY_CODE_DEFER 0x2 |
#include <xdp_hw.h>
AUX command deferred.
#define XDP_TX_AUX_REPLY_CODE_I2C_ACK 0x0 |
#include <xdp_hw.h>
I2C-over-AUX command not ACKed.
#define XDP_TX_AUX_REPLY_CODE_I2C_DEFER 0x8 |
#include <xdp_hw.h>
I2C-over-AUX command deferred.
#define XDP_TX_AUX_REPLY_CODE_I2C_NACK 0x4 |
#include <xdp_hw.h>
I2C-over-AUX command not ACKed.
#define XDP_TX_AUX_REPLY_CODE_NACK 0x1 |
#include <xdp_hw.h>
AUX command not ACKed.
#define XDP_TX_AUX_REPLY_COUNT 0x13C |
#include <xdp_hw.h>
Number of reply transactions received over AUX.
#define XDP_TX_AUX_REPLY_DATA 0x134 |
#include <xdp_hw.h>
Reply data received during the AUX reply.
#define XDP_TX_AUX_WRITE_FIFO 0x104 |
#include <xdp_hw.h>
Write data for the current AUX command.
#define XDP_TX_CORE_ID 0x0FC |
#include <xdp_hw.h>
DisplayPort protocol version and revision.
#define XDP_TX_CORE_ID_DP_MJR_VER_MASK 0x0000F000 |
#include <xdp_hw.h>
DisplayPort protocol major version.
#define XDP_TX_CORE_ID_DP_MJR_VER_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol major version.
#define XDP_TX_CORE_ID_DP_MNR_VER_MASK 0x00000F00 |
#include <xdp_hw.h>
DisplayPort protocol minor version.
#define XDP_TX_CORE_ID_DP_MNR_VER_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol major version.
#define XDP_TX_CORE_ID_DP_REV_MASK 0x000000F0 |
#include <xdp_hw.h>
DisplayPort protocol revision.
#define XDP_TX_CORE_ID_DP_REV_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for DisplayPort protocol revision.
#define XDP_TX_CORE_ID_TYPE_MASK 0x0000000F |
#include <xdp_hw.h>
Core type.
#define XDP_TX_CORE_ID_TYPE_RX 0x1 |
#include <xdp_hw.h>
Core is a receiver.
#define XDP_TX_CORE_ID_TYPE_TX 0x0 |
#include <xdp_hw.h>
Core is a transmitter.
#define XDP_TX_DOWNSPREAD_CTRL 0x018 |
#include <xdp_hw.h>
Enable a 0.5% spreading of the clock.
#define XDP_TX_ENABLE 0x080 |
#include <xdp_hw.h>
Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled.
#define XDP_TX_ENABLE_MAIN_STREAM 0x084 |
#include <xdp_hw.h>
Enable transmission of main link video info.
#define XDP_TX_ENABLE_SEC_STREAM 0x088 |
#include <xdp_hw.h>
Enable the transmission of secondary link info.
#define XDP_TX_ENHANCED_FRAME_EN 0x008 |
#include <xdp_hw.h>
Enable enhanced framing symbol sequence.
#define XDP_TX_FORCE_SCRAMBLER_RESET 0x0C0 |
#include <xdp_hw.h>
Force a scrambler reset.
#define XDP_TX_FRAC_BYTES_PER_TU 0x1C8 |
#include <xdp_hw.h>
The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value.
#define XDP_TX_GT_DRP_CHANNEL_STATUS 0x2A8 |
#include <xdp_hw.h>
Provides access to GT DRP channel status.
#define XDP_TX_GT_DRP_COMMAND 0x2A0 |
#include <xdp_hw.h>
Provides access to the GT DRP ports.
#define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F |
#include <xdp_hw.h>
DRP address.
#define XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 |
#include <xdp_hw.h>
DRP read/write command (Read=0, Write=1).
#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 |
#include <xdp_hw.h>
DRP write data.
#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for DRP write data.
#define XDP_TX_GT_DRP_READ_DATA 0x2A4 |
#include <xdp_hw.h>
Provides access to GT DRP read data.
#define XDP_TX_HDCP_ENABLE 0x400 |
#include <xdp_hw.h>
Enables HDCP core.
#define XDP_TX_HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001 |
#include <xdp_hw.h>
Disables bypass of the HDCP core.
#define XDP_TX_HPD_DURATION 0x150 |
#include <xdp_hw.h>
Duration of the HPD pulse in microseconds.
#define XDP_TX_INIT_WAIT 0x1CC |
#include <xdp_hw.h>
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.
#define XDP_TX_INTERRUPT_MASK 0x144 |
#include <xdp_hw.h>
Masks the specified interrupt sources.
#define XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK 0x00000020 |
#include <xdp_hw.h>
Mask extended packet transmit interrupt.
#define XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK 0x00000002 |
#include <xdp_hw.h>
Mask HPD event interrupt.
#define XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK 0x00000001 |
#include <xdp_hw.h>
Mask HPD IRQ interrupt.
#define XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK 0x00000010 |
#include <xdp_hw.h>
Mask HPD pulse detected interrupt.
#define XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK 0x00000004 |
#include <xdp_hw.h>
Mask reply received interrupt.
#define XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK 0x00000008 |
#include <xdp_hw.h>
Mask reply received interrupt.
#define XDP_TX_INTERRUPT_SIG_STATE 0x130 |
#include <xdp_hw.h>
The raw signal values for interrupt events.
#define XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 |
#include <xdp_hw.h>
Raw state of the HPD pin on the DP connector.
#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK 0x00000004 |
#include <xdp_hw.h>
A reply is currently being received.
#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK 0x00000008 |
#include <xdp_hw.h>
A reply timeout has occurred.
#define XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK 0x00000002 |
#include <xdp_hw.h>
A request is currently being sent.
#define XDP_TX_INTERRUPT_STATUS 0x140 |
#include <xdp_hw.h>
Status for interrupt events.
#define XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK 0x00000020 |
#include <xdp_hw.h>
Extended packet has been transmitted and the core is ready to accept a new packet.
#define XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK 0x00000002 |
#include <xdp_hw.h>
Detected the presence of the HPD signal.
#define XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK 0x00000001 |
#include <xdp_hw.h>
Detected an IRQ framed with the proper timing on the HPD signal.
#define XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK 0x00000010 |
#include <xdp_hw.h>
A pulse on the HPD line was detected.
#define XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK 0x00000004 |
#include <xdp_hw.h>
An AUX reply transaction has been detected.
#define XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK 0x00000008 |
#include <xdp_hw.h>
A reply timeout has occurred.
#define XDP_TX_LANE_COUNT_SET 0x004 |
#include <xdp_hw.h>
Set lane count setting.
#define XDP_TX_LANE_COUNT_SET_1 0x01 |
#define XDP_TX_LANE_COUNT_SET_2 0x02 |
#define XDP_TX_LANE_COUNT_SET_4 0x04 |
#define XDP_TX_LINE_RESET_DISABLE 0x0F0 |
#include <xdp_hw.h>
TX line reset disable.
#define XDP_TX_LINE_RESET_DISABLE_MASK | ( | Stream | ) | (1 << ((Stream) - XDP_TX_STREAM_ID1)) |
#include <xdp_hw.h>
Used to disable the end of the line reset to the internal video pipe.
#define XDP_TX_LINK_BW_SET 0x000 |
#include <xdp_hw.h>
Set main link bandwidth setting.
#define XDP_TX_LINK_BW_SET_162GBPS 0x06 |
#define XDP_TX_LINK_BW_SET_270GBPS 0x0A |
#define XDP_TX_LINK_BW_SET_540GBPS 0x14 |
#define XDP_TX_LINK_QUAL_PATTERN_SET 0x010 |
#include <xdp_hw.h>
Transmit the link quality pattern.
#define XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST 0x1 |
#include <xdp_hw.h>
D10.2 unscrambled test pattern transmitted.
#define XDP_TX_LINK_QUAL_PATTERN_SET_OFF 0x0 |
#include <xdp_hw.h>
Link quality test pattern not transmitted.
#define XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7 0x3 |
#include <xdp_hw.h>
Pseudo random bit sequence 7 transmitted.
#define XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES 0x2 |
#include <xdp_hw.h>
Symbol error rate measurement pattern transmitted.
#define XDP_TX_M_VID 0x1AC |
#include <xdp_hw.h>
M value for the video stream as computed by the source core in asynchronous clock mode.
Must be written in synchronous mode.
#define XDP_TX_MAIN_STREAM_HRES 0x194 |
#include <xdp_hw.h>
Number of active pixels per line (the horizontal resolution).
#define XDP_TX_MAIN_STREAM_HSTART 0x19C |
#include <xdp_hw.h>
Number of clocks between the leading edge of the horizontal sync and the start of active data.
#define XDP_TX_MAIN_STREAM_HSWIDTH 0x18C |
#include <xdp_hw.h>
Width of the horizontal sync pulse.
#define XDP_TX_MAIN_STREAM_HTOTAL 0x180 |
#include <xdp_hw.h>
Total number of clocks in the horizontal framing period.
#define XDP_TX_MAIN_STREAM_INTERLACED 0x1C0 |
#include <xdp_hw.h>
Video is interlaced.
#define XDP_TX_MAIN_STREAM_MISC0 0x1A4 |
#include <xdp_hw.h>
Miscellaneous stream attributes.
#define XDP_TX_MAIN_STREAM_MISC1 0x1A8 |
#include <xdp_hw.h>
Miscellaneous stream attributes.
#define XDP_TX_MAIN_STREAM_POLARITY 0x188 |
#include <xdp_hw.h>
Polarity for the video sync signals.
#define XDP_TX_MAIN_STREAM_VRES 0x198 |
#include <xdp_hw.h>
Number of active lines (the vertical resolution).
#define XDP_TX_MAIN_STREAM_VSTART 0x1A0 |
#include <xdp_hw.h>
Number of lines between the leading edge of the vertical sync and the first line of active data.
#define XDP_TX_MAIN_STREAM_VSWIDTH 0x190 |
#include <xdp_hw.h>
Width of the vertical sync pulse.
#define XDP_TX_MAIN_STREAM_VTOTAL 0x184 |
#include <xdp_hw.h>
Total number of lines in the video frame.
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_INSERT_TIMESTAMP_MASK 0x00000400 |
#include <xdp_hw.h>
Inserts info/timestamp every 512 BS symbols.
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_MODE_MASK 0x00000200 |
#include <xdp_hw.h>
Audio clock modes, Setting this bit to 1 enables sync mode.
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_UNMASK_LOWER_MAUD_BITS_MASK 0x00000800 |
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC 0x2 |
#include <xdp_hw.h>
10 bits per component.
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC 0x3 |
#include <xdp_hw.h>
12 bits per component.
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC 0x4 |
#include <xdp_hw.h>
16 bits per component.
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC 0x0 |
#include <xdp_hw.h>
6 bits per component.
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC 0x1 |
#include <xdp_hw.h>
8 bits per component.
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 |
#include <xdp_hw.h>
Bit depth per color component (BDC).
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT 5 |
#include <xdp_hw.h>
Shift bits for BDC.
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 |
#include <xdp_hw.h>
Component format.
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB 0x0 |
#include <xdp_hw.h>
Stream's component format is RGB.
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 |
#include <xdp_hw.h>
Shift bits for component format.
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 0x5 |
#include <xdp_hw.h>
Stream's component format is YcbCr 4:2:2.
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 0x6 |
#include <xdp_hw.h>
Stream's component format is YcbCr 4:4:4.
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_CEA 1 |
#include <xdp_hw.h>
CEA range.
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 |
#include <xdp_hw.h>
Dynamic range.
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 |
#include <xdp_hw.h>
Shift bits for dynamic range.
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_VESA 0 |
#include <xdp_hw.h>
VESA range.
#define XDP_TX_MAIN_STREAMX_MISC0_OVERRIDE_CLOCKING_MODE_MASK 0x00000100 |
#include <xdp_hw.h>
Override Audio clk Mode.
#define XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK 0x00000001 |
#include <xdp_hw.h>
Synchronous clock.
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT601 0 |
#include <xdp_hw.h>
ITU BT601 YCbCr coefficients.
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT709 1 |
#include <xdp_hw.h>
ITU BT709 YCbCr coefficients.
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 |
#include <xdp_hw.h>
YCbCr colorimetry.
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 |
#include <xdp_hw.h>
Shift bits for YCbCr colorimetry.
#define XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK 0x00000001 |
#include <xdp_hw.h>
Interlaced vertical total even.
#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK 0x00000006 |
#include <xdp_hw.h>
Stereo video attribute.
#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT 1 |
#include <xdp_hw.h>
Shift bits for stereo video attribute.
#define XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK 0x00000001 |
#include <xdp_hw.h>
Polarity of the horizontal sync pulse.
#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK 0x00000002 |
#include <xdp_hw.h>
Polarity of the vertical sync pulse.
#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 |
#include <xdp_hw.h>
Shift bits for polarity of the vertical sync pulse.
#define XDP_TX_MIN_BYTES_PER_TU 0x1C4 |
#include <xdp_hw.h>
The minimum number of bytes per transfer unit.
#define XDP_TX_MST_CONFIG 0x0D0 |
#include <xdp_hw.h>
Enable MST.
#define XDP_TX_MST_CONFIG_MST_EN_MASK 0x00000001 |
#include <xdp_hw.h>
Enable MST.
#define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK 0x00000002 |
#include <xdp_hw.h>
The VC payload has been updated in the sink.
#define XDP_TX_N_VID 0x1B4 |
#include <xdp_hw.h>
N value for the video stream as computed by the source core in asynchronous clock mode.
Must be written in synchronous mode.
#define XDP_TX_PE_LEVEL_0 0x00 |
#include <xdp_hw.h>
Pre-emphasis level 0.
#define XDP_TX_PE_LEVEL_1 0x0E |
#include <xdp_hw.h>
Pre-emphasis level 1.
#define XDP_TX_PE_LEVEL_2 0x14 |
#include <xdp_hw.h>
Pre-emphasis level 2.
#define XDP_TX_PE_LEVEL_3 0x1B |
#include <xdp_hw.h>
Pre-emphasis level 3.
#define XDP_TX_PHY_CLOCK_SELECT 0x234 |
#include <xdp_hw.h>
Instructs the PHY PLL to generate the proper clock frequency for the required link rate.
#define XDP_TX_PHY_CLOCK_SELECT_162GBPS 0x1 |
#include <xdp_hw.h>
1.62 Gbps link.
#define XDP_TX_PHY_CLOCK_SELECT_270GBPS 0x3 |
#include <xdp_hw.h>
2.70 Gbps link.
#define XDP_TX_PHY_CLOCK_SELECT_540GBPS 0x5 |
#include <xdp_hw.h>
5.40 Gbps link.
#define XDP_TX_PHY_CONFIG 0x200 |
#include <xdp_hw.h>
Transceiver PHY reset and configuration.
#define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 |
#include <xdp_hw.h>
Reset GT and PHY.
#define XDP_TX_PHY_CONFIG_GTTX_RESET_MASK 0x0000002 |
#include <xdp_hw.h>
Hold GTTXRESET in reset.
#define XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK 0x0000000 |
#include <xdp_hw.h>
Release reset.
#define XDP_TX_PHY_CONFIG_PHY_RESET_MASK 0x0000001 |
#include <xdp_hw.h>
Hold the PHY in reset.
#define XDP_TX_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0200000 |
#include <xdp_hw.h>
8B10B encoding enable.
#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 |
#include <xdp_hw.h>
Set TX_PHY_LOOPBACK.
#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 |
#include <xdp_hw.h>
Shift bits for TX_PHY_LOOPBACK.
#define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK 0x0000200 |
#include <xdp_hw.h>
Hold TX_PHY_PCS reset.
#define XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK 0x0000100 |
#include <xdp_hw.h>
Hold TX_PHY_PMA reset.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK 0x0010000 |
#include <xdp_hw.h>
Set to enable individual lane polarity.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK 0x0020000 |
#include <xdp_hw.h>
Set TX_PHY_POLARITY for lane 0.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK 0x0040000 |
#include <xdp_hw.h>
Set TX_PHY_POLARITY for lane 1.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK 0x0080000 |
#include <xdp_hw.h>
Set TX_PHY_POLARITY for lane 2.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK 0x0100000 |
#include <xdp_hw.h>
Set TX_PHY_POLARITY for lane 3.
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK 0x0000800 |
#include <xdp_hw.h>
Set TX_PHY_POLARITY.
#define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK 0x0001000 |
#include <xdp_hw.h>
Set TX_PHY_PRBSFORCEERR.
#define XDP_TX_PHY_POSTCURSOR_LANE_0 0x24C |
#include <xdp_hw.h>
Controls the post-cursor level.
#define XDP_TX_PHY_POSTCURSOR_LANE_1 0x250 |
#include <xdp_hw.h>
Controls the post-cursor level.
#define XDP_TX_PHY_POSTCURSOR_LANE_2 0x254 |
#include <xdp_hw.h>
Controls the post-cursor level.
#define XDP_TX_PHY_POSTCURSOR_LANE_3 0x258 |
#include <xdp_hw.h>
Controls the post-cursor level.
#define XDP_TX_PHY_POWER_DOWN 0x238 |
#include <xdp_hw.h>
Controls PHY power down.
#define XDP_TX_PHY_PRECURSOR_LANE_0 0x23C |
#include <xdp_hw.h>
Controls the pre-cursor level.
#define XDP_TX_PHY_PRECURSOR_LANE_1 0x240 |
#include <xdp_hw.h>
Controls the pre-cursor level.
#define XDP_TX_PHY_PRECURSOR_LANE_2 0x244 |
#include <xdp_hw.h>
Controls the pre-cursor level.
#define XDP_TX_PHY_PRECURSOR_LANE_3 0x248 |
#include <xdp_hw.h>
Controls the pre-cursor level.
#define XDP_TX_PHY_STATUS 0x280 |
#include <xdp_hw.h>
Current PHY status.
#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK |
#include <xdp_hw.h>
Lanes 0-3 are ready.
#define XDP_TX_PHY_STATUS_LANE_0_READY_MASK |
#include <xdp_hw.h>
Lane 0 is ready.
#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK |
#include <xdp_hw.h>
Lanes 0-1 are ready.
#define XDP_TX_PHY_STATUS_LANES_READY_MASK | ( | n | ) |
#include <xdp_hw.h>
Macro for lanes ready mask with number of lanes as the argument.
#define XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK 0x00000040 |
#include <xdp_hw.h>
FPGA fabric clock PLL locked.
#define XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK 0x00000010 |
#include <xdp_hw.h>
PLL locked for lanes 0 and 1.
#define XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK 0x00000020 |
#include <xdp_hw.h>
PLL locked for lanes 2 and 3.
#define XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001 |
#include <xdp_hw.h>
Reset done for lane 0.
#define XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK 0x00000002 |
#include <xdp_hw.h>
Reset done for lane 1.
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK 0x0000000C |
#include <xdp_hw.h>
Reset done for lanes 2 and 3.
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT 2 |
#include <xdp_hw.h>
Shift bits for reset done for lanes 2 and 3.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK 0x00030000 |
#include <xdp_hw.h>
TX buffer status lane 0.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for TX buffer status lane 0.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK 0x00300000 |
#include <xdp_hw.h>
TX buffer status lane 1.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT 20 |
#include <xdp_hw.h>
Shift bits for TX buffer status lane 1.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK 0x03000000 |
#include <xdp_hw.h>
TX buffer status lane 2.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for TX buffer status lane 2.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK 0x30000000 |
#include <xdp_hw.h>
TX buffer status lane 3.
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT 28 |
#include <xdp_hw.h>
Shift bits for TX buffer status lane 3.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK 0x000C0000 |
#include <xdp_hw.h>
TX error on lane 0.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT 18 |
#include <xdp_hw.h>
Shift bits for TX error on lane 0.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK 0x00C00000 |
#include <xdp_hw.h>
TX error on lane 1.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT 22 |
#include <xdp_hw.h>
Shift bits for TX error on lane 1.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK 0x0C000000 |
#include <xdp_hw.h>
TX error on lane 2.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT 26 |
#include <xdp_hw.h>
Shift bits for TX error on lane 2.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK 0xC0000000 |
#include <xdp_hw.h>
TX error on lane 3.
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT 30 |
#include <xdp_hw.h>
Shift bits for TX error on lane 3.
#define XDP_TX_PHY_TRANSMIT_PRBS7 0x230 |
#include <xdp_hw.h>
Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x220 |
#include <xdp_hw.h>
Controls the differential voltage swing.
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x224 |
#include <xdp_hw.h>
Controls the differential voltage swing.
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x228 |
#include <xdp_hw.h>
Controls the differential voltage swing.
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x22C |
#include <xdp_hw.h>
Controls the differential voltage swing.
#define XDP_TX_REPLY_DATA_COUNT 0x148 |
#include <xdp_hw.h>
Total number of data bytes actually received during a transaction.
#define XDP_TX_REPLY_STATUS 0x14C |
#include <xdp_hw.h>
Reply status of most recent AUX transaction.
#define XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 |
#include <xdp_hw.h>
Detected an error in the AUX reply of the most recent transaction.
#define XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 |
#include <xdp_hw.h>
AUX reply is currently being received.
#define XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 |
#include <xdp_hw.h>
AUX transaction is complete and a valid reply transaction received.
#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 |
#include <xdp_hw.h>
Internal AUX reply state machine status bits.
#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 |
#include <xdp_hw.h>
Shift bits for the internal AUX reply state machine status.
#define XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 |
#include <xdp_hw.h>
AUX request is currently being transmitted.
#define XDP_TX_SCRAMBLING_DISABLE 0x014 |
#include <xdp_hw.h>
Disable scrambler and transmit all symbols.
#define XDP_TX_SOFT_RESET 0x01C |
#include <xdp_hw.h>
Software reset.
#define XDP_TX_SOFT_RESET_AUX_MASK 0x00000080 |
#include <xdp_hw.h>
Reset AUX logic.
#define XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK 0x00000001 |
#include <xdp_hw.h>
Reset video logic.
#define XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK 0x00000002 |
#include <xdp_hw.h>
Reset video logic.
#define XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK 0x00000004 |
#include <xdp_hw.h>
Reset video logic.
#define XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK 0x00000008 |
#include <xdp_hw.h>
Reset video logic.
#define XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK 0x0000000F |
#include <xdp_hw.h>
Reset video logic for all streams.
#define XDP_TX_STREAM1 0x1D0 |
#include <xdp_hw.h>
Average stream symbol timeslots per MTP config.
#define XDP_TX_STREAM1_MSA_START 0x180 |
#include <xdp_hw.h>
Start of the MSA registers for stream 1.
#define XDP_TX_STREAM2 0x1D4 |
#include <xdp_hw.h>
Average stream symbol timeslots per MTP config.
#define XDP_TX_STREAM2_MSA_START 0x500 |
#include <xdp_hw.h>
Start of the MSA registers for stream 2.
#define XDP_TX_STREAM2_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().
#define XDP_TX_STREAM3 0x1D8 |
#include <xdp_hw.h>
Average stream symbol timeslots per MTP config.
#define XDP_TX_STREAM3_MSA_START 0x550 |
#include <xdp_hw.h>
Start of the MSA registers for stream 3.
#define XDP_TX_STREAM3_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().
#define XDP_TX_STREAM4 0x1DC |
#include <xdp_hw.h>
Average stream symbol timeslots per MTP config.
#define XDP_TX_STREAM4_MSA_START 0x5A0 |
#include <xdp_hw.h>
Start of the MSA registers for stream 4.
#define XDP_TX_STREAM4_MSA_START_OFFSET |
#include <xdp_hw.h>
The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1.
Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().
#define XDP_TX_TRAINING_PATTERN_SET 0x00C |
#include <xdp_hw.h>
Set the link training pattern.
#define XDP_TX_TRAINING_PATTERN_SET_OFF 0x0 |
#include <xdp_hw.h>
Training off.
#define XDP_TX_TRAINING_PATTERN_SET_TP1 0x1 |
#include <xdp_hw.h>
Training pattern 1 used for clock recovery.
#define XDP_TX_TRAINING_PATTERN_SET_TP2 0x2 |
#include <xdp_hw.h>
Training pattern 2 used for channel equalization.
#define XDP_TX_TRAINING_PATTERN_SET_TP3 0x3 |
#include <xdp_hw.h>
Training pattern 3 used for channel equalization for cores with DP v1.2.
#define XDP_TX_TU_SIZE 0x1B0 |
#include <xdp_hw.h>
Size of a transfer unit in the framing logic.
#define XDP_TX_USER_DATA_COUNT_PER_LANE 0x1BC |
#include <xdp_hw.h>
Used to translate the number of pixels per line to the native internal 16-bit datapath.
#define XDP_TX_USER_FIFO_OVERFLOW 0x110 |
#include <xdp_hw.h>
Indicates an overflow in user FIFO.
#define XDP_TX_USER_PIXEL_WIDTH 0x1B8 |
#include <xdp_hw.h>
Selects the width of the user data input port.
#define XDP_TX_VC_PAYLOAD_BUFFER_ADDR 0x800 |
#include <xdp_hw.h>
Virtual channel payload table (0xFF bytes).
#define XDP_TX_VERSION 0x0F8 |
#include <xdp_hw.h>
Version and revision of the DisplayPort core.
#define XDP_TX_VERSION_CORE_PATCH_MASK 0x00000030 |
#include <xdp_hw.h>
Core patch details.
#define XDP_TX_VERSION_CORE_PATCH_SHIFT 8 |
#include <xdp_hw.h>
Shift bits for core patch details.
#define XDP_TX_VERSION_CORE_VER_MJR_MASK 0x0000F000 |
#include <xdp_hw.h>
Core major version.
#define XDP_TX_VERSION_CORE_VER_MJR_SHIFT 24 |
#include <xdp_hw.h>
Shift bits for core major version.
#define XDP_TX_VERSION_CORE_VER_MNR_MASK 0x00000F00 |
#include <xdp_hw.h>
Core minor version.
#define XDP_TX_VERSION_CORE_VER_MNR_SHIFT 16 |
#include <xdp_hw.h>
Shift bits for core minor version.
#define XDP_TX_VERSION_CORE_VER_REV_MASK 0x000000C0 |
#include <xdp_hw.h>
Core version revision.
#define XDP_TX_VERSION_CORE_VER_REV_SHIFT 12 |
#include <xdp_hw.h>
Shift bits for core version revision.
#define XDP_TX_VERSION_INTER_REV_MASK 0x0000000F |
#include <xdp_hw.h>
Internal revision.
#define XDP_TX_VS_LEVEL_0 0x2 |
#include <xdp_hw.h>
Voltage swing level 0.
#define XDP_TX_VS_LEVEL_1 0x5 |
#include <xdp_hw.h>
Voltage swing level 1.
#define XDP_TX_VS_LEVEL_2 0x8 |
#include <xdp_hw.h>
Voltage swing level 2.
#define XDP_TX_VS_LEVEL_3 0xF |
#include <xdp_hw.h>
Voltage swing level 3.
#define XDP_TX_VS_LEVEL_OFFSET 0x4 |
#include <xdp_hw.h>
Voltage swing compensation offset used when there's no redriver in display path.
#define XDp_TxCfgSetRGB | ( | InstancePtr, | |
Stream | |||
) |
#include <xdp.h>
The following functions set the color encoding scheme for a given stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to configure the color encoding scheme for. |
#define XDp_TxGetDispIdTdtHLoc | ( | Tdt | ) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled display.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxGetDispIdTdtHTotal | ( | Tdt | ) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the tiled display.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxGetDispIdTdtNumTiles | ( | Tdt | ) | (XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt)) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, retrieve the total number of tiles in the tiled display.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxGetDispIdTdtTileOrder | ( | Tdt | ) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, calculate the tiling order of the associated tile.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID. The tiling order starts at 0 for x,y coordinate 0,0 and increments as the horizontal location increases. Once the last horizontal tile has been reached, the next tile in the order is 0,y+1.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxGetDispIdTdtVLoc | ( | Tdt | ) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled display.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxGetDispIdTdtVTotal | ( | Tdt | ) |
#include <xdp_hw.h>
Given a Tiled Display Topology (TDT) data block, retrieve the total number of vertical tiles in the tiled display.
The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.
Tdt | is a pointer to the TDT data block. |
#define XDp_TxIsEdidExtBlockDispId | ( | Ext | ) | (Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID) |
#include <xdp_hw.h>
Check if an Extended Display Identification Data (EDID) extension block is of type DisplayID.
Ext | is a pointer to the EDID extension block under comparison. |
#define XDp_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
Data | |||
) | XDp_Out32((BaseAddress) + (RegOffset), (Data)) |
#include <xdp_hw.h>
This is a low-level function that writes to the specified register.
BaseAddress | is the base address of the device. |
RegOffset | is the register offset to write to. |
Data | is the 32-bit data to write to the specified register. |
Referenced by XDp_RxAllocatePayloadStream().
typedef void(* XDp_IntrHandler) (void *InstancePtr) |
typedef void(* XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds) |
#include <xdp.h>
Callback type which represents a custom timer wait handler.
This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.
InstancePtr | is a pointer to the XDp instance. |
MicroSeconds | is the number of microseconds to be passed to the timer function. |
enum XDp_CoreType |
#include <xdp.h>
This typedef enumerates the RX and TX modes of operation for the DisplayPort core.
enum XDp_DynamicRange |
#include <xdp.h>
This typedef enumerates the dynamic ranges available to the DisplayPort core.
enum XDp_TxTrainingState |
#include <xdp.c>
This typedef enumerates the list of training states used in the state machine during the link training process.
void XDp_CfgInitialize | ( | XDp * | InstancePtr, |
XDp_Config * | ConfigPtr, | ||
UINTPTR | EffectiveAddr | ||
) |
#include <xdp.c>
This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.
InstancePtr | is a pointer to the XDp instance. |
ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from. |
EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed. |
References XDp_Config::BaseAddr, XDp::Config, and XDp_GetCoreType.
Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().
u32 XDp_Initialize | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
Referenced by Dptx_SetupExample().
void XDp_InterruptHandler | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function is the interrupt handler for the XDp driver.
When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u8 XDp_IsLaneCountValid | ( | XDp * | InstancePtr, |
u8 | LaneCount | ||
) |
#include <xdp.c>
This function checks the validity of the lane count.
InstancePtr | is a pointer to the XDp instance. |
LaneCount | is the number of lanes to check if valid. |
References XDp::Config, XDp_Config::MaxLaneCount, XDP_TX_LANE_COUNT_SET_1, XDP_TX_LANE_COUNT_SET_2, and XDP_TX_LANE_COUNT_SET_4.
u8 XDp_IsLinkRateValid | ( | XDp * | InstancePtr, |
u8 | LinkRate | ||
) |
#include <xdp.c>
This function checks the validity of the link rate.
InstancePtr | is a pointer to the XDp instance. |
LinkRate | is the link rate to check if valid. |
References XDp::Config, XDp_Config::MaxLinkRate, XDP_TX_LINK_BW_SET_162GBPS, XDP_TX_LINK_BW_SET_270GBPS, and XDP_TX_LINK_BW_SET_540GBPS.
XDp_Config * XDp_LookupConfig | ( | u16 | DeviceId | ) |
#include <xdp.h>
This function looks for the device configuration based on the unique device ID.
The table XDp_ConfigTable[] contains the configuration information for each device in the system.
DeviceId | is the unique device ID of the device being looked up. |
Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().
void XDp_RxAllocatePayloadStream | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will set the virtual channel payload table both in software and in the DisplayPort RX core's hardware registers based on the MST allocation values from ALLOCATE_PAYLOAD and CLEAR_PAYLOAD sideband message requests.
InstancePtr | is a pointer to the XDp instance. |
References XDp_Config::BaseAddr, XDp::Config, XDp_RxTopology::PayloadTable, XDp_Rx::Topology, XDp_ReadReg, XDP_RX_MST_ALLOC, XDP_RX_MST_ALLOC_COUNT_TS_MASK, XDP_RX_MST_ALLOC_COUNT_TS_SHIFT, XDP_RX_MST_ALLOC_START_TS_MASK, XDP_RX_MST_ALLOC_START_TS_SHIFT, XDP_RX_MST_ALLOC_VCP_ID_MASK, XDP_RX_MST_CAP, XDP_RX_MST_CAP_VCP_UPDATE_MASK, XDP_RX_VC_PAYLOAD_TABLE, and XDp_WriteReg.
void XDp_RxAudioDis | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function disables audio stream packets on the main link.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxAudioEn | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function enables audio stream packets on the main link.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxAudioReset | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function resets the RX core's reception of audio stream packets on the main link.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_RxCheckLinkStatus | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function checks if the receiver's internal registers indicate that link training has complete.
That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxDtgDis | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function disables the display timing generator (DTG).
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxDtgEn | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function enables the display timing generator (DTG).
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxGenerateHpdInterrupt | ( | XDp * | InstancePtr, |
u16 | DurationUs | ||
) |
#include <xdp.h>
This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.
InstancePtr | is a pointer to the XDp instance. |
DurationUs | is the duration of the HPD pulse, in microseconds. |
References XDp::IsReady, and XDp_GetCoreType.
XVidC_ColorDepth XDp_RxGetBpc | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function extracts the bits per color from MISC0 of the stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number to make the calculations for. |
References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.
XVidC_ColorFormat XDp_RxGetColorComponent | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function extracts the color component format from MISC0 of the stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number to make the calculations for. |
References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.
XDp_RxIicMapEntry * XDp_RxGetIicMapEntry | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
u8 | IicAddress | ||
) |
#include <xdp.h>
This function returns a pointer to the I2C map entry at the supplied I2C address for the specified port.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number for which to obtain the I2C map entry for. |
IicAddress | is the I2C address of the map entry. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_RxHandleDownReq | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will handle incoming sideband messages.
It will 1) Read the contents of the down request registers, 2) Delegate control depending on the request type, and 3) Send a down reply.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxInterruptDisable | ( | XDp * | InstancePtr, |
u32 | Mask | ||
) |
#include <xdp.h>
This function disables interrupts associated with the specified mask.
InstancePtr | is a pointer to the XDp instance. |
Mask | specifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxInterruptEnable | ( | XDp * | InstancePtr, |
u32 | Mask | ||
) |
#include <xdp.h>
This function enables interrupts associated with the specified mask.
InstancePtr | is a pointer to the XDp instance. |
Mask | specifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxMstExposePort | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
u8 | Expose | ||
) |
#include <xdp.h>
This function allows the user to select which ports will be exposed when replying to a LINK_ADDRESS sideband message.
The number of ports will also be set. When an upstream device sends a LINK_ADDRESS sideband message, the RX will respond by forming a reply message containing port information for directly connected ports. If exposed, this information will be provided in the LINK_ADDRESS reply. Otherwise, the LINK_ADDRESS reply will not contain this information, hiding the port from the TX.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number to enable or disable exposure. |
Expose | will expose the port at the specified PortNum as part of the LINK_ADDRESS reply when set to 1. Hidden otherwise. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxMstSetInputPort | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
XDp_SbMsgLinkAddressReplyPortDetail * | PortOverride | ||
) |
#include <xdp.h>
This function, for an input port, sets the port information that is contained in the driver instance structure for the specified port number.
Some default values will be used if no port structure is supplied.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number to set the input port for. |
PortOverride | is a pointer to the user-defined port structure, whose information is to be copied into the driver instance. If set to NULL, default values for the input port will be used. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxMstSetPbn | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
u16 | PbnVal | ||
) |
#include <xdp.h>
This function will set the available payload bandwidth number (PBN) of the specified port that is available for allocation, and the full PBN that the port is capable of using.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number to set the PBN values for. |
PbnVal | is the value to set the port's available and full PBN to. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxMstSetPort | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
XDp_SbMsgLinkAddressReplyPortDetail * | PortDetails | ||
) |
#include <xdp.h>
This function sets the port information that is contained in the driver instance structure for the specified port number, to be copied from the supplied port details structure.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number to set the port details for. |
PortDetails | is a pointer to the user-defined port structure, whose information is to be copied into the driver instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxSetDpcdMap | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
u32 | StartAddr, | ||
u32 | NumBytes, | ||
u8 * | DpcdMap | ||
) |
#include <xdp.h>
This function specified the DPCD address space for a given port.
The user provides a pointer to the data to be used. When an upstream device issues a REMOTE_DPCD_READ sideband message, the contents of this DPCD structure will be used as the reply's data.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number for which to set the DPCD. |
StartAddr | is the starting address for which to define the DPCD. |
NumBytes | is the total number of bytes defined by the DPCD. |
DpcdMap | is a pointer to a user-defined data structure that will be used as read data when an upstream device issues a DPCD read. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxSetDrvIntrNoVideoHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs driver callback function for when a no video interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetDrvIntrPowerStateHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a driver callback function for when the power state interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetDrvIntrVideoHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a driver callback function for when a valid video interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
u32 XDp_RxSetIicMapEntry | ( | XDp * | InstancePtr, |
u8 | PortNum, | ||
u8 | IicAddress, | ||
u8 | ReadNumBytes, | ||
u8 * | ReadData | ||
) |
#include <xdp.h>
This function adds an entry into the I2C map for a given port.
The user provides a pointer to the data to be used for the specified I2C address. When an upstream device issues a REMOTE_I2C_READ sideband message, this I2C map will be searched for an entry matching the requested I2C address read.
InstancePtr | is a pointer to the XDp instance. |
PortNum | is the port number for which to set the I2C map entry. |
IicAddress | is the I2C address for which to set the data. |
ReadNumBytes | is number of bytes available for reading from the associated IicAddress. |
ReadData | is a pointer to a user-defined data structure that will be used as read data when an upstream device issues an I2C read. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxSetIntrActRxHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when an ACT received interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrAudioOverHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when an audio packet overflow interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrBwChangeHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a bandwidth change interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrCrcTestHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a CRC test start interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrDownReplyHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a down reply interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrDownReqHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a down request interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrExtPktHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when an audio extension packet interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpAinfoWriteHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a write to the hdcp Ainfo MSB register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpAksvWriteHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a write to the hdcp Aksv MSB register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpAnWriteHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a write to the hdcp An MSB register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpBinfoReadHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a read of the hdcp Binfo register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpDebugWriteHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a write to any hdcp debug register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrHdcpRoReadHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a read of the hdcp Ro/Ri MSB register occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrInfoPktHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when an audio info packet interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrNoVideoHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a no video interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrPayloadAllocHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when the RX's DPCD payload allocation registers have been written for allocation, de-allocation, or partial deletion.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrPowerStateHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when the power state interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrTp1Handler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a training pattern 1 interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrTp2Handler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a training pattern 2 interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrTp3Handler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a training pattern 3 interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrTrainingDoneHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a training done interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrTrainingLostHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a training lost interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrUnplugHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when an unplug event interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrVBlankHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a vertical blanking interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrVideoHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a valid video interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetIntrVmChangeHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a video mode change interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_RxSetLaneCount | ( | XDp * | InstancePtr, |
u8 | LaneCount | ||
) |
#include <xdp.c>
This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
InstancePtr | is a pointer to the XDp instance. |
LaneCount | is the number of lanes to be used over the main link. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxSetLineReset | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
Disable/enables the end of line reset to the internal video pipe in case of reduced blanking as required.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number to make the calculations for. |
References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.
void XDp_RxSetLinkRate | ( | XDp * | InstancePtr, |
u8 | LinkRate | ||
) |
#include <xdp.c>
This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.
InstancePtr | is a pointer to the XDp instance. |
LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
References XDp::IsReady, and XDp_GetCoreType.
void XDp_RxSetUserPixelWidth | ( | XDp * | InstancePtr, |
u8 | UserPixelWidth | ||
) |
#include <xdp.h>
This function configures the number of pixels output through the user data interface.
InstancePtr | is a pointer to the XDp instance. |
UserPixelWidth | is the user pixel width to be configured. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_SelfTest | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode.
The sanity test checks whether or not all tested registers hold their default reset values.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
Referenced by Dp_SelfTestExample().
void XDp_SetUserTimerHandler | ( | XDp * | InstancePtr, |
XDp_TimerHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.c>
This function installs a custom delay/sleep function to be used by the XDp driver.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked. |
References XDp::UserTimerPtr, and XDp::UserTimerWaitUs.
u32 XDp_TxAllocatePayloadStreams | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will allocate bandwidth for all enabled stream.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxAllocatePayloadVcIdTable | ( | XDp * | InstancePtr, |
u8 | VcId, | ||
u8 | Ts, | ||
u8 | StartTs | ||
) |
#include <xdp.h>
This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress.
InstancePtr | is a pointer to the XDp instance. |
VcId | is the unique virtual channel ID to allocate into the payload ID tables. |
Ts | is the number of timeslots to allocate in the payload ID tables. |
StartTs | is the starting time slot to allocate the VcId to. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxAuxRead | ( | XDp * | InstancePtr, |
u32 | DpcdAddress, | ||
u32 | BytesToRead, | ||
void * | ReadData | ||
) |
#include <xdp.c>
This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space.
The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
InstancePtr | is a pointer to the XDp instance. |
DpcdAddress | is the starting address to read from the RX device. |
BytesToRead | is the number of bytes to read from the RX device. |
ReadData | is a pointer to the data buffer that will be filled with read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxAuxWrite | ( | XDp * | InstancePtr, |
u32 | DpcdAddress, | ||
u32 | BytesToWrite, | ||
void * | WriteData | ||
) |
#include <xdp.c>
This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space.
The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
InstancePtr | is a pointer to the XDp instance. |
DpcdAddress | is the starting address to write to the RX device. |
BytesToWrite | is the number of bytes to write to the RX device. |
WriteData | is a pointer to the data buffer that contains the data to be written to the RX device. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxCfgMainLinkMax | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function determines the common capabilities between the DisplayPort TX core and the RX device.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, XDp_Tx::LinkConfig, and XDp_GetCoreType.
void XDp_TxCfgMsaEnSynchClkMode | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
u8 | Enable | ||
) |
#include <xdp.h>
This function enables or disables synchronous clock mode for a video stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to enable or disable synchronous clock mode. |
Enable | if set to 1, will enable synchronous clock mode. Otherwise, if set to 0, synchronous clock mode will be disabled. |
References XDp_GetCoreType.
void XDp_TxCfgMsaRecalculate | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function calculates the following Main Stream Attributes (MSA):
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to calculate the MSA values. |
References XDp_GetCoreType.
void XDp_TxCfgMsaSetBpc | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
u8 | BitsPerColor | ||
) |
#include <xdp.h>
This function sets the bits per color value of the video stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to set the color depth. |
BitsPerColor | is the new number of bits per color to use. |
References XDp_GetCoreType.
void XDp_TxCfgMsaUseCustom | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
XDp_TxMainStreamAttributes * | MsaConfigCustom, | ||
u8 | Recalculate | ||
) |
#include <xdp.h>
This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig.
If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which the MSA values will be used for. |
MsaConfigCustom | is the structure that will be used to copy the main stream attributes from (into InstancePtr->TxInstance.MsaConfig). |
Recalculate | is a boolean enable that determines whether or not the main stream attributes should be recalculated. |
References XDp_GetCoreType.
void XDp_TxCfgMsaUseEdidPreferredTiming | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
u8 * | Edid | ||
) |
#include <xdp.h>
This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor.
This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which the MSA values will be used for. |
Edid | is a pointer to the Edid to use for the specified stream. |
References XDp_GetCoreType.
void XDp_TxCfgMsaUseStandardVideoMode | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
XVidC_VideoMode | VideoMode | ||
) |
#include <xdp.h>
This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table.
The XDp_TxVideoMode enumeration in xvidc.h lists the available video modes.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which the MSA values will be used for. |
VideoMode | is one of the enumerated standard video modes that is used to determine the MSA values to be used. |
References XDp_GetCoreType.
u32 XDp_TxCfgSetColorEncode | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
XVidC_ColorFormat | Format, | ||
XVidC_ColorStd | ColorCoeffs, | ||
XDp_DynamicRange | Range | ||
) |
#include <xdp.h>
This function will set the color encoding scheme for a given stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to configure the color encoding scheme for. |
Format | is the color space format. |
ColorCoeffs | is the color space conversion standard to use which will determine which color coefficients to use. |
Range | is the dynamic range to use (CEA or VESA). |
References XDp_GetCoreType.
void XDp_TxCfgTxPeLevel | ( | XDp * | InstancePtr, |
u8 | Level, | ||
u8 | TxLevel | ||
) |
#include <xdp.c>
This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level.
InstancePtr | is a pointer to the XDp instance. |
Level | is the pre-emphasis training level to set the DisplayPort TX level for. |
TxLevel | is the DisplayPort TX pre-emphasis level value to be used during link training. |
References XDp_GetCoreType.
void XDp_TxCfgTxVsLevel | ( | XDp * | InstancePtr, |
u8 | Level, | ||
u8 | TxLevel | ||
) |
#include <xdp.c>
This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level.
InstancePtr | is a pointer to the XDp instance. |
Level | is the voltage swing training level to set the DisplayPort TX level for. |
TxLevel | is the DisplayPort TX voltage swing level value to be used during link training. |
References XDp_GetCoreType.
void XDp_TxCfgTxVsOffset | ( | XDp * | InstancePtr, |
u8 | Offset | ||
) |
#include <xdp.c>
This function sets the voltage swing offset to use during training when no redriver exists.
The offset will be added to the DisplayPort TX's voltage swing level value when pre-emphasis is used (when the pre-emphasis level not equal to 0).
InstancePtr | is a pointer to the XDp instance. |
Offset | is the value to set for the voltage swing offset. |
References XDp_GetCoreType.
u32 XDp_TxCheckLinkStatus | ( | XDp * | InstancePtr, |
u8 | LaneCount | ||
) |
#include <xdp.c>
This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates the receiver has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.
InstancePtr | is a pointer to the XDp instance. |
LaneCount | is the number of lanes to check. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxClearMsaValues | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function clears the main stream attributes registers of the DisplayPort TX core.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to clear the MSA values. |
References XDp::IsReady, XDp_GetCoreType, XDP_TX_STREAM2_MSA_START_OFFSET, XDP_TX_STREAM3_MSA_START_OFFSET, and XDP_TX_STREAM4_MSA_START_OFFSET.
u32 XDp_TxClearPayloadVcIdTable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxDisableMainLink | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function disables the main link.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxDiscoverTopology | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX.
It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
InstancePtr | is a pointer to the XDp instance. |
References XDp_TxFindAccessibleDpDevices().
void XDp_TxEnableMainLink | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function enables the main link.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxEnableTrainAdaptive | ( | XDp * | InstancePtr, |
u8 | Enable | ||
) |
#include <xdp.c>
This function enables or disables downshifting during the training process.
InstancePtr | is a pointer to the XDp instance. |
Enable | controls the downshift feature in the training process. |
References XDp_GetCoreType.
u32 XDp_TxEstablishLink | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function checks if the link needs training and runs the training sequence if training is required.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, XDp_Tx::LinkConfig, and XDp_GetCoreType.
u32 XDp_TxFindAccessibleDpDevices | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress | ||
) |
#include <xdp.h>
This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters.
It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the current downstream device in the recursion. |
RelativeAddress | is the relative address from the DisplayPort source to the current target DisplayPort device in the recursion. |
References XDp::IsReady, and XDp_GetCoreType.
Referenced by XDp_TxDiscoverTopology().
u32 XDp_TxGetDispIdDataBlock | ( | u8 * | DisplayIdRaw, |
u8 | SectionTag, | ||
u8 ** | DataBlockPtr | ||
) |
#include <xdp.h>
Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure.
DisplayIdRaw | is a pointer to the DisplayID data. |
SectionTag | is the tag to search for that represents the desired section data block. |
DataBlockPtr | will be set by this function to point to the appropriate section data block that is part of the DisplayIdRaw. |
u32 XDp_TxGetEdid | ( | XDp * | InstancePtr, |
u8 * | Edid | ||
) |
#include <xdp.h>
This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure.
InstancePtr | is a pointer to the XDp instance. |
Edid | is a pointer to the Edid buffer to save to. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxGetEdidBlock | ( | XDp * | InstancePtr, |
u8 * | Data, | ||
u8 | BlockNum | ||
) |
#include <xdp.h>
Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number.
A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
InstancePtr | is a pointer to the XDp instance. |
Data | is a pointer to the data buffer to save the block data to. |
BlockNum | is the EDID block number to retrieve. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxGetGuid | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 * | Guid | ||
) |
#include <xdp.h>
This function will obtain the global unique identifier (GUID) for the target DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. |
RelativeAddress | is the relative address from the DisplayPort source to the target device. |
Guid | is a pointer to the GUID that will store the existing GUID of the target device. |
References XDp::IsReady, XDp_GetCoreType, and XDP_GUID_NBYTES.
u32 XDp_TxGetRemoteEdid | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 * | Edid | ||
) |
#include <xdp.h>
This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
Edid | is a pointer to the Edid buffer to save to. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxGetRemoteEdidBlock | ( | XDp * | InstancePtr, |
u8 * | Data, | ||
u8 | BlockNum, | ||
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress | ||
) |
#include <xdp.h>
Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number.
A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.
InstancePtr | is a pointer to the XDp instance. |
Data | is a pointer to the data buffer to save the block data to. |
BlockNum | is the EDID block number to retrieve. |
LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. |
RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxGetRemoteEdidDispIdExt | ( | XDp * | InstancePtr, |
u8 * | Data, | ||
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress | ||
) |
#include <xdp.h>
Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID.
InstancePtr | is a pointer to the XDp instance. |
Data | is a pointer to the data buffer to save the DisplayID to. |
LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. |
RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxGetRemoteTiledDisplayDb | ( | XDp * | InstancePtr, |
u8 * | EdidExt, | ||
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 ** | DataBlockPtr | ||
) |
#include <xdp.h>
Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure.
The DisplayID structure is part of the Extended Display Identification Data (EDID) in the form of an extension block.
InstancePtr | is a pointer to the XDp instance. |
EdidExt | is a pointer to the data area that will be filled by the retrieved DisplayID extension block. |
LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. |
RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
DataBlockPtr | will be set by this function to point to the TDT data block that is part of the EdidExt extension block. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxGetRxCapabilities | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).
InstancePtr | is a pointer to the XDp instance. |
References XDp::Config, XDp_TxSinkConfig::DpcdRxCapsField, XDp::IsReady, XDp_Tx::LinkConfig, XDp_Tx::RxConfig, and XDp_GetCoreType.
Referenced by Dptx_StartLink().
u32 XDp_TxIicRead | ( | XDp * | InstancePtr, |
u8 | IicAddress, | ||
u16 | Offset, | ||
u16 | BytesToRead, | ||
void * | ReadData | ||
) |
#include <xdp.c>
This function performs an I2C read over the AUX channel.
The read message will be divided into multiple transactions if the requested data spans multiple segments. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
InstancePtr | is a pointer to the XDp instance. |
IicAddress | is the address on the I2C bus of the target device. |
Offset | is the offset at the specified address of the targeted I2C device that the read will start from. |
BytesToRead | is the number of bytes to read. |
ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxIicWrite | ( | XDp * | InstancePtr, |
u8 | IicAddress, | ||
u8 | BytesToWrite, | ||
void * | WriteData | ||
) |
#include <xdp.c>
This function performs an I2C write over the AUX channel.
InstancePtr | is a pointer to the XDp instance. |
IicAddress | is the address on the I2C bus of the target device. |
BytesToWrite | is the number of bytes to write. |
WriteData | is a pointer to a buffer which will be used as the data source for the write. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxIsConnected | ( | XDp * | InstancePtr | ) |
#include <xdp.c>
This function checks if there is a connected RX device.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxMstCapable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode.
A DisplayPort Configuration Data (DPCD) version of 1.2 or higher is required and the MST capability bit in the DPCD must be set for this function to return XST_SUCCESS.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxMstCfgModeDisable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will disable multi-stream transport (MST) mode for the driver.
InstancePtr | is a pointer to the XDp instance. |
References XDp_GetCoreType.
Referenced by Dptx_AudioExample(), and Dptx_TimerExample().
void XDp_TxMstCfgModeEnable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will enable multi-stream transport (MST) mode for the driver.
InstancePtr | is a pointer to the XDp instance. |
References XDp_GetCoreType.
void XDp_TxMstCfgStreamDisable | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream ID that will be disabled. |
References XDp_GetCoreType.
void XDp_TxMstCfgStreamEnable | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream ID that will be enabled. |
References XDp_GetCoreType.
u32 XDp_TxMstDisable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxMstEnable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u8 XDp_TxMstStreamIsEnabled | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function will check whether.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream ID to check for enable/disable status. |
References XDp_GetCoreType.
u32 XDp_TxRemoteDpcdRead | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u32 | DpcdAddress, | ||
u32 | BytesToRead, | ||
u8 * | ReadData | ||
) |
#include <xdp.h>
This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message.
In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
DpcdAddress | is the starting address to read from the RX device. |
BytesToRead | is the number of bytes to read. |
ReadData | is a pointer to the data buffer that will be filled with read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxRemoteDpcdWrite | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u32 | DpcdAddress, | ||
u32 | BytesToWrite, | ||
u8 * | WriteData | ||
) |
#include <xdp.h>
This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message.
In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
DpcdAddress | is the starting address to write to the RX device. |
BytesToWrite | is the number of bytes to write. |
WriteData | is a pointer to a buffer which will be used as the data source for the write. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxRemoteIicRead | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 | IicAddress, | ||
u16 | Offset, | ||
u16 | BytesToRead, | ||
u8 * | ReadData | ||
) |
#include <xdp.h>
This function performs a remote I2C read by sending a sideband message.
In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
IicAddress | is the address on the I2C bus of the target device. |
Offset | is the offset at the specified address of the targeted I2C device that the read will start from. |
BytesToRead | is the number of bytes to read. |
ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxRemoteIicWrite | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 | IicAddress, | ||
u8 | BytesToWrite, | ||
u8 * | WriteData | ||
) |
#include <xdp.h>
This function performs a remote I2C write by sending a sideband message.
In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
IicAddress | is the address on the I2C bus of the target device. |
BytesToWrite | is the number of bytes to write. |
WriteData | is a pointer to a buffer which will be used as the data source for the write. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxResetPhy | ( | XDp * | InstancePtr, |
u32 | Reset | ||
) |
#include <xdp.c>
This function does a PHY reset.
InstancePtr | is a pointer to the XDp instance. |
Reset | is the type of reset to assert. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgAllocatePayload | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 | VcId, | ||
u16 | Pbn | ||
) |
#include <xdp.h>
This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
VcId | is the unique virtual channel ID to allocate into the payload ID tables. |
Pbn | is the payload bandwidth number that determines how much bandwidth will be allocated for the virtual channel. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgClearPayloadIdTable | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables.
InstancePtr | is a pointer to the XDp instance. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgEnumPathResources | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u16 * | AvailPbn, | ||
u16 * | FullPbn | ||
) |
#include <xdp.h>
This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
AvailPbn | is a pointer to the available PBN of the path whose value will be filled in by this function. |
FullPbn | is a pointer to the total PBN of the path whose value will be filled in by this function. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgLinkAddress | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
XDp_SbMsgLinkAddressReplyDeviceInfo * | DeviceInfo | ||
) |
#include <xdp.h>
This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device.
It is used to determine the resources available for that device and some device information for each of the ports connected to the branch device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort branch device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort branch device. |
DeviceInfo | is a pointer to the device information structure whose contents will be filled in with the information obtained by the LINK_ADDRESS sideband message. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgRemoteDpcdRead | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u32 | DpcdAddress, | ||
u32 | BytesToRead, | ||
u8 * | ReadData | ||
) |
#include <xdp.h>
This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
DpcdAddress | is the DPCD address of the target device that data will be read from. |
BytesToRead | is the number of bytes to read from the specified DPCD address. |
ReadData | is a pointer to a buffer that will be filled with the DPCD read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgRemoteDpcdWrite | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u32 | DpcdAddress, | ||
u32 | BytesToWrite, | ||
u8 * | WriteData | ||
) |
#include <xdp.h>
This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
DpcdAddress | is the DPCD address of the target device that data will be written to. |
BytesToWrite | is the number of bytes to write to the specified DPCD address. |
WriteData | is a pointer to a buffer that stores the data to write to the DPCD location. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgRemoteIicRead | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 | IicDeviceId, | ||
u8 | Offset, | ||
u8 | BytesToRead, | ||
u8 * | ReadData | ||
) |
#include <xdp.h>
This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
IicDeviceId | is the address on the I2C bus of the target device. |
Offset | is the offset at the specified address of the targeted I2C device that the read will start from. |
BytesToRead | is the number of bytes to read from the I2C address. |
ReadData | is a pointer to a buffer that will be filled with the I2C read data. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSendSbMsgRemoteIicWrite | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 | IicDeviceId, | ||
u8 | BytesToWrite, | ||
u8 * | WriteData | ||
) |
#include <xdp.h>
This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target DisplayPort device. |
RelativeAddress | is the relative address from the DisplayPort source to the target DisplayPort device. |
IicDeviceId | is the address on the I2C bus of the target device. |
BytesToWrite | is the number of bytes to write to the I2C address. |
WriteData | is a pointer to a buffer that will be written. |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSetDownspread | ( | XDp * | InstancePtr, |
u8 | Enable | ||
) |
#include <xdp.c>
This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.
InstancePtr | is a pointer to the XDp instance. |
Enable | will downspread the main link signal if set to 1 and disable downspreading if set to 0. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetDrvHpdEventHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a driver's internal callback function for when a hot-plug-detect event interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_TxSetDrvHpdPulseHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a driver's internal callback function for when a hot-plug-detect pulse interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
u32 XDp_TxSetEnhancedFrameMode | ( | XDp * | InstancePtr, |
u8 | Enable | ||
) |
#include <xdp.c>
This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.
InstancePtr | is a pointer to the XDp instance. |
Enable | will enable enhanced frame mode if set to 1 and disable it if set to 0. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetHasRedriverInPath | ( | XDp * | InstancePtr, |
u8 | Set | ||
) |
#include <xdp.c>
This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path.
XDp_TxSetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.
InstancePtr | is a pointer to the XDp instance. |
Set | establishes that a redriver exists in the DisplayPort output path. |
References XDp_GetCoreType.
void XDp_TxSetHpdEventHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a hot-plug-detect event interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_TxSetHpdPulseHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
u32 XDp_TxSetLaneCount | ( | XDp * | InstancePtr, |
u8 | LaneCount | ||
) |
#include <xdp.c>
This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.
InstancePtr | is a pointer to the XDp instance. |
LaneCount | is the number of lanes to be used over the main link. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetLaneCountChangeCallback | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.c>
This function installs a callback function for when the driver's lane count change function is called either directly by the user or during link training.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
u32 XDp_TxSetLinkRate | ( | XDp * | InstancePtr, |
u8 | LinkRate | ||
) |
#include <xdp.c>
This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.
InstancePtr | is a pointer to the XDp instance. |
LinkRate | is the link rate to be used over the main link based on one of the following selects:
|
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetLinkRateChangeCallback | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.c>
This function installs a callback function for when the driver's link rate change function is called either directly by the user or during link training.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_TxSetMsaHandler | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.h>
This function installs a callback function for when the main stream attribute (MSA) values are updated.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_TxSetMsaValues | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to set the MSA values for. |
References XDp::IsReady, XDp_GetCoreType, XDP_TX_STREAM2_MSA_START_OFFSET, XDP_TX_STREAM3_MSA_START_OFFSET, and XDP_TX_STREAM4_MSA_START_OFFSET.
void XDp_TxSetPeVsAdjustCallback | ( | XDp * | InstancePtr, |
XDp_IntrHandler | CallbackFunc, | ||
void * | CallbackRef | ||
) |
#include <xdp.c>
This function installs a callback function for when the driver's link rate change function is called during link training.
InstancePtr | is a pointer to the XDp instance. |
CallbackFunc | is the address to the callback function. |
CallbackRef | is the user data item that will be passed to the callback function when it is invoked. |
References XDp_GetCoreType.
void XDp_TxSetPhyPolarityAll | ( | XDp * | InstancePtr, |
u8 | Polarity | ||
) |
#include <xdp.c>
This function sets the PHY polarity on all lanes.
InstancePtr | is a pointer to the XDp instance. |
Polarity | is the value to set for the polarity (0 or 1). |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetPhyPolarityLane | ( | XDp * | InstancePtr, |
u8 | Lane, | ||
u8 | Polarity | ||
) |
#include <xdp.c>
This function sets the PHY polarity on a specified lane.
InstancePtr | is a pointer to the XDp instance. |
Lane | is the lane number (0-3) to set the polarity for. |
Polarity | is the value to set for the polarity (0 or 1). |
References XDp::IsReady, and XDp_GetCoreType.
u32 XDp_TxSetScrambler | ( | XDp * | InstancePtr, |
u8 | Enable | ||
) |
#include <xdp.c>
This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.
InstancePtr | is a pointer to the XDp instance. |
Enable | will enable or disable scrambling. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetStreamSelectFromSinkList | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
u8 | SinkNum | ||
) |
#include <xdp.h>
This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream ID that will be mapped to a DisplayPort device. |
SinkNum | is the sink ID in the sink list that will be mapped to the stream. |
References XDp_GetCoreType.
void XDp_TxSetStreamSinkRad | ( | XDp * | InstancePtr, |
u8 | Stream, | ||
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress | ||
) |
#include <xdp.h>
This function will map a stream to a downstream DisplayPort TX device determined by the relative address.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number that will be mapped to a DisplayPort device. |
LinkCountTotal | is the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device. |
RelativeAddress | is the relative address from the DisplayPort source to the targeted DisplayPort device. |
References XDp_GetCoreType.
void XDp_TxSetUserPixelWidth | ( | XDp * | InstancePtr, |
u8 | UserPixelWidth | ||
) |
#include <xdp.h>
This function configures the number of pixels output through the user data interface for DisplayPort TX core.
InstancePtr | is a pointer to the XDp instance. |
UserPixelWidth | is the user pixel width to be configured. |
References XDp::IsReady, and XDp_GetCoreType.
void XDp_TxSetVideoMode | ( | XDp * | InstancePtr, |
u8 | Stream | ||
) |
#include <xdp.h>
This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.
InstancePtr | is a pointer to the XDp instance. |
Stream | is the stream number for which to set the MSA values for. |
References XDp::IsReady.
void XDp_TxTopologySortSinksByTiling | ( | XDp * | InstancePtr | ) |
#include <xdp.h>
Order the sink list with all sinks of the same tiled display being sorted by 'tile order'.
Refer to the XDp_TxGetDispIdTdtTileOrder macro on how to determine the 'tile order'. Sinks of a tiled display will have an index in the sink list that is lower than all indices of other sinks within that same tiled display that have a greater 'tile order'. When operations are done on the sink list, this ordering will ensure that sinks within the same tiled display will be acted upon in a consistent manner - with an incrementing sink list index, sinks with a lower 'tile order' will be acted upon first relative to the other sinks in the same tiled display. Multiple tiled displays may exist in the sink list.
InstancePtr | is a pointer to the XDp instance. |
References XDp_GetCoreType.
void XDp_TxTopologySwapSinks | ( | XDp * | InstancePtr, |
u8 | Index0, | ||
u8 | Index1 | ||
) |
#include <xdp.h>
Swap the ordering of the sinks in the topology's sink list.
All sink information is preserved in the node table - the swapping takes place only on the pointers to the sinks in the node table. The reason this swapping is done is so that functions that use the sink list will act on the sinks in a different order.
InstancePtr | is a pointer to the XDp instance. |
Index0 | is the sink list's index of one of the sink pointers to be swapped. |
Index1 | is the sink list's index of the other sink pointer to be swapped. |
References XDp_GetCoreType.
void XDp_TxWriteGuid | ( | XDp * | InstancePtr, |
u8 | LinkCountTotal, | ||
u8 * | RelativeAddress, | ||
u8 * | Guid | ||
) |
#include <xdp.h>
This function will write a global unique identifier (GUID) to the target DisplayPort device.
InstancePtr | is a pointer to the XDp instance. |
LinkCountTotal | is the number of DisplayPort links from the DisplayPort source to the target device. |
RelativeAddress | is the relative address from the DisplayPort source to the target device. |
Guid | is a pointer to the GUID to write to the target device. |
References XDp::IsReady, XDp_GetCoreType, and XDP_GUID_NBYTES.
void XDp_WaitUs | ( | XDp * | InstancePtr, |
u32 | MicroSeconds | ||
) |
#include <xdp.c>
This function is the delay/sleep function for the XDp driver.
For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.
InstancePtr | is a pointer to the XDp instance. |
MicroSeconds | is the number of microseconds to delay/sleep for. |
References XDp::IsReady, and XDp::UserTimerWaitUs.
u8 GuidTable[16][XDP_GUID_NBYTES] |
#include <xdp_mst.c>
This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function.
u32 RxResetValues[2][2] |
#include <xdp_selftest.c>
This table contains the default values for the DisplayPort RX core's general usage registers.
u32 TxResetValues[2][2] |
#include <xdp_selftest.c>
This table contains the default values for the DisplayPort TX core's general usage registers.
u32 TxResetValuesMsa[20][2] |
#include <xdp_selftest.c>
This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.
XDp_Config XDp_ConfigTable[XPAR_XDP_NUM_INSTANCES] |
#include <xdp_sinit.c>
A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.