rfdc
Xilinx SDK Drivers API Documentation
Rfdc_v2_0

Data Structures

struct  XRFdc_PLL_Settings
 PLL settings. More...
 
struct  XRFdc_QMC_Settings
 QMC settings. More...
 
struct  XRFdc_CoarseDelay_Settings
 Coarse delay settings. More...
 
struct  XRFdc_Mixer_Settings
 Mixer settings. More...
 
struct  XRFdc_Threshold_Settings
 ADC block Threshold settings. More...
 
struct  XRFdc_TileStatus
 RFSoC Tile status. More...
 
struct  XRFdc_IPStatus
 RFSoC Data converter IP status. More...
 
struct  XRFdc_BlockStatus
 status of DAC or ADC blocks in the RFSoC Data converter. More...
 
struct  XRFdc_DACBlock_AnalogDataPath_Config
 DAC block Analog DataPath Config settings. More...
 
struct  XRFdc_DACBlock_DigitalDataPath_Config
 DAC block Digital DataPath Config settings. More...
 
struct  XRFdc_ADCBlock_AnalogDataPath_Config
 ADC block Analog DataPath Config settings. More...
 
struct  XRFdc_ADCBlock_DigitalDataPath_Config
 DAC block Digital DataPath Config settings. More...
 
struct  XRFdc_DACTile_Config
 DAC Tile Config structure. More...
 
struct  XRFdc_ADCTile_Config
 ADC Tile Config Structure. More...
 
struct  XRFdc_Config
 RFdc Config Structure. More...
 
struct  XRFdc_DACBlock_AnalogDataPath
 DAC Block Analog DataPath Structure. More...
 
struct  XRFdc_DACBlock_DigitalDataPath
 DAC Block Digital DataPath Structure. More...
 
struct  XRFdc_ADCBlock_AnalogDataPath
 ADC Block Analog DataPath Structure. More...
 
struct  XRFdc_ADCBlock_DigitalDataPath
 ADC Block Digital DataPath Structure. More...
 
struct  XRFdc_DAC_Tile
 DAC Tile Structure. More...
 
struct  XRFdc_ADC_Tile
 ADC Tile Structure. More...
 
struct  XRFdc
 RFdc Structure. More...
 

Macros

#define XRFdc_ReadReg64(InstancePtr, BaseAddress, RegOffset)   XRFdc_In64(InstancePtr->io, (RegOffset + BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg64(InstancePtr, BaseAddress, RegOffset, RegisterValue)
 Write to a register. More...
 
#define XRFdc_ReadReg(InstancePtr, BaseAddress, RegOffset)   XRFdc_In32((InstancePtr->io), (BaseAddress + RegOffset))
 Read a register. More...
 
#define XRFdc_WriteReg(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out32((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))
 Write to a register. More...
 
#define XRFdc_ReadReg16(InstancePtr, BaseAddress, RegOffset)   XRFdc_In16((InstancePtr->io), (RegOffset + BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg16(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out16((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))
 Write to a register. More...
 
#define XRFdc_ReadReg8(InstancePtr, BaseAddress, RegOffset)   XRFdc_In8((InstancePtr->io), (RegOffset + BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg8(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out8((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))
 Write to a register. More...
 

Typedefs

typedef void(* XRFdc_StatusHandler) (void *CallBackRef, u32 Type, int Tile_Id, u32 Block_Id, u32 StatusEvent)
 The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...
 

Functions

XRFdc_ConfigXRFdc_LookupConfig (u16 DeviceId)
 Looks up the device configuration based on the unique device ID. More...
 
int XRFdc_CfgInitialize (XRFdc *InstancePtr, XRFdc_Config *Config)
 Initializes a specific XRFdc instance such that the driver is ready to use. More...
 
int XRFdc_StartUp (XRFdc *InstancePtr, u32 Type, int Tile_Id)
 The API Restarts the requested tile. More...
 
int XRFdc_Shutdown (XRFdc *InstancePtr, u32 Type, int Tile_Id)
 The API stops the tile as requested. More...
 
int XRFdc_Reset (XRFdc *InstancePtr, u32 Type, int Tile_Id)
 The API resets the requested tile. More...
 
int XRFdc_GetIPStatus (XRFdc *InstancePtr, XRFdc_IPStatus *IPStatus)
 The API returns the IP status. More...
 
int XRFdc_GetBlockStatus (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatus)
 The API returns the requested block status. More...
 
int XRFdc_SetMixerSettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *Mixer_Settings)
 The API is used to update various mixer settings, fine, coarse, NCO etc. More...
 
int XRFdc_GetMixerSettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *Mixer_Settings)
 The API returns back Mixer/NCO settings to the caller. More...
 
int XRFdc_SetQMCSettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMC_Settings)
 This API is used to update various QMC settings, eg gain, phase, offset etc. More...
 
int XRFdc_GetQMCSettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMC_Settings)
 QMC settings are returned back to the caller through this API. More...
 
int XRFdc_GetCoarseDelaySettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelay_Settings)
 Coarse delay settings are returned back to the caller. More...
 
int XRFdc_SetCoarseDelaySettings (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelay_Settings)
 Coarse delay settings passed are used to update the corresponding block level registers. More...
 
int XRFdc_GetInterpolationFactor (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 *InterpolationFactor)
 Interpolation factor are returned back to the caller. More...
 
int XRFdc_GetDecimationFactor (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 *DecimationFactor)
 Decimation factor are returned back to the caller. More...
 
int XRFdc_GetFabWrVldWords (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 *FabricDataRate)
 This API returns the the number of fabric write valid words requested for the block. More...
 
int XRFdc_GetFabRdVldWords (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 *FabricDataRate)
 This API returns the the number of fabric read valid words requested for the block. More...
 
int XRFdc_SetFabRdVldWords (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 FabricDataRate)
 Fabric data rate for the requested ADC block is set by writing to the corresponding register. More...
 
int XRFdc_SetFabWrVldWords (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 FabricDataRate)
 Fabric data rate for the requested DAC block is set by writing to the corresponding register. More...
 
int XRFdc_GetThresholdSettings (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *Threshold_Settings)
 Threshold settings are read from the corresponding registers and are passed back to the caller. More...
 
int XRFdc_SetThresholdSettings (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *Threshold_Settings)
 Threshold settings are updated into the relevant registers. More...
 
int XRFdc_SetDecoderMode (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 DecoderMode)
 Decoder mode is updated into the relevant registers. More...
 
int XRFdc_UpdateEvent (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 Event)
 This function will trigger the update event for an event. More...
 
int XRFdc_GetDecoderMode (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, u32 *DecoderMode)
 Decoder mode is read and returned back. More...
 
int XRFdc_ResetNCOPhase (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id)
 Resets the NCO phase of the current block phase accumulator. More...
 
void XRFdc_DumpRegs (XRFdc *InstancePtr, u32 Type, int Tile_Id)
 This Prints the offset of the register along with the content. More...
 
void XRFdc_SetSignalFlow (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 AnalogDataPath, u32 ConnectIData, u32 ConnectQData)
 Sets up multiband configuration. More...
 
void XRFdc_GetSignalFlow (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 AnalogDataPath, u32 *ConnectedIData, u32 *ConnectedQData)
 Reads back the multiband configuration. More...
 
int XRFdc_IntrHandler (int Vector, void *XRFdcPtr)
 This function is the interrupt handler for the driver. More...
 
void XRFdc_IntrClr (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 IntrMask)
 This function clear the interrupts. More...
 
u32 XRFdc_GetIntrStatus (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id)
 This function returns the interrupt status read from Interrupt Status Register(ISR). More...
 
void XRFdc_IntrDisable (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 IntrMask)
 This function clears the interrupt mask. More...
 
void XRFdc_IntrEnable (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 IntrMask)
 This function sets the interrupt mask. More...
 
void XRFdc_SetStatusHandler (XRFdc *InstancePtr, void *CallBackRef, XRFdc_StatusHandler FunctionPtr)
 This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More...
 
int XRFdc_SetupFIFO (XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable)
 Enable and Disable the ADC/DAC FIFO. More...
 
int XRFdc_SetNyquistZone (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 NyquistZone)
 Set the Nyquist zone. More...
 
int XRFdc_GetNyquistZone (XRFdc *InstancePtr, u32 Type, int Tile_Id, u32 Block_Id, u32 *NyquistZone)
 Get the Nyquist zone. More...
 
int XRFdc_GetOutputCurr (XRFdc *InstancePtr, int Tile_Id, u32 Block_Id, int *OutputCurr)
 Get Output Current for DAC block. More...
 

Variables

XRFdc_Config XRFdc_ConfigTable [XPAR_XRFDC_NUM_INSTANCES]
 The configuration table for devices. More...
 
XRFdc_Config XRFdc_ConfigTable []
 The configuration table for devices. More...
 

Register Map

Register offsets from the base address of an RFDC ADC and DAC device.

#define XRFDC_CLK_EN_OFFSET   0x000U
 ADC Clock Enable Register. More...
 
#define XRFDC_ADC_DEBUG_RST_OFFSET   0x004U
 ADC Debug Reset Register. More...
 
#define XRFDC_ADC_FABRIC_RATE_OFFSET   0x008U
 ADC Fabric Rate Register. More...
 
#define XRFDC_ADC_FABRIC_OFFSET   0x00CU
 ADC Fabric Register. More...
 
#define XRFDC_ADC_FABRIC_ISR_OFFSET   0x010U
 ADC Fabric ISR Register. More...
 
#define XRFDC_DAC_FABRIC_ISR_OFFSET   0x014U
 DAC Fabric ISR Register. More...
 
#define XRFDC_ADC_FABRIC_IMR_OFFSET   0x014U
 ADC Fabric IMR Register. More...
 
#define XRFDC_DAC_FABRIC_IMR_OFFSET   0x018U
 DAC Fabric IMR Register. More...
 
#define XRFDC_ADC_FABRIC_DBG_OFFSET   0x018U
 ADC Fabric Debug Register. More...
 
#define XRFDC_ADC_UPDATE_DYN_OFFSET   0x01CU
 ADC Update Dynamic Register. More...
 
#define XRFDC_DAC_UPDATE_DYN_OFFSET   0x020U
 DAC Update Dynamic Register. More...
 
#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET   0x020U
 ADC FIFO Latency Control Register. More...
 
#define XRFDC_ADC_DEC_ISR_OFFSET   0x030U
 ADC Decoder interface ISR Register. More...
 
#define XRFDC_ADC_DEC_IMR_OFFSET   0x034U
 ADC Decoder interface IMR Register. More...
 
#define XRFDC_DATPATH_ISR_OFFSET   0x038U
 ADC Data Path ISR Register. More...
 
#define XRFDC_DATPATH_IMR_OFFSET   0x03CU
 ADC Data Path IMR Register. More...
 
#define XRFDC_ADC_DECI_CONFIG_OFFSET   0x040U
 ADC Decimation Config Register. More...
 
#define XRFDC_DAC_INTERP_CTRL_OFFSET   0x040U
 DAC Interpolation Control Register. More...
 
#define XRFDC_ADC_DECI_MODE_OFFSET   0x044U
 ADC Decimation mode Register. More...
 
#define XRFDC_ADC_MXR_CFG0_OFFSET   0x080U
 ADC I channel mixer config Register. More...
 
#define XRFDC_ADC_MXR_CFG1_OFFSET   0x084U
 ADC Q channel mixer config Register. More...
 
#define XRFDC_MXR_MODE_OFFSET   0x088U
 ADC/DAC mixer mode Register. More...
 
#define XRFDC_NCO_UPDT_OFFSET   0x08CU
 ADC/DAC NCO Update mode Register. More...
 
#define XRFDC_NCO_RST_OFFSET   0x090U
 ADC/DAC NCO Phase Reset Register. More...
 
#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET   0x094U
 ADC NCO Frequency Word[47:32] Register. More...
 
#define XRFDC_ADC_NCO_FQWD_MID_OFFSET   0x098U
 ADC NCO Frequency Word[31:16] Register. More...
 
#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET   0x09CU
 ADC NCO Frequency Word[15:0] Register. More...
 
#define XRFDC_NCO_PHASE_UPP_OFFSET   0x0A0U
 ADC/DAC NCO Phase[17:16] Register. More...
 
#define XRFDC_NCO_PHASE_LOW_OFFSET   0x0A4U
 ADC/DAC NCO Phase[15:0] Register. More...
 
#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET   0x0A8U
 ADC NCO Phase Mode Register. More...
 
#define XRFDC_QMC_UPDT_OFFSET   0x0C8U
 ADC/DAC QMC Update Mode Register. More...
 
#define XRFDC_QMC_CFG_OFFSET   0x0CCU
 ADC/DAC QMC Config Register. More...
 
#define XRFDC_QMC_OFF_OFFSET   0x0D0U
 ADC/DAC QMC Offset Correction Register. More...
 
#define XRFDC_QMC_GAIN_OFFSET   0x0D4U
 ADC/DAC QMC Gain Correction Register. More...
 
#define XRFDC_QMC_PHASE_OFFSET   0x0D8U
 ADC/DAC QMC Phase Correction Register. More...
 
#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET   0x0DCU
 ADC Coarse Delay Update Register. More...
 
#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET   0x0E0U
 DAC Coarse Delay Update Register. More...
 
#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET   0x0E0U
 ADC Coarse delay Config Register. More...
 
#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET   0x0DCU
 DAC Coarse delay Config Register. More...
 
#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET   0x0E4U
 ADC Data Scaling Config Register. More...
 
#define XRFDC_ADC_SWITCH_MATRX_OFFSET   0x0E8U
 ADC Switch Matrix Config Register. More...
 
#define XRFDC_ADC_TRSHD0_CFG_OFFSET   0x0ECU
 ADC Threshold0 Config Register. More...
 
#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET   0x0F0U
 ADC Threshold0 Average[31:16] Register. More...
 
#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET   0x0F4U
 ADC Threshold0 Average[15:0] Register. More...
 
#define XRFDC_ADC_TRSHD0_UNDER_OFFSET   0x0F8U
 ADC Threshold0 Under Threshold Register. More...
 
#define XRFDC_ADC_TRSHD0_OVER_OFFSET   0x0FCU
 ADC Threshold0 Over Threshold Register. More...
 
#define XRFDC_ADC_TRSHD1_CFG_OFFSET   0x100U
 ADC Threshold1 Config Register. More...
 
#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET   0x104U
 ADC Threshold1 Average[31:16] Register. More...
 
#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET   0x108U
 ADC Threshold1 Average[15:0] Register. More...
 
#define XRFDC_ADC_TRSHD1_UNDER_OFFSET   0x10CU
 ADC Threshold1 Under Threshold Register. More...
 
#define XRFDC_ADC_TRSHD1_OVER_OFFSET   0x110U
 ADC Threshold1 Over Threshold Register. More...
 
#define XRFDC_ADC_FEND_DAT_CRL_OFFSET   0x140U
 ADC Front end Data Control Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL0_OFFSET   0x144U
 ADC Time Interleaved digital correction block gain control0 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL1_OFFSET   0x148U
 ADC Time Interleaved digital correction block gain control1 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL2_OFFSET   0x14CU
 ADC Time Interleaved digital correction block gain control2 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL3_OFFSET   0x150U
 ADC Time Interleaved digital correction block gain control3 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL0_OFFSET   0x154U
 ADC Time skew correction control bits0 Register. More...
 
#define XRFDC_DAC_MC_CFG0_OFFSET   0x1C4U
 Static Configuration data for DAC Analog. More...
 
#define XRFDC_ADC_TI_TISK_CRL1_OFFSET   0x158U
 ADC Time skew correction control bits1 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL2_OFFSET   0x15CU
 ADC Time skew correction control bits2 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL3_OFFSET   0x160U
 ADC Time skew correction control bits3 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL4_OFFSET   0x164U
 ADC Time skew correction control bits4 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC0_OFFSET   0x168U
 ADC Time skew DAC cal code of subadc ch0 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC1_OFFSET   0x16CU
 ADC Time skew DAC cal code of subadc ch1 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC2_OFFSET   0x170U
 ADC Time skew DAC cal code of subadc ch2 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC3_OFFSET   0x174U
 ADC Time skew DAC cal code of subadc ch3 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP0_OFFSET   0x178U
 ADC Time skew DAC cal code of subadc ch0 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP1_OFFSET   0x17CU
 ADC Time skew DAC cal code of subadc ch1 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP2_OFFSET   0x180U
 ADC Time skew DAC cal code of subadc ch2 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP3_OFFSET   0x184U
 ADC Time skew DAC cal code of subadc ch3 Register. More...
 
#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET   0x198U
 subadc0, sub-drp address of target Register More...
 
#define XRFDC_ADC0_SUBDRP_DAT_OFFSET   0x19CU
 subadc0, sub-drp data of target Register More...
 
#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET   0x1A0U
 subadc1, sub-drp address of target Register More...
 
#define XRFDC_ADC1_SUBDRP_DAT_OFFSET   0x1A4U
 subadc1, sub-drp data of target Register More...
 
#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET   0x1A8U
 subadc2, sub-drp address of target Register More...
 
#define XRFDC_ADC2_SUBDRP_DAT_OFFSET   0x1ACU
 subadc2, sub-drp data of target Register More...
 
#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET   0x1B0U
 subadc3, sub-drp address of target Register More...
 
#define XRFDC_ADC3_SUBDRP_DAT_OFFSET   0x1B4U
 subadc3, sub-drp data of target Register More...
 
#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET   0x1C0U
 ADC Static configuration bits for ADC(RX) analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG0_OFFSET   0x1C4U
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG1_OFFSET   0x1C8U
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG2_OFFSET   0x1CCU
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_DAC_MC_CFG3_OFFSET   0x1D0U
 DAC Static configuration bits for DAC analog Register. More...
 
#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET   0x1D0U
 ADC RX Pair static Configuration Register. More...
 
#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET   0x1D4U
 ADC RX Pair static Configuration Register. More...
 
#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET   0x200U
 ADC DCB Status0 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET   0x204U
 ADC DCB Status0 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET   0x208U
 ADC DCB Status1 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET   0x20CU
 ADC DCB Status1 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET   0x210U
 ADC DCB Status2 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET   0x214U
 ADC DCB Status2 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET   0x218U
 ADC DCB Status3 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET   0x21CU
 ADC DCB Status3 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET   0x220U
 ADC DCB Status4 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET   0x224U
 ADC DCB Status4 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET   0x228U
 ADC DCB Status5 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET   0x22CU
 ADC DCB Status5 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET   0x230U
 ADC DCB Status6 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET   0x234U
 ADC DCB Status6 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET   0x238U
 ADC DCB Status7 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET   0x23CU
 ADC DCB Status7 LSB Register. More...
 
#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET   0x280U
 ADC FIFO Latency measurement LSB Register. More...
 
#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET   0x284U
 ADC FIFO Latency measurement MSB Register. More...
 
#define XRFDC_DAC_DECODER_CTRL_OFFSET   0x180U
 DAC Unary Decoder/ Randomizer settings. More...
 
#define XRFDC_HSCOM_PWR_OFFSET   0x094
 Control register during power-up sequence. More...
 
#define XRFDC_HSCOM_UPDT_DYN_OFFSET   0x0B8
 Trigger the update dynamic event. More...
 
#define XRFDC_RESET_OFFSET   0x00U
 Tile reset register. More...
 
#define XRFDC_RESTART_OFFSET   0x04U
 Tile restart register. More...
 
#define XRFDC_RESTART_STATE_OFFSET   0x08U
 Tile restart state register. More...
 
#define XRFDC_CURRENT_STATE_OFFSET   0x0CU
 Current state register. More...
 
#define XRFDC_STATUS_OFFSET   0x228U
 Common status register. More...
 
#define XRFDC_COMMON_INTR_STS   0x100U
 Common Intr Status register. More...
 
#define XRFDC_COMMON_INTR_ENABLE   0x104U
 Common Intr enable register. More...
 
#define XRFDC_INTR_STS   0x200U
 Intr status register. More...
 
#define XRFDC_INTR_ENABLE   0x204U
 Intr enable register. More...
 
#define XRFDC_CONV_INTR_STS(X)   (0x208U + (X * 0x08))
 
#define XRFDC_CONV_INTR_EN(X)   (0x20CU + (X * 0x08))
 
#define XRFDC_FIFO_ENABLE   0x230U
 FIFO Enable and Disable. More...
 

FIFO Enable - FIFO enable and disable register

This register contains bits for FIFO enable and disable for ADC and DAC.

#define XRFDC_FIFO_EN_MASK   0x00000001U
 FIFO enable/disable. More...
 

Clock Enable - FIFO Latency, fabric, DataPath,

full-rate, output register

This register contains bits for various clock enable options of the ADC. Read/Write apart from the reserved bits.

#define XRFDC_CLK_EN_CAL_MASK   0x00000001U
 Enable Output Register clock. More...
 
#define XRFDC_CLK_EN_DIG_MASK   0x00000002U
 Enable full-rate clock. More...
 
#define XRFDC_CLK_EN_DP_MASK   0x00000004U
 Enable Data Path clock. More...
 
#define XRFDC_CLK_EN_FAB_MASK   0x00000008U
 Enable fabric clock. More...
 
#define XRFDC_DAT_CLK_EN_MASK   0x0000000FU
 Data Path Clk enable. More...
 
#define XRFDC_CLK_EN_LM_MASK   0x00000010U
 Enable for FIFO Latency measurement clock. More...
 

Debug reset - FIFO Latency, fabric, DataPath,

full-rate, output register

This register contains bits for various Debug reset options of the ADC. Read/Write apart from the reserved bits.

#define XRFDC_DBG_RST_CAL_MASK   0x00000001U
 Reset clk_cal clock domain. More...
 
#define XRFDC_DBG_RST_DP_MASK   0x00000002U
 Reset data path clock domain. More...
 
#define XRFDC_DBG_RST_FAB_MASK   0x00000004U
 Reset clock fabric clock domain. More...
 
#define XRFDC_DBG_RST_DIG_MASK   0x00000008U
 Reset clk_dig clock domain. More...
 
#define XRFDC_DBG_RST_DRP_CAL_MASK   0x00000010U
 Reset subadc-drp register on clock cal. More...
 
#define XRFDC_DBG_RST_LM_MASK   0x00000020U
 Reset FIFO Latency measurement clock domain. More...
 

Fabric rate - Fabric data rate for read and write

This register contains bits for read and write fabric data rate for ADC.

Read/Write apart from the reserved bits.

#define XRFDC_ADC_FAB_RATE_WR_MASK   0x0000000FU
 ADC FIFO Write Number of Words per clock. More...
 
#define XRFDC_DAC_FAB_RATE_WR_MASK   0x0000001FU
 DAC FIFO Write Number of Words per clock. More...
 
#define XRFDC_FAB_RATE_RD_MASK   0x00000F00U
 FIFO Read Number of words per clock. More...
 

Fabric Offset - FIFO de-skew

This register contains bits of Fabric Offset.

Read/Write apart from the reserved bits.

#define XRFDC_FAB_RD_PTR_OFFST_MASK   0x0000003FU
 FIFO read pointer offset for interface de-skew. More...
 

Fabric ISR - Interrupt status register for FIFO interface

This register contains bits of margin-indicator and user-data overlap (overflow/underflow).

Read/Write apart from the reserved bits.

#define XRFDC_FAB_ISR_USRDAT_OVR_MASK   0x00000001U
 User-data overlap- data written faster than read (overflow) More...
 
#define XRFDC_FAB_ISR_USRDAT_UND_MASK   0x00000002U
 User-data overlap- data read faster than written (underflow) More...
 
#define XRFDC_FAB_ISR_USRDAT_MASK   0x00000003U
 User-data overlap Mask. More...
 
#define XRFDC_FAB_ISR_MARGIND_OVR_MASK   0x00000004U
 Marginal-indicator overlap (overflow) More...
 
#define XRFDC_FAB_ISR_MARGIND_UND_MASK   0x00000008U
 Marginal-indicator overlap (underflow) More...
 

Fabric IMR - Interrupt mask register for FIFO interface

This register contains bits of margin-indicator and user-data overlap (overflow/underflow).

Read/Write apart from the reserved bits.

#define XRFDC_FAB_IMR_USRDAT_OVR_MASK   0x00000001U
 User-data overlap- data written faster than read (overflow) More...
 
#define XRFDC_FAB_IMR_USRDAT_UND_MASK   0x00000002U
 User-data overlap- data read faster than written (underflow) More...
 
#define XRFDC_FAB_IMR_USRDAT_MASK   0x00000003U
 User-data overlap Mask. More...
 
#define XRFDC_FAB_IMR_MARGIND_OVR_MASK   0x00000004U
 Marginal-indicator overlap (overflow) More...
 
#define XRFDC_FAB_IMR_MARGIND_UND_MASK   0x00000008U
 Marginal-indicator overlap (underflow) More...
 

Update Dynamic - Trigger a dynamic update event

This register contains bits of update event for slice, nco, qmc and coarse delay.

Read/Write apart from the reserved bits.

#define XRFDC_UPDT_EVNT_MASK   0x0000000FU
 Update event mask. More...
 
#define XRFDC_UPDT_EVNT_SLICE_MASK   0x00000001U
 Trigger a slice update event apply to _DCONFIG reg. More...
 
#define XRFDC_UPDT_EVNT_NCO_MASK   0x00000002U
 Trigger a update event apply to NCO_DCONFIG reg. More...
 
#define XRFDC_UPDT_EVNT_QMC_MASK   0x00000004U
 Trigger a update event apply to QMC_DCONFIG reg. More...
 
#define XRFDC_ADC_UPDT_CRSE_DLY_MASK   0x00000008U
 ADC Trigger a update event apply to Coarse delay_DCONFIG reg. More...
 
#define XRFDC_DAC_UPDT_CRSE_DLY_MASK   0x00000020U
 DAC Trigger a update event apply to Coarse delay_DCONFIG reg. More...
 

FIFO Latency control - Config registers for FIFO Latency measurement

This register contains bits of FIFO Latency ctrl for disable, restart and set fifo latency measurement.

Read/Write apart from the reserved bits.

#define XRFDC_FIFO_LTNCY_PRD_MASK   0x00000007U
 Set FIFO Latency measurement period. More...
 
#define XRFDC_FIFO_LTNCY_RESTRT_MASK   0x00000008U
 Restart FIFO Latency measurement. More...
 
#define XRFDC_FIFO_LTNCY_DIS_MASK   0x000000010U
 Disable FIFO Latency measurement. More...
 

Decode ISR - ISR for Decoder Interface

This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_ISR_SUBADC_MASK   0x000000FFU
 subadc decoder Mask More...
 
#define XRFDC_DEC_ISR_SUBADC0_UND_MASK   0x00000001U
 subadc0 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK   0x00000002U
 subadc0 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC1_UND_MASK   0x00000004U
 subadc1 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK   0x00000008U
 subadc1 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC2_UND_MASK   0x00000010U
 subadc2 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK   0x00000020U
 subadc2 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC3_UND_MASK   0x00000040U
 subadc3 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK   0x00000080U
 subadc3 decoder overflow range More...
 

Decode IMR - IMR for Decoder Interface

This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_IMR_SUBADC0_UND_MASK   0x00000001U
 subadc0 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK   0x00000002U
 subadc0 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC1_UND_MASK   0x00000004U
 subadc1 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK   0x00000008U
 subadc1 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC2_UND_MASK   0x00000010U
 subadc2 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK   0x00000020U
 subadc2 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC3_UND_MASK   0x00000040U
 subadc3 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK   0x00000080U
 subadc3 decoder overflow range More...
 

DataPath ISR - ISR for Data Path interface

This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.

Read/Write apart from the reserved bits.

#define XRFDC_ADC_DAT_PATH_ISR_MASK   0x000000FFU
 ADC Data Path Overflow. More...
 
#define XRFDC_DAC_DAT_PATH_ISR_MASK   0x000001FFU
 DAC Data Path Overflow. More...
 
#define XRFDC_DAT_ISR_DECI_IPATH_MASK   0x00000007U
 Decimation I-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_ISR_INTR_QPATH_MASK   0x00000038U
 Interpolation Q-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_ISR_QMC_GAIN_MASK   0x00000040U
 QMC Gain/Phase overflow. More...
 
#define XRFDC_DAT_ISR_QMC_OFFST_MASK   0x00000080U
 QMC offset overflow. More...
 
#define XRFDC_DAC_DAT_ISR_INVSINC_MASK   0x00000100U
 Inverse Sinc offset overflow. More...
 

DataPath IMR - IMR for Data Path interface

This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.

Read/Write apart from the reserved bits.

#define XRFDC_DAT_IMR_DECI_IPATH_MASK   0x00000007U
 Decimation I-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_IMR_INTR_QPATH_MASK   0x00000038U
 Interpolation Q-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_IMR_QMC_GAIN_MASK   0x00000040U
 QMC Gain/Phase overflow. More...
 
#define XRFDC_DAT_IMR_QMC_OFFST_MASK   0x00000080U
 QMC offset overflow. More...
 

Decimation Config - Decimation control

This register contains bits to configure the decimation in terms of the type of data.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_CFG_MASK   0x00000003U
 ChannelA (2GSPS real data from Mixer I output) More...
 
#define XRFDC_DEC_CFG_CHB_MASK   0x00000001U
 ChannelB (2GSPS real data from Mixer Q output) More...
 
#define XRFDC_DEC_CFG_IQ_MASK   0x00000002U
 IQ-2GSPS. More...
 
#define XRFDC_DEC_CFG_4GSPS_MASK   0x00000003U
 4GSPS may be I or Q or Real depending on high level block config More...
 

Decimation Mode - Decimation Rate

This register contains bits to configures the decimation rate.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_MOD_MASK   0x00000007U
 Decimation mode Mask. More...
 
#define XRFDC_DEC_MOD_1X_MASK   0x00000001U
 1x (decimation bypass) More...
 
#define XRFDC_DEC_MOD_2X_MASK   0x00000002U
 2x (decimation bypass) More...
 
#define XRFDC_DEC_MOD_4X_MASK   0x00000003U
 4x (decimation bypass) More...
 
#define XRFDC_DEC_MOD_8X_MASK   0x00000004U
 8x (decimation bypass) More...
 
#define XRFDC_DEC_MOD_2X_BW_MASK   0x00000005U
 2x (med BW) More...
 
#define XRFDC_DEC_MOD_4X_BW_MASK   0x00000006U
 4x (med BW) More...
 
#define XRFDC_DEC_MOD_8X_BW_MASK   0x00000007U
 8x (med BW) More...
 

Mixer config0 - Configure I channel coarse mixer mode of operation

This register contains bits to set the output data sequence of I channel.

Read/Write apart from the reserved bits.

#define XRFDC_MIX_CFG0_MASK   0x00000FFFU
 Mixer Config0 Mask. More...
 
#define XRFDC_MIX_I_DAT_WRD0_MASK   0x00000007U
 Output data word[0] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD1_MASK   0x00000038U
 Output data word[1] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD2_MASK   0x000001C0U
 Output data word[2] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD3_MASK   0x00000E00U
 Output data word[3] of I channel. More...
 

Mixer config1 - Configure Q channel coarse mixer mode of operation

This register contains bits to set the output data sequence of Q channel.

Read/Write apart from the reserved bits.

#define XRFDC_MIX_CFG1_MASK   0x00000FFFU
 Mixer Config0 Mask. More...
 
#define XRFDC_MIX_Q_DAT_WRD0_MASK   0x00000007U
 Output data word[0] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD1_MASK   0x00000038U
 Output data word[1] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD2_MASK   0x000001C0U
 Output data word[2] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD3_MASK   0x00000E00U
 Output data word[3] of Q channel. More...
 

Mixer mode - Configure mixer mode of operation

This register contains bits to set NCO phases, NCO output scale and fine mixer multipliers.

Read/Write apart from the reserved bits.

#define XRFDC_EN_I_IQ_MASK   0x00000003U
 Enable fine mixer multipliers on IQ i/p for I output. More...
 
#define XRFDC_EN_Q_IQ_MASK   0x0000000CU
 Enable fine mixer multipliers on IQ i/p for Q output. More...
 
#define XRFDC_FINE_MIX_SCALE_MASK   0x00000010U
 NCO output scale. More...
 
#define XRFDC_SEL_I_IQ_MASK   0x00000F00U
 Select NCO phases for I output. More...
 
#define XRFDC_SEL_Q_IQ_MASK   0x0000F000U
 Select NCO phases for Q output. More...
 
#define XRFDC_I_IQ_COS_MINSIN   0x00000C00U
 Select NCO phases for I output. More...
 
#define XRFDC_Q_IQ_SIN_COS   0x00001000U
 Select NCO phases for Q output. More...
 

NCO update - NCO update mode

This register contains bits to Select event source, delay and reset delay.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_UPDT_MODE_MASK   0x00000007U
 NCO event source selection mask. More...
 
#define XRFDC_NCO_UPDT_MODE_GRP   0x00000000U
 NCO event source selection is Group. More...
 
#define XRFDC_NCO_UPDT_MODE_SLICE   0x00000001U
 NCO event source selection is slice. More...
 
#define XRFDC_NCO_UPDT_MODE_TILE   0x00000002U
 NCO event source selection is tile. More...
 
#define XRFDC_NCO_UPDT_MODE_SYSREF   0x00000003U
 NCO event source selection is Sysref. More...
 
#define XRFDC_NCO_UPDT_MODE_MARKER   0x00000004U
 NCO event source selection is Marker. More...
 
#define XRFDC_NCO_UPDT_MODE_FABRIC   0x00000005U
 NCO event source selection is fabric. More...
 
#define XRFDC_NCO_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 
#define XRFDC_NCO_UPDT_RST_DLY_MASK   0x0000D000U
 optional delay on the NCO phase reset delay More...
 

NCO Phase Reset - NCO Slice Phase Reset

This register contains bits to reset the nco phase of the current slice phase accumulator.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_RST_MASK   0x00000001U
 Reset NCO Phase of current slice. More...
 

NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_UPP_MASK   0x0000FFFFU
 NCO Phase increment[47:32]. More...
 

NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_MID_MASK   0x0000FFFFU
 NCO Phase increment[31:16]. More...
 

NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_LOW_MASK   0x0000FFFFU
 NCO Phase increment[15:0]. More...
 
#define XRFDC_NCO_FQWD_MASK   0x0000FFFFFFFFFFFFU
 NCO Freq offset[48:0]. More...
 

NCO Phase Offset[17:16] - NCO Phase offset

This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_UPP_MASK   0x00000003U
 NCO Phase offset[17:16]. More...
 

NCO Phase Offset[15:0] - NCO Phase offset

This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_LOW_MASK   0x0000FFFFU
 NCO Phase offset[15:0]. More...
 
#define XRFDC_NCO_PHASE_MASK   0x0003FFFFU
 NCO Phase offset[17:0]. More...
 

NCO Phase mode - NCO Control setting mode

This register contains bits to set NCO mode of operation.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_MOD_MASK   0x00000003U
 NCO mode of operation mask. More...
 
#define XRFDC_NCO_PHASE_MOD_4PHASE   0x00000003U
 NCO output 4 successive phase. More...
 
#define XRFDC_NCO_PHASE_MOD_EVEN   0x00000001U
 NCO output even phase. More...
 
#define XRFDC_NCO_PHASE_MODE_ODD   0x00000002U
 NCO output odd phase. More...
 

QMC update - QMC update mode

This register contains bits to Select event source and delay.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_UPDT_MODE_MASK   0x00000007U
 QMC event source selection mask. More...
 
#define XRFDC_QMC_UPDT_MODE_GRP   0x00000000U
 QMC event source selection is group. More...
 
#define XRFDC_QMC_UPDT_MODE_SLICE   0x00000001U
 QMC event source selection is slice. More...
 
#define XRFDC_QMC_UPDT_MODE_TILE   0x00000002U
 QMC event source selection is tile. More...
 
#define XRFDC_QMC_UPDT_MODE_SYSREF   0x00000003U
 QMC event source selection is Sysref. More...
 
#define XRFDC_QMC_UPDT_MODE_MARKER   0x00000004U
 QMC event source selection is Marker. More...
 
#define XRFDC_QMC_UPDT_MODE_FABRIC   0x00000005U
 QMC event source selection is fabric. More...
 
#define XRFDC_QMC_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 

QMC Config - QMC Config register

This register contains bits to enable QMC gain and QMC Phase correction.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_CFG_EN_GAIN_MASK   0x00000001U
 enable QMC gain correction mask More...
 
#define XRFDC_QMC_CFG_EN_PHASE_MASK   0x00000002U
 enable QMC Phase correction mask More...
 

QMC Offset - QMC offset correction

This register contains bits to set QMC offset correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_OFFST_CRCTN_MASK   0x00000FFFU
 QMC offset correction factor. More...
 

QMC Gain - QMC Gain correction

This register contains bits to set QMC gain correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_GAIN_CRCTN_MASK   0x00003FFFU
 QMC gain correction factor. More...
 

QMC Phase - QMC Phase correction

This register contains bits to set QMC phase correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_PHASE_CRCTN_MASK   0x00000FFFU
 QMC phase correction factor. More...
 

Coarse Delay Update - Coarse delay update mode.

This register contains bits to Select event source and delay.

Read/Write apart from the reserved bits.

#define XRFDC_CRSEDLY_UPDT_MODE_MASK   0x00000007U
 Coarse delay event source selection mask. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_GRP   0x00000000U
 Coarse delay event source selection is group. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_SLICE   0x00000001U
 Coarse delay event source selection is slice. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_TILE   0x00000002U
 Coarse delay event source selection is tile. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF   0x00000003U
 Coarse delay event source selection is sysref. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_MARKER   0x00000004U
 Coarse delay event source selection is Marker. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC   0x00000005U
 Coarse delay event source selection is fabric. More...
 
#define XRFDC_CRSEDLY_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 

Coarse delay Config - Coarse delay select

This register contains bits to select coarse delay.

Read/Write apart from the reserved bits.

#define XRFDC_CRSE_DLY_CFG_MASK   0x00000007U
 Coarse delay select. More...
 

Data Scaling Config - Data Scaling enable

This register contains bits to enable data scaling.

Read/Write apart from the reserved bits.

#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U
 Enable data scaling. More...
 
#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U
 Enable data scaling. More...
 

Switch Matrix Config

This register contains bits to control crossbar switch that select data to mixer block.

Read/Write apart from the reserved bits.

#define XRFDC_SEL_CB_TO_MIX1_MASK   0x00000003U
 Control crossbar switch that select the data to mixer block mux1. More...
 
#define XRFDC_SEL_CB_TO_MIX0_MASK   0x0000000CU
 Control crossbar switch that select the data to mixer block mux0. More...
 
#define XRFDC_SEL_CB_TO_QMC_MASK   0x00000010U
 Control crossbar switch that select the data to QMC. More...
 
#define XRFDC_SEL_CB_TO_DECI_MASK   0x00000020U
 Control crossbar switch that select the data to decimation filter. More...
 

Threshold0 Config

This register contains bits to select mode, clear mode and to clear sticky bit.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_EN_MOD_MASK   0x00000003U
 Enable Threshold0 block. More...
 
#define XRFDC_TRSHD0_CLR_MOD_MASK   0x00000004U
 Clear mode. More...
 
#define XRFDC_TRSHD0_STIKY_CLR_MASK   0x00000008U
 Clear sticky bit. More...
 

Threshold0 Average[31:16]

This register contains bits to select Threshold0 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_AVG_UPP_MASK   0x0000FFFFU
 Threshold0 under Averaging[31:16]. More...
 

Threshold0 Average[15:0]

This register contains bits to select Threshold0 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_AVG_LOW_MASK   0x0000FFFFU
 Threshold0 under Averaging[15:0]. More...
 

Threshold0 Under threshold

This register contains bits to select Threshold0 under threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_UNDER_MASK   0x00007FFFU
 Threshold0 under Threshold[14:0]. More...
 

Threshold0 Over threshold

This register contains bits to select Threshold0 over threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_OVER_MASK   0x00007FFFU
 Threshold0 under Threshold[14:0]. More...
 

Threshold1 Config

This register contains bits to select mode, clear mode and to clear sticky bit.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_EN_MOD_MASK   0x00000003U
 Enable Threshold1 block. More...
 
#define XRFDC_TRSHD1_CLR_MOD_MASK   0x00000004U
 Clear mode. More...
 
#define XRFDC_TRSHD1_STIKY_CLR_MASK   0x00000008U
 Clear sticky bit. More...
 

Threshold1 Average[31:16]

This register contains bits to select Threshold1 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_AVG_UPP_MASK   0x0000FFFFU
 Threshold1 under Averaging[31:16]. More...
 

Threshold1 Average[15:0]

This register contains bits to select Threshold1 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_AVG_LOW_MASK   0x0000FFFFU
 Threshold1 under Averaging[15:0]. More...
 

Threshold1 Under threshold

This register contains bits to select Threshold1 under threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_UNDER_MASK   0x00007FFFU
 Threshold1 under Threshold[14:0]. More...
 

Threshold1 Over threshold

This register contains bits to select Threshold1 over threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_OVER_MASK   0x00007FFFU
 Threshold1 under Threshold[14:0]. More...
 

FrontEnd Data Control

This register contains bits to select raw data and cal coefficient to be streamed to memory.

Read/Write apart from the reserved bits.

#define XRFDC_FEND_DAT_CTRL_MASK   0x000000FFU
 raw data and cal coefficient to be streamed to memory More...
 

TI Digital Correction Block control0

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL0_MASK   0x0000FFFFU
 TI DCB gain and offset correction. More...
 

TI Digital Correction Block control1

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL1_MASK   0x00001FFFU
 TI DCB gain and offset correction. More...
 

TI Digital Correction Block control2

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL2_MASK   0x00001FFFU
 TI DCB gain and offset correction. More...
 

TI Time Skew control0

This register contains bits for Time skew correction control bits0(enables, mode, multiplier factors, debug).

Read/Write apart from the reserved bits.

#define XRFDC_TI_TISK_EN_MASK   0x00000001U
 Block Enable. More...
 
#define XRFDC_TI_TISK_MODE_MASK   0x00000002U
 Mode (2G/4G) More...
 
#define XRFDC_TI_TISK_ZONE_MASK   0x00000004U
 Specifies Nyquist zone. More...
 
#define XRFDC_TI_TISK_CHOP_EN_MASK   0x00000008U
 enable chopping mode More...
 
#define XRFDC_TI_TISK_MU_CM_MASK   0x000000F0U
 Constant mu_cm multiplying common mode path. More...
 
#define XRFDC_TI_TISK_MU_DF_MASK   0x00000F00U
 Constant mu_df multiplying differential path. More...
 
#define XRFDC_TI_TISK_DBG_CTRL_MASK   0x0000F000U
 Debug control. More...
 
#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK   0x00001000U
 Debug update rate. More...
 
#define XRFDC_TI_TISK_DITH_DLY_MASK   0x0000E000U
 Programmable delay on dither path to match data path. More...
 
#define XRFDC_TISK_EN_MASK   0x00000001U
 Block Enable. More...
 
#define XRFDC_TISK_MODE_MASK   0x00000002U
 Mode (2G/4G) More...
 
#define XRFDC_TISK_ZONE_MASK   0x00000004U
 Specifies Nyquist zone. More...
 
#define XRFDC_TISK_CHOP_EN_MASK   0x00000008U
 enable chopping mode More...
 
#define XRFDC_TISK_MU_CM_MASK   0x000000F0U
 Constant mu_cm multiplying common mode path. More...
 
#define XRFDC_TISK_MU_DF_MASK   0x00000F00U
 Constant mu_df multiplying differential path. More...
 
#define XRFDC_TISK_DBG_CTRL_MASK   0x0000F000U
 Debug control. More...
 
#define XRFDC_TISK_DBG_UPDT_RT_MASK   0x00001000U
 Debug update rate. More...
 
#define XRFDC_TISK_DITH_DLY_MASK   0x0000E000U
 Programmable delay on dither path to match data path. More...
 

DAC MC Config0

This register contains bits for enable/disable shadow logic , Nyquist zone selction, enable full speed clock, Programmable delay.

#define XRFDC_MC_CFG0_MIX_MODE_MASK   0x00000002U
 Enable Mixing mode. More...
 

TI Time Skew control1

This register contains bits for Time skew correction control bits1 (Deadzone Parameters).

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DZ_MIN_VAL_MASK   0x000000FFU
 Deadzone min. More...
 
#define XRFDC_TISK_DZ_MAX_VAL_MASK   0x0000FF00U
 Deadzone max. More...
 

TI Time Skew control2

This register contains bits for Time skew correction control bits2 (Filter parameters).

Read/Write apart from the reserved bits.

#define XRFDC_TISK_MU0_MASK   0x0000000FU
 Filter0 multiplying factor. More...
 
#define XRFDC_TISK_BYPASS0_MASK   0x00000080U
 ByPass filter0. More...
 
#define XRFDC_TISK_MU1_MASK   0x00000F00U
 Filter1 multiplying factor. More...
 
#define XRFDC_TISK_BYPASS1_MASK   0x00008000U
 Filter1 multiplying factor. More...
 

TI Time Skew control3

This register contains bits for Time skew control settling time following code update.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_SETTLE_MASK   0x000000FFU
 Settling time following code update. More...
 

TI Time Skew control4

This register contains bits for Time skew control setting time following code update.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_CAL_PRI_MASK   0x00000001U
 
#define XRFDC_TISK_DITH_INV_MASK   0x00000FF0U
 

TI Time Skew DAC0

This register contains bits for Time skew DAC cal code of subadc ch0.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC0_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch0 front end switch0. More...
 
#define XRFDC_TISK_DAC0_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DAC1

This register contains bits for Time skew DAC cal code of subadc ch1.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC1_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch1 front end switch0. More...
 
#define XRFDC_TISK_DAC1_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DAC2

This register contains bits for Time skew DAC cal code of subadc ch2.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC2_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch2 front end switch0. More...
 
#define XRFDC_TISK_DAC2_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DAC3

This register contains bits for Time skew DAC cal code of subadc ch3.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC3_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch3 front end switch0. More...
 
#define XRFDC_TISK_DAC3_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DACP0

This register contains bits for Time skew DAC cal code of subadc ch0.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP0_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch0 front end switch1. More...
 
#define XRFDC_TISK_DACP0_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DACP1

This register contains bits for Time skew DAC cal code of subadc ch1.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP1_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch1 front end switch1. More...
 
#define XRFDC_TISK_DACP1_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DACP2

This register contains bits for Time skew DAC cal code of subadc ch2.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP2_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch2 front end switch1. More...
 
#define XRFDC_TISK_DACP2_OVRID_EN_MASK   0x00008000U
 override enable More...
 

TI Time Skew DACP3

This register contains bits for Time skew DAC cal code of subadc ch3.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP3_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch3 front end switch1. More...
 
#define XRFDC_TISK_DACP3_OVRID_EN_MASK   0x00008000U
 override enable More...
 

SubDRP ADC0 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC0_ADDR_MASK   0x000000FFU
 sub-drp0 address More...
 

SubDRP ADC0 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC0_DAT_MASK   0x0000FFFFU
 sub-drp0 data for read or write transaction More...
 

SubDRP ADC1 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC1_ADDR_MASK   0x000000FFU
 sub-drp1 address More...
 

SubDRP ADC1 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC1_DAT_MASK   0x0000FFFFU
 sub-drp1 data for read or write transaction More...
 

SubDRP ADC2 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC2_ADDR_MASK   0x000000FFU
 sub-drp2 address More...
 

SubDRP ADC2 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC2_DAT_MASK   0x0000FFFFU
 sub-drp2 data for read or write transaction More...
 

SubDRP ADC3 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC3_ADDR_MASK   0x000000FFU
 sub-drp3 address More...
 

SubDRP ADC3 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC3_DAT_MASK   0x0000FFFFU
 sub-drp3 data for read or write transaction More...
 

RX MC PWRDWN

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_PWRDWN_MASK   0x0000FFFFU
 RX MC power down. More...
 

RX MC Config0

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG0_MASK   0x0000FFFFU
 RX MC config0. More...
 

RX MC Config1

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG1_MASK   0x0000FFFFU
 RX MC Config1. More...
 

RX MC Config2

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG2_MASK   0x0000FFFFU
 RX MC Config2. More...
 

RX Pair MC Config0

This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_PR_MC_CFG0_MASK   0x0000FFFFU
 RX Pair MC Config0. More...
 

RX Pair MC Config1

This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_PR_MC_CFG1_MASK   0x0000FFFFU
 RX Pair MC Config1. More...
 

TI DCB Status0 BG

This register contains the subadc ch0 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS0_BG_MASK   0x0000FFFFU
 DCB Status0 BG. More...
 

TI DCB Status0 FG

This register contains the subadc ch0 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS0_FG_MASK   0x0000FFFFU
 DCB Status0 FG. More...
 

TI DCB Status1 BG

This register contains the subadc ch1 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS1_BG_MASK   0x0000FFFFU
 DCB Status1 BG. More...
 

TI DCB Status1 FG

This register contains the subadc ch1 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS1_FG_MASK   0x0000FFFFU
 DCB Status1 FG. More...
 

TI DCB Status2 BG

This register contains the subadc ch2 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS2_BG_MASK   0x0000FFFFU
 DCB Status2 BG. More...
 

TI DCB Status2 FG

This register contains the subadc ch2 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS2_FG_MASK   0x0000FFFFU
 DCB Status2 FG. More...
 

TI DCB Status3 BG

This register contains the subadc ch3 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS3_BG_MASK   0x0000FFFFU
 DCB Status3 BG. More...
 

TI DCB Status3 FG

This register contains the subadc ch3 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS3_FG_MASK   0x0000FFFFU
 DCB Status3 FG. More...
 

TI DCB Status4 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS4_MSB_MASK   0x0000FFFFU
 read the status of gcb acc0 msb bits(subadc chan0) More...
 

TI DCB Status4 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS4_LSB_MASK   0x0000FFFFU
 read the status of gcb acc0 lsb bits(subadc chan0) More...
 

TI DCB Status5 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS5_MSB_MASK   0x0000FFFFU
 read the status of gcb acc1 msb bits(subadc chan1) More...
 

TI DCB Status5 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS5_LSB_MASK   0x0000FFFFU
 read the status of gcb acc1 lsb bits(subadc chan1) More...
 

TI DCB Status6 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS6_MSB_MASK   0x0000FFFFU
 read the status of gcb acc2 msb bits(subadc chan2) More...
 

TI DCB Status6 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS6_LSB_MASK   0x0000FFFFU
 read the status of gcb acc2 lsb bits(subadc chan2) More...
 

TI DCB Status7 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS7_MSB_MASK   0x0000FFFFU
 read the status of gcb acc3 msb bits(subadc chan3) More...
 

TI DCB Status7 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS7_LSB_MASK   0x0000FFFFU
 read the status of gcb acc3 lsb bits(subadc chan3) More...
 

FIFO Latency

This register contains bits for result, key and done flag.

Read/Write apart from the reserved bits.

#define XRFDC_FIFO_LTNCY_RES_MASK   0x00000FFFU
 Latency measurement result. More...
 
#define XRFDC_FIFO_LTNCY_KEY_MASK   0x00004000U
 Latency measurement result identification key. More...
 
#define XRFDC_FIFO_LTNCY_DONE_MASK   0x00008000U
 Latency measurement done flag. More...
 

Decoder Control

This register contains Unary Decoder/Randomizer settings to use.

#define XRFDC_DEC_CTRL_MODE_MASK   0x00000007U
 Decoder mode. More...
 

HSCOM Power state mask

This register contains HSCOM_PWR to check powerup_state.

#define XRFDC_HSCOM_PWR_STATE_MASK   0x0000FFFFU
 powerup state mask More...
 

Interpolation Control

This register contains Interpolation filter modes.

#define XRFDC_INTERP_MODE_MASK   0x00000007U
 Interpolation filter mode mask. More...
 

Tile Reset

This register contains Tile reset bit.

#define XRFDC_TILE_RESET_MASK   0x00000001U
 Tile reset mask. More...
 

Status register

This register contains common status bits.

#define XRFDC_PWR_UP_STAT_MASK   0x00000004U
 Power Up state mask. More...
 
#define XRFDC_PLL_LOCKED_MASK   0x00000008U
 PLL Locked mask. More...
 

Restart State register

This register contains Start and End state bits.

#define XRFDC_PWR_STATE_MASK   0x0000FFFFU
 State mask. More...
 

Common interrupt enable register

This register contains bits to enable interrupt for ADC and DAC tiles.

#define XRFDC_EN_INTR_DAC_TILE0_MASK   0x00000001U
 DAC Tile0 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE1_MASK   0x00000002U
 DAC Tile1 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE2_MASK   0x00000004U
 DAC Tile2 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE3_MASK   0x00000008U
 DAC Tile3 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE0_MASK   0x00000010U
 ADC Tile0 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE1_MASK   0x00000020U
 ADC Tile1 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE2_MASK   0x00000040U
 ADC Tile2 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE3_MASK   0x00000080U
 ADC Tile3 interrupt enable mask. More...
 

interrupt enable register

This register contains bits to enable interrupt for blocks.

#define XRFDC_EN_INTR_SLICE0_MASK   0x00000001U
 slice0 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE1_MASK   0x00000002U
 slice1 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE2_MASK   0x00000004U
 slice2 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE3_MASK   0x00000008U
 slice3 interrupt enable mask More...
 

Converter(X) interrupt register

This register contains bits to enable different interrupts for block X.

#define XRFDC_INTR_OVR_RANGE_MASK   0x00000008U
 Over Range interrupt mask. More...
 
#define XRFDC_INTR_OVR_VOLTAGE_MASK   0x00000004U
 Over Voltage interrupt mask. More...
 

Macro Definition Documentation

◆ XRFDC_ADC0_SUBDRP_ADDR_OFFSET

#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET   0x198U

#include <xrfdc_hw.h>

subadc0, sub-drp address of target Register

◆ XRFDC_ADC0_SUBDRP_DAT_OFFSET

#define XRFDC_ADC0_SUBDRP_DAT_OFFSET   0x19CU

#include <xrfdc_hw.h>

subadc0, sub-drp data of target Register

◆ XRFDC_ADC1_SUBDRP_ADDR_OFFSET

#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET   0x1A0U

#include <xrfdc_hw.h>

subadc1, sub-drp address of target Register

◆ XRFDC_ADC1_SUBDRP_DAT_OFFSET

#define XRFDC_ADC1_SUBDRP_DAT_OFFSET   0x1A4U

#include <xrfdc_hw.h>

subadc1, sub-drp data of target Register

◆ XRFDC_ADC2_SUBDRP_ADDR_OFFSET

#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET   0x1A8U

#include <xrfdc_hw.h>

subadc2, sub-drp address of target Register

◆ XRFDC_ADC2_SUBDRP_DAT_OFFSET

#define XRFDC_ADC2_SUBDRP_DAT_OFFSET   0x1ACU

#include <xrfdc_hw.h>

subadc2, sub-drp data of target Register

◆ XRFDC_ADC3_SUBDRP_ADDR_OFFSET

#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET   0x1B0U

#include <xrfdc_hw.h>

subadc3, sub-drp address of target Register

◆ XRFDC_ADC3_SUBDRP_DAT_OFFSET

#define XRFDC_ADC3_SUBDRP_DAT_OFFSET   0x1B4U

#include <xrfdc_hw.h>

subadc3, sub-drp data of target Register

◆ XRFDC_ADC_CRSE_DLY_CFG_OFFSET

#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET   0x0E0U

#include <xrfdc_hw.h>

ADC Coarse delay Config Register.

◆ XRFDC_ADC_CRSE_DLY_UPDT_OFFSET

#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET   0x0DCU

#include <xrfdc_hw.h>

ADC Coarse Delay Update Register.

◆ XRFDC_ADC_DAC_MC_CFG0_OFFSET

#define XRFDC_ADC_DAC_MC_CFG0_OFFSET   0x1C4U

#include <xrfdc_hw.h>

ADC/DAC Static configuration bits for ADC/DAC analog Register.

◆ XRFDC_ADC_DAC_MC_CFG1_OFFSET

#define XRFDC_ADC_DAC_MC_CFG1_OFFSET   0x1C8U

#include <xrfdc_hw.h>

ADC/DAC Static configuration bits for ADC/DAC analog Register.

◆ XRFDC_ADC_DAC_MC_CFG2_OFFSET

#define XRFDC_ADC_DAC_MC_CFG2_OFFSET   0x1CCU

#include <xrfdc_hw.h>

ADC/DAC Static configuration bits for ADC/DAC analog Register.

◆ XRFDC_ADC_DAT_PATH_ISR_MASK

#define XRFDC_ADC_DAT_PATH_ISR_MASK   0x000000FFU

#include <xrfdc_hw.h>

ADC Data Path Overflow.

◆ XRFDC_ADC_DAT_SCAL_CFG_OFFSET

#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET   0x0E4U

#include <xrfdc_hw.h>

ADC Data Scaling Config Register.

◆ XRFDC_ADC_DEBUG_RST_OFFSET

#define XRFDC_ADC_DEBUG_RST_OFFSET   0x004U

#include <xrfdc_hw.h>

ADC Debug Reset Register.

◆ XRFDC_ADC_DEC_IMR_OFFSET

#define XRFDC_ADC_DEC_IMR_OFFSET   0x034U

#include <xrfdc_hw.h>

ADC Decoder interface IMR Register.

◆ XRFDC_ADC_DEC_ISR_OFFSET

#define XRFDC_ADC_DEC_ISR_OFFSET   0x030U

#include <xrfdc_hw.h>

ADC Decoder interface ISR Register.

◆ XRFDC_ADC_DECI_CONFIG_OFFSET

#define XRFDC_ADC_DECI_CONFIG_OFFSET   0x040U

#include <xrfdc_hw.h>

ADC Decimation Config Register.

◆ XRFDC_ADC_DECI_MODE_OFFSET

#define XRFDC_ADC_DECI_MODE_OFFSET   0x044U

#include <xrfdc_hw.h>

ADC Decimation mode Register.

◆ XRFDC_ADC_FAB_RATE_WR_MASK

#define XRFDC_ADC_FAB_RATE_WR_MASK   0x0000000FU

#include <xrfdc_hw.h>

ADC FIFO Write Number of Words per clock.

◆ XRFDC_ADC_FABRIC_DBG_OFFSET

#define XRFDC_ADC_FABRIC_DBG_OFFSET   0x018U

#include <xrfdc_hw.h>

ADC Fabric Debug Register.

◆ XRFDC_ADC_FABRIC_IMR_OFFSET

#define XRFDC_ADC_FABRIC_IMR_OFFSET   0x014U

#include <xrfdc_hw.h>

ADC Fabric IMR Register.

◆ XRFDC_ADC_FABRIC_ISR_OFFSET

#define XRFDC_ADC_FABRIC_ISR_OFFSET   0x010U

#include <xrfdc_hw.h>

ADC Fabric ISR Register.

◆ XRFDC_ADC_FABRIC_OFFSET

#define XRFDC_ADC_FABRIC_OFFSET   0x00CU

#include <xrfdc_hw.h>

ADC Fabric Register.

◆ XRFDC_ADC_FABRIC_RATE_OFFSET

#define XRFDC_ADC_FABRIC_RATE_OFFSET   0x008U

#include <xrfdc_hw.h>

ADC Fabric Rate Register.

◆ XRFDC_ADC_FEND_DAT_CRL_OFFSET

#define XRFDC_ADC_FEND_DAT_CRL_OFFSET   0x140U

#include <xrfdc_hw.h>

ADC Front end Data Control Register.

◆ XRFDC_ADC_FIFO_LTNC_CRL_OFFSET

#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET   0x020U

#include <xrfdc_hw.h>

ADC FIFO Latency Control Register.

◆ XRFDC_ADC_FIFO_LTNCY_LB_OFFSET

#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET   0x280U

#include <xrfdc_hw.h>

ADC FIFO Latency measurement LSB Register.

◆ XRFDC_ADC_FIFO_LTNCY_MB_OFFSET

#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET   0x284U

#include <xrfdc_hw.h>

ADC FIFO Latency measurement MSB Register.

◆ XRFDC_ADC_MXR_CFG0_OFFSET

#define XRFDC_ADC_MXR_CFG0_OFFSET   0x080U

#include <xrfdc_hw.h>

ADC I channel mixer config Register.

◆ XRFDC_ADC_MXR_CFG1_OFFSET

#define XRFDC_ADC_MXR_CFG1_OFFSET   0x084U

#include <xrfdc_hw.h>

ADC Q channel mixer config Register.

◆ XRFDC_ADC_NCO_FQWD_LOW_OFFSET

#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET   0x09CU

#include <xrfdc_hw.h>

ADC NCO Frequency Word[15:0] Register.

◆ XRFDC_ADC_NCO_FQWD_MID_OFFSET

#define XRFDC_ADC_NCO_FQWD_MID_OFFSET   0x098U

#include <xrfdc_hw.h>

ADC NCO Frequency Word[31:16] Register.

◆ XRFDC_ADC_NCO_FQWD_UPP_OFFSET

#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET   0x094U

#include <xrfdc_hw.h>

ADC NCO Frequency Word[47:32] Register.

◆ XRFDC_ADC_NCO_PHASE_MOD_OFFSET

#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET   0x0A8U

#include <xrfdc_hw.h>

ADC NCO Phase Mode Register.

◆ XRFDC_ADC_RX_MC_PWRDWN_OFFSET

#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET   0x1C0U

#include <xrfdc_hw.h>

ADC Static configuration bits for ADC(RX) analog Register.

◆ XRFDC_ADC_RXPR_MC_CFG0_OFFSET

#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET   0x1D0U

#include <xrfdc_hw.h>

ADC RX Pair static Configuration Register.

◆ XRFDC_ADC_RXPR_MC_CFG1_OFFSET

#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET   0x1D4U

#include <xrfdc_hw.h>

ADC RX Pair static Configuration Register.

◆ XRFDC_ADC_SWITCH_MATRX_OFFSET

#define XRFDC_ADC_SWITCH_MATRX_OFFSET   0x0E8U

#include <xrfdc_hw.h>

ADC Switch Matrix Config Register.

◆ XRFDC_ADC_TI_DCB_CRL0_OFFSET

#define XRFDC_ADC_TI_DCB_CRL0_OFFSET   0x144U

#include <xrfdc_hw.h>

ADC Time Interleaved digital correction block gain control0 Register.

◆ XRFDC_ADC_TI_DCB_CRL1_OFFSET

#define XRFDC_ADC_TI_DCB_CRL1_OFFSET   0x148U

#include <xrfdc_hw.h>

ADC Time Interleaved digital correction block gain control1 Register.

◆ XRFDC_ADC_TI_DCB_CRL2_OFFSET

#define XRFDC_ADC_TI_DCB_CRL2_OFFSET   0x14CU

#include <xrfdc_hw.h>

ADC Time Interleaved digital correction block gain control2 Register.

◆ XRFDC_ADC_TI_DCB_CRL3_OFFSET

#define XRFDC_ADC_TI_DCB_CRL3_OFFSET   0x150U

#include <xrfdc_hw.h>

ADC Time Interleaved digital correction block gain control3 Register.

◆ XRFDC_ADC_TI_DCBSTS0_BG_OFFSET

#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET   0x200U

#include <xrfdc_hw.h>

ADC DCB Status0 BG Register.

◆ XRFDC_ADC_TI_DCBSTS0_FG_OFFSET

#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET   0x204U

#include <xrfdc_hw.h>

ADC DCB Status0 FG Register.

◆ XRFDC_ADC_TI_DCBSTS1_BG_OFFSET

#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET   0x208U

#include <xrfdc_hw.h>

ADC DCB Status1 BG Register.

◆ XRFDC_ADC_TI_DCBSTS1_FG_OFFSET

#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET   0x20CU

#include <xrfdc_hw.h>

ADC DCB Status1 FG Register.

◆ XRFDC_ADC_TI_DCBSTS2_BG_OFFSET

#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET   0x210U

#include <xrfdc_hw.h>

ADC DCB Status2 BG Register.

◆ XRFDC_ADC_TI_DCBSTS2_FG_OFFSET

#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET   0x214U

#include <xrfdc_hw.h>

ADC DCB Status2 FG Register.

◆ XRFDC_ADC_TI_DCBSTS3_BG_OFFSET

#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET   0x218U

#include <xrfdc_hw.h>

ADC DCB Status3 BG Register.

◆ XRFDC_ADC_TI_DCBSTS3_FG_OFFSET

#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET   0x21CU

#include <xrfdc_hw.h>

ADC DCB Status3 FG Register.

◆ XRFDC_ADC_TI_DCBSTS4_LB_OFFSET

#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET   0x224U

#include <xrfdc_hw.h>

ADC DCB Status4 LSB Register.

◆ XRFDC_ADC_TI_DCBSTS4_MB_OFFSET

#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET   0x220U

#include <xrfdc_hw.h>

ADC DCB Status4 MSB Register.

◆ XRFDC_ADC_TI_DCBSTS5_LB_OFFSET

#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET   0x22CU

#include <xrfdc_hw.h>

ADC DCB Status5 LSB Register.

◆ XRFDC_ADC_TI_DCBSTS5_MB_OFFSET

#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET   0x228U

#include <xrfdc_hw.h>

ADC DCB Status5 MSB Register.

◆ XRFDC_ADC_TI_DCBSTS6_LB_OFFSET

#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET   0x234U

#include <xrfdc_hw.h>

ADC DCB Status6 LSB Register.

◆ XRFDC_ADC_TI_DCBSTS6_MB_OFFSET

#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET   0x230U

#include <xrfdc_hw.h>

ADC DCB Status6 MSB Register.

◆ XRFDC_ADC_TI_DCBSTS7_LB_OFFSET

#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET   0x23CU

#include <xrfdc_hw.h>

ADC DCB Status7 LSB Register.

◆ XRFDC_ADC_TI_DCBSTS7_MB_OFFSET

#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET   0x238U

#include <xrfdc_hw.h>

ADC DCB Status7 MSB Register.

◆ XRFDC_ADC_TI_TISK_CRL0_OFFSET

#define XRFDC_ADC_TI_TISK_CRL0_OFFSET   0x154U

#include <xrfdc_hw.h>

ADC Time skew correction control bits0 Register.

◆ XRFDC_ADC_TI_TISK_CRL1_OFFSET

#define XRFDC_ADC_TI_TISK_CRL1_OFFSET   0x158U

#include <xrfdc_hw.h>

ADC Time skew correction control bits1 Register.

◆ XRFDC_ADC_TI_TISK_CRL2_OFFSET

#define XRFDC_ADC_TI_TISK_CRL2_OFFSET   0x15CU

#include <xrfdc_hw.h>

ADC Time skew correction control bits2 Register.

◆ XRFDC_ADC_TI_TISK_CRL3_OFFSET

#define XRFDC_ADC_TI_TISK_CRL3_OFFSET   0x160U

#include <xrfdc_hw.h>

ADC Time skew correction control bits3 Register.

◆ XRFDC_ADC_TI_TISK_CRL4_OFFSET

#define XRFDC_ADC_TI_TISK_CRL4_OFFSET   0x164U

#include <xrfdc_hw.h>

ADC Time skew correction control bits4 Register.

◆ XRFDC_ADC_TI_TISK_DAC0_OFFSET

#define XRFDC_ADC_TI_TISK_DAC0_OFFSET   0x168U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch0 Register.

◆ XRFDC_ADC_TI_TISK_DAC1_OFFSET

#define XRFDC_ADC_TI_TISK_DAC1_OFFSET   0x16CU

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch1 Register.

◆ XRFDC_ADC_TI_TISK_DAC2_OFFSET

#define XRFDC_ADC_TI_TISK_DAC2_OFFSET   0x170U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch2 Register.

◆ XRFDC_ADC_TI_TISK_DAC3_OFFSET

#define XRFDC_ADC_TI_TISK_DAC3_OFFSET   0x174U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch3 Register.

◆ XRFDC_ADC_TI_TISK_DACP0_OFFSET

#define XRFDC_ADC_TI_TISK_DACP0_OFFSET   0x178U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch0 Register.

◆ XRFDC_ADC_TI_TISK_DACP1_OFFSET

#define XRFDC_ADC_TI_TISK_DACP1_OFFSET   0x17CU

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch1 Register.

◆ XRFDC_ADC_TI_TISK_DACP2_OFFSET

#define XRFDC_ADC_TI_TISK_DACP2_OFFSET   0x180U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch2 Register.

◆ XRFDC_ADC_TI_TISK_DACP3_OFFSET

#define XRFDC_ADC_TI_TISK_DACP3_OFFSET   0x184U

#include <xrfdc_hw.h>

ADC Time skew DAC cal code of subadc ch3 Register.

◆ XRFDC_ADC_TRSHD0_AVG_LO_OFFSET

#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET   0x0F4U

#include <xrfdc_hw.h>

ADC Threshold0 Average[15:0] Register.

◆ XRFDC_ADC_TRSHD0_AVG_UP_OFFSET

#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET   0x0F0U

#include <xrfdc_hw.h>

ADC Threshold0 Average[31:16] Register.

◆ XRFDC_ADC_TRSHD0_CFG_OFFSET

#define XRFDC_ADC_TRSHD0_CFG_OFFSET   0x0ECU

#include <xrfdc_hw.h>

ADC Threshold0 Config Register.

◆ XRFDC_ADC_TRSHD0_OVER_OFFSET

#define XRFDC_ADC_TRSHD0_OVER_OFFSET   0x0FCU

#include <xrfdc_hw.h>

ADC Threshold0 Over Threshold Register.

◆ XRFDC_ADC_TRSHD0_UNDER_OFFSET

#define XRFDC_ADC_TRSHD0_UNDER_OFFSET   0x0F8U

#include <xrfdc_hw.h>

ADC Threshold0 Under Threshold Register.

◆ XRFDC_ADC_TRSHD1_AVG_LO_OFFSET

#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET   0x108U

#include <xrfdc_hw.h>

ADC Threshold1 Average[15:0] Register.

◆ XRFDC_ADC_TRSHD1_AVG_UP_OFFSET

#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET   0x104U

#include <xrfdc_hw.h>

ADC Threshold1 Average[31:16] Register.

◆ XRFDC_ADC_TRSHD1_CFG_OFFSET

#define XRFDC_ADC_TRSHD1_CFG_OFFSET   0x100U

#include <xrfdc_hw.h>

ADC Threshold1 Config Register.

◆ XRFDC_ADC_TRSHD1_OVER_OFFSET

#define XRFDC_ADC_TRSHD1_OVER_OFFSET   0x110U

#include <xrfdc_hw.h>

ADC Threshold1 Over Threshold Register.

◆ XRFDC_ADC_TRSHD1_UNDER_OFFSET

#define XRFDC_ADC_TRSHD1_UNDER_OFFSET   0x10CU

#include <xrfdc_hw.h>

ADC Threshold1 Under Threshold Register.

◆ XRFDC_ADC_UPDATE_DYN_OFFSET

#define XRFDC_ADC_UPDATE_DYN_OFFSET   0x01CU

#include <xrfdc_hw.h>

ADC Update Dynamic Register.

◆ XRFDC_ADC_UPDT_CRSE_DLY_MASK

#define XRFDC_ADC_UPDT_CRSE_DLY_MASK   0x00000008U

#include <xrfdc_hw.h>

ADC Trigger a update event apply to Coarse delay_DCONFIG reg.

◆ XRFDC_CLK_EN_CAL_MASK

#define XRFDC_CLK_EN_CAL_MASK   0x00000001U

#include <xrfdc_hw.h>

Enable Output Register clock.

◆ XRFDC_CLK_EN_DIG_MASK

#define XRFDC_CLK_EN_DIG_MASK   0x00000002U

#include <xrfdc_hw.h>

Enable full-rate clock.

◆ XRFDC_CLK_EN_DP_MASK

#define XRFDC_CLK_EN_DP_MASK   0x00000004U

#include <xrfdc_hw.h>

Enable Data Path clock.

◆ XRFDC_CLK_EN_FAB_MASK

#define XRFDC_CLK_EN_FAB_MASK   0x00000008U

#include <xrfdc_hw.h>

Enable fabric clock.

◆ XRFDC_CLK_EN_LM_MASK

#define XRFDC_CLK_EN_LM_MASK   0x00000010U

#include <xrfdc_hw.h>

Enable for FIFO Latency measurement clock.

◆ XRFDC_CLK_EN_OFFSET

#define XRFDC_CLK_EN_OFFSET   0x000U

#include <xrfdc_hw.h>

ADC Clock Enable Register.

◆ XRFDC_COMMON_INTR_ENABLE

#define XRFDC_COMMON_INTR_ENABLE   0x104U

#include <xrfdc_hw.h>

Common Intr enable register.

◆ XRFDC_COMMON_INTR_STS

#define XRFDC_COMMON_INTR_STS   0x100U

#include <xrfdc_hw.h>

Common Intr Status register.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_CRSE_DLY_CFG_MASK

#define XRFDC_CRSE_DLY_CFG_MASK   0x00000007U

#include <xrfdc_hw.h>

Coarse delay select.

◆ XRFDC_CRSEDLY_UPDT_DLY_MASK

#define XRFDC_CRSEDLY_UPDT_DLY_MASK   0x00001FF8U

#include <xrfdc_hw.h>

delay in clk_dp cycles in application of event after arrival

◆ XRFDC_CRSEDLY_UPDT_MODE_FABRIC

#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC   0x00000005U

#include <xrfdc_hw.h>

Coarse delay event source selection is fabric.

◆ XRFDC_CRSEDLY_UPDT_MODE_GRP

#define XRFDC_CRSEDLY_UPDT_MODE_GRP   0x00000000U

#include <xrfdc_hw.h>

Coarse delay event source selection is group.

◆ XRFDC_CRSEDLY_UPDT_MODE_MARKER

#define XRFDC_CRSEDLY_UPDT_MODE_MARKER   0x00000004U

#include <xrfdc_hw.h>

Coarse delay event source selection is Marker.

◆ XRFDC_CRSEDLY_UPDT_MODE_MASK

#define XRFDC_CRSEDLY_UPDT_MODE_MASK   0x00000007U

#include <xrfdc_hw.h>

Coarse delay event source selection mask.

◆ XRFDC_CRSEDLY_UPDT_MODE_SLICE

#define XRFDC_CRSEDLY_UPDT_MODE_SLICE   0x00000001U

#include <xrfdc_hw.h>

Coarse delay event source selection is slice.

◆ XRFDC_CRSEDLY_UPDT_MODE_SYSREF

#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF   0x00000003U

#include <xrfdc_hw.h>

Coarse delay event source selection is sysref.

◆ XRFDC_CRSEDLY_UPDT_MODE_TILE

#define XRFDC_CRSEDLY_UPDT_MODE_TILE   0x00000002U

#include <xrfdc_hw.h>

Coarse delay event source selection is tile.

◆ XRFDC_CURRENT_STATE_OFFSET

#define XRFDC_CURRENT_STATE_OFFSET   0x0CU

#include <xrfdc_hw.h>

Current state register.

◆ XRFDC_DAC_CRSE_DLY_CFG_OFFSET

#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET   0x0DCU

#include <xrfdc_hw.h>

DAC Coarse delay Config Register.

◆ XRFDC_DAC_CRSE_DLY_UPDT_OFFSET

#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET   0x0E0U

#include <xrfdc_hw.h>

DAC Coarse Delay Update Register.

◆ XRFDC_DAC_DAT_ISR_INVSINC_MASK

#define XRFDC_DAC_DAT_ISR_INVSINC_MASK   0x00000100U

#include <xrfdc_hw.h>

Inverse Sinc offset overflow.

◆ XRFDC_DAC_DAT_PATH_ISR_MASK

#define XRFDC_DAC_DAT_PATH_ISR_MASK   0x000001FFU

#include <xrfdc_hw.h>

DAC Data Path Overflow.

◆ XRFDC_DAC_DECODER_CTRL_OFFSET

#define XRFDC_DAC_DECODER_CTRL_OFFSET   0x180U

#include <xrfdc_hw.h>

DAC Unary Decoder/ Randomizer settings.

◆ XRFDC_DAC_FAB_RATE_WR_MASK

#define XRFDC_DAC_FAB_RATE_WR_MASK   0x0000001FU

#include <xrfdc_hw.h>

DAC FIFO Write Number of Words per clock.

◆ XRFDC_DAC_FABRIC_IMR_OFFSET

#define XRFDC_DAC_FABRIC_IMR_OFFSET   0x018U

#include <xrfdc_hw.h>

DAC Fabric IMR Register.

◆ XRFDC_DAC_FABRIC_ISR_OFFSET

#define XRFDC_DAC_FABRIC_ISR_OFFSET   0x014U

#include <xrfdc_hw.h>

DAC Fabric ISR Register.

◆ XRFDC_DAC_INTERP_CTRL_OFFSET

#define XRFDC_DAC_INTERP_CTRL_OFFSET   0x040U

#include <xrfdc_hw.h>

DAC Interpolation Control Register.

◆ XRFDC_DAC_MC_CFG0_OFFSET

#define XRFDC_DAC_MC_CFG0_OFFSET   0x1C4U

#include <xrfdc_hw.h>

Static Configuration data for DAC Analog.

◆ XRFDC_DAC_MC_CFG3_OFFSET

#define XRFDC_DAC_MC_CFG3_OFFSET   0x1D0U

#include <xrfdc_hw.h>

DAC Static configuration bits for DAC analog Register.

◆ XRFDC_DAC_UPDATE_DYN_OFFSET

#define XRFDC_DAC_UPDATE_DYN_OFFSET   0x020U

#include <xrfdc_hw.h>

DAC Update Dynamic Register.

◆ XRFDC_DAC_UPDT_CRSE_DLY_MASK

#define XRFDC_DAC_UPDT_CRSE_DLY_MASK   0x00000020U

#include <xrfdc_hw.h>

DAC Trigger a update event apply to Coarse delay_DCONFIG reg.

◆ XRFDC_DAT_CLK_EN_MASK

#define XRFDC_DAT_CLK_EN_MASK   0x0000000FU

#include <xrfdc_hw.h>

Data Path Clk enable.

◆ XRFDC_DAT_IMR_DECI_IPATH_MASK

#define XRFDC_DAT_IMR_DECI_IPATH_MASK   0x00000007U

#include <xrfdc_hw.h>

Decimation I-Path overflow for stages 0,1,2.

◆ XRFDC_DAT_IMR_INTR_QPATH_MASK

#define XRFDC_DAT_IMR_INTR_QPATH_MASK   0x00000038U

#include <xrfdc_hw.h>

Interpolation Q-Path overflow for stages 0,1,2.

◆ XRFDC_DAT_IMR_QMC_GAIN_MASK

#define XRFDC_DAT_IMR_QMC_GAIN_MASK   0x00000040U

#include <xrfdc_hw.h>

QMC Gain/Phase overflow.

◆ XRFDC_DAT_IMR_QMC_OFFST_MASK

#define XRFDC_DAT_IMR_QMC_OFFST_MASK   0x00000080U

#include <xrfdc_hw.h>

QMC offset overflow.

◆ XRFDC_DAT_ISR_DECI_IPATH_MASK

#define XRFDC_DAT_ISR_DECI_IPATH_MASK   0x00000007U

#include <xrfdc_hw.h>

Decimation I-Path overflow for stages 0,1,2.

◆ XRFDC_DAT_ISR_INTR_QPATH_MASK

#define XRFDC_DAT_ISR_INTR_QPATH_MASK   0x00000038U

#include <xrfdc_hw.h>

Interpolation Q-Path overflow for stages 0,1,2.

◆ XRFDC_DAT_ISR_QMC_GAIN_MASK

#define XRFDC_DAT_ISR_QMC_GAIN_MASK   0x00000040U

#include <xrfdc_hw.h>

QMC Gain/Phase overflow.

◆ XRFDC_DAT_ISR_QMC_OFFST_MASK

#define XRFDC_DAT_ISR_QMC_OFFST_MASK   0x00000080U

#include <xrfdc_hw.h>

QMC offset overflow.

◆ XRFDC_DAT_SCALE_CFG_MASK [1/2]

#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U

#include <xrfdc_hw.h>

Enable data scaling.

◆ XRFDC_DAT_SCALE_CFG_MASK [2/2]

#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U

#include <xrfdc_hw.h>

Enable data scaling.

◆ XRFDC_DATPATH_IMR_OFFSET

#define XRFDC_DATPATH_IMR_OFFSET   0x03CU

#include <xrfdc_hw.h>

ADC Data Path IMR Register.

◆ XRFDC_DATPATH_ISR_OFFSET

#define XRFDC_DATPATH_ISR_OFFSET   0x038U

#include <xrfdc_hw.h>

ADC Data Path ISR Register.

◆ XRFDC_DBG_RST_CAL_MASK

#define XRFDC_DBG_RST_CAL_MASK   0x00000001U

#include <xrfdc_hw.h>

Reset clk_cal clock domain.

◆ XRFDC_DBG_RST_DIG_MASK

#define XRFDC_DBG_RST_DIG_MASK   0x00000008U

#include <xrfdc_hw.h>

Reset clk_dig clock domain.

◆ XRFDC_DBG_RST_DP_MASK

#define XRFDC_DBG_RST_DP_MASK   0x00000002U

#include <xrfdc_hw.h>

Reset data path clock domain.

◆ XRFDC_DBG_RST_DRP_CAL_MASK

#define XRFDC_DBG_RST_DRP_CAL_MASK   0x00000010U

#include <xrfdc_hw.h>

Reset subadc-drp register on clock cal.

◆ XRFDC_DBG_RST_FAB_MASK

#define XRFDC_DBG_RST_FAB_MASK   0x00000004U

#include <xrfdc_hw.h>

Reset clock fabric clock domain.

◆ XRFDC_DBG_RST_LM_MASK

#define XRFDC_DBG_RST_LM_MASK   0x00000020U

#include <xrfdc_hw.h>

Reset FIFO Latency measurement clock domain.

◆ XRFDC_DEC_CFG_4GSPS_MASK

#define XRFDC_DEC_CFG_4GSPS_MASK   0x00000003U

#include <xrfdc_hw.h>

4GSPS may be I or Q or Real depending on high level block config

◆ XRFDC_DEC_CFG_CHB_MASK

#define XRFDC_DEC_CFG_CHB_MASK   0x00000001U

#include <xrfdc_hw.h>

ChannelB (2GSPS real data from Mixer Q output)

◆ XRFDC_DEC_CFG_IQ_MASK

#define XRFDC_DEC_CFG_IQ_MASK   0x00000002U

#include <xrfdc_hw.h>

IQ-2GSPS.

◆ XRFDC_DEC_CFG_MASK

#define XRFDC_DEC_CFG_MASK   0x00000003U

#include <xrfdc_hw.h>

ChannelA (2GSPS real data from Mixer I output)

◆ XRFDC_DEC_CTRL_MODE_MASK

#define XRFDC_DEC_CTRL_MODE_MASK   0x00000007U

#include <xrfdc_hw.h>

Decoder mode.

◆ XRFDC_DEC_IMR_SUBADC0_OVR_MASK

#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK   0x00000002U

#include <xrfdc_hw.h>

subadc0 decoder overflow range

◆ XRFDC_DEC_IMR_SUBADC0_UND_MASK

#define XRFDC_DEC_IMR_SUBADC0_UND_MASK   0x00000001U

#include <xrfdc_hw.h>

subadc0 decoder underflow range

◆ XRFDC_DEC_IMR_SUBADC1_OVR_MASK

#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK   0x00000008U

#include <xrfdc_hw.h>

subadc1 decoder overflow range

◆ XRFDC_DEC_IMR_SUBADC1_UND_MASK

#define XRFDC_DEC_IMR_SUBADC1_UND_MASK   0x00000004U

#include <xrfdc_hw.h>

subadc1 decoder underflow range

◆ XRFDC_DEC_IMR_SUBADC2_OVR_MASK

#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK   0x00000020U

#include <xrfdc_hw.h>

subadc2 decoder overflow range

◆ XRFDC_DEC_IMR_SUBADC2_UND_MASK

#define XRFDC_DEC_IMR_SUBADC2_UND_MASK   0x00000010U

#include <xrfdc_hw.h>

subadc2 decoder underflow range

◆ XRFDC_DEC_IMR_SUBADC3_OVR_MASK

#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK   0x00000080U

#include <xrfdc_hw.h>

subadc3 decoder overflow range

◆ XRFDC_DEC_IMR_SUBADC3_UND_MASK

#define XRFDC_DEC_IMR_SUBADC3_UND_MASK   0x00000040U

#include <xrfdc_hw.h>

subadc3 decoder underflow range

◆ XRFDC_DEC_ISR_SUBADC0_OVR_MASK

#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK   0x00000002U

#include <xrfdc_hw.h>

subadc0 decoder overflow range

◆ XRFDC_DEC_ISR_SUBADC0_UND_MASK

#define XRFDC_DEC_ISR_SUBADC0_UND_MASK   0x00000001U

#include <xrfdc_hw.h>

subadc0 decoder underflow range

◆ XRFDC_DEC_ISR_SUBADC1_OVR_MASK

#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK   0x00000008U

#include <xrfdc_hw.h>

subadc1 decoder overflow range

◆ XRFDC_DEC_ISR_SUBADC1_UND_MASK

#define XRFDC_DEC_ISR_SUBADC1_UND_MASK   0x00000004U

#include <xrfdc_hw.h>

subadc1 decoder underflow range

◆ XRFDC_DEC_ISR_SUBADC2_OVR_MASK

#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK   0x00000020U

#include <xrfdc_hw.h>

subadc2 decoder overflow range

◆ XRFDC_DEC_ISR_SUBADC2_UND_MASK

#define XRFDC_DEC_ISR_SUBADC2_UND_MASK   0x00000010U

#include <xrfdc_hw.h>

subadc2 decoder underflow range

◆ XRFDC_DEC_ISR_SUBADC3_OVR_MASK

#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK   0x00000080U

#include <xrfdc_hw.h>

subadc3 decoder overflow range

◆ XRFDC_DEC_ISR_SUBADC3_UND_MASK

#define XRFDC_DEC_ISR_SUBADC3_UND_MASK   0x00000040U

#include <xrfdc_hw.h>

subadc3 decoder underflow range

◆ XRFDC_DEC_ISR_SUBADC_MASK

#define XRFDC_DEC_ISR_SUBADC_MASK   0x000000FFU

#include <xrfdc_hw.h>

subadc decoder Mask

◆ XRFDC_DEC_MOD_1X_MASK

#define XRFDC_DEC_MOD_1X_MASK   0x00000001U

#include <xrfdc_hw.h>

1x (decimation bypass)

◆ XRFDC_DEC_MOD_2X_BW_MASK

#define XRFDC_DEC_MOD_2X_BW_MASK   0x00000005U

#include <xrfdc_hw.h>

2x (med BW)

◆ XRFDC_DEC_MOD_2X_MASK

#define XRFDC_DEC_MOD_2X_MASK   0x00000002U

#include <xrfdc_hw.h>

2x (decimation bypass)

◆ XRFDC_DEC_MOD_4X_BW_MASK

#define XRFDC_DEC_MOD_4X_BW_MASK   0x00000006U

#include <xrfdc_hw.h>

4x (med BW)

◆ XRFDC_DEC_MOD_4X_MASK

#define XRFDC_DEC_MOD_4X_MASK   0x00000003U

#include <xrfdc_hw.h>

4x (decimation bypass)

◆ XRFDC_DEC_MOD_8X_BW_MASK

#define XRFDC_DEC_MOD_8X_BW_MASK   0x00000007U

#include <xrfdc_hw.h>

8x (med BW)

◆ XRFDC_DEC_MOD_8X_MASK

#define XRFDC_DEC_MOD_8X_MASK   0x00000004U

#include <xrfdc_hw.h>

8x (decimation bypass)

◆ XRFDC_DEC_MOD_MASK

#define XRFDC_DEC_MOD_MASK   0x00000007U

#include <xrfdc_hw.h>

Decimation mode Mask.

◆ XRFDC_EN_I_IQ_MASK

#define XRFDC_EN_I_IQ_MASK   0x00000003U

#include <xrfdc_hw.h>

Enable fine mixer multipliers on IQ i/p for I output.

◆ XRFDC_EN_INTR_ADC_TILE0_MASK

#define XRFDC_EN_INTR_ADC_TILE0_MASK   0x00000010U

#include <xrfdc_hw.h>

ADC Tile0 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_ADC_TILE1_MASK

#define XRFDC_EN_INTR_ADC_TILE1_MASK   0x00000020U

#include <xrfdc_hw.h>

ADC Tile1 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_ADC_TILE2_MASK

#define XRFDC_EN_INTR_ADC_TILE2_MASK   0x00000040U

#include <xrfdc_hw.h>

ADC Tile2 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_ADC_TILE3_MASK

#define XRFDC_EN_INTR_ADC_TILE3_MASK   0x00000080U

#include <xrfdc_hw.h>

ADC Tile3 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_DAC_TILE0_MASK

#define XRFDC_EN_INTR_DAC_TILE0_MASK   0x00000001U

#include <xrfdc_hw.h>

DAC Tile0 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_DAC_TILE1_MASK

#define XRFDC_EN_INTR_DAC_TILE1_MASK   0x00000002U

#include <xrfdc_hw.h>

DAC Tile1 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_DAC_TILE2_MASK

#define XRFDC_EN_INTR_DAC_TILE2_MASK   0x00000004U

#include <xrfdc_hw.h>

DAC Tile2 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_DAC_TILE3_MASK

#define XRFDC_EN_INTR_DAC_TILE3_MASK   0x00000008U

#include <xrfdc_hw.h>

DAC Tile3 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

◆ XRFDC_EN_INTR_SLICE0_MASK

#define XRFDC_EN_INTR_SLICE0_MASK   0x00000001U

#include <xrfdc_hw.h>

slice0 interrupt enable mask

◆ XRFDC_EN_INTR_SLICE1_MASK

#define XRFDC_EN_INTR_SLICE1_MASK   0x00000002U

#include <xrfdc_hw.h>

slice1 interrupt enable mask

◆ XRFDC_EN_INTR_SLICE2_MASK

#define XRFDC_EN_INTR_SLICE2_MASK   0x00000004U

#include <xrfdc_hw.h>

slice2 interrupt enable mask

◆ XRFDC_EN_INTR_SLICE3_MASK

#define XRFDC_EN_INTR_SLICE3_MASK   0x00000008U

#include <xrfdc_hw.h>

slice3 interrupt enable mask

◆ XRFDC_EN_Q_IQ_MASK

#define XRFDC_EN_Q_IQ_MASK   0x0000000CU

#include <xrfdc_hw.h>

Enable fine mixer multipliers on IQ i/p for Q output.

◆ XRFDC_FAB_IMR_MARGIND_OVR_MASK

#define XRFDC_FAB_IMR_MARGIND_OVR_MASK   0x00000004U

#include <xrfdc_hw.h>

Marginal-indicator overlap (overflow)

◆ XRFDC_FAB_IMR_MARGIND_UND_MASK

#define XRFDC_FAB_IMR_MARGIND_UND_MASK   0x00000008U

#include <xrfdc_hw.h>

Marginal-indicator overlap (underflow)

◆ XRFDC_FAB_IMR_USRDAT_MASK

#define XRFDC_FAB_IMR_USRDAT_MASK   0x00000003U

#include <xrfdc_hw.h>

User-data overlap Mask.

◆ XRFDC_FAB_IMR_USRDAT_OVR_MASK

#define XRFDC_FAB_IMR_USRDAT_OVR_MASK   0x00000001U

#include <xrfdc_hw.h>

User-data overlap- data written faster than read (overflow)

◆ XRFDC_FAB_IMR_USRDAT_UND_MASK

#define XRFDC_FAB_IMR_USRDAT_UND_MASK   0x00000002U

#include <xrfdc_hw.h>

User-data overlap- data read faster than written (underflow)

◆ XRFDC_FAB_ISR_MARGIND_OVR_MASK

#define XRFDC_FAB_ISR_MARGIND_OVR_MASK   0x00000004U

#include <xrfdc_hw.h>

Marginal-indicator overlap (overflow)

◆ XRFDC_FAB_ISR_MARGIND_UND_MASK

#define XRFDC_FAB_ISR_MARGIND_UND_MASK   0x00000008U

#include <xrfdc_hw.h>

Marginal-indicator overlap (underflow)

◆ XRFDC_FAB_ISR_USRDAT_MASK

#define XRFDC_FAB_ISR_USRDAT_MASK   0x00000003U

#include <xrfdc_hw.h>

User-data overlap Mask.

◆ XRFDC_FAB_ISR_USRDAT_OVR_MASK

#define XRFDC_FAB_ISR_USRDAT_OVR_MASK   0x00000001U

#include <xrfdc_hw.h>

User-data overlap- data written faster than read (overflow)

◆ XRFDC_FAB_ISR_USRDAT_UND_MASK

#define XRFDC_FAB_ISR_USRDAT_UND_MASK   0x00000002U

#include <xrfdc_hw.h>

User-data overlap- data read faster than written (underflow)

◆ XRFDC_FAB_RATE_RD_MASK

#define XRFDC_FAB_RATE_RD_MASK   0x00000F00U

#include <xrfdc_hw.h>

FIFO Read Number of words per clock.

◆ XRFDC_FAB_RD_PTR_OFFST_MASK

#define XRFDC_FAB_RD_PTR_OFFST_MASK   0x0000003FU

#include <xrfdc_hw.h>

FIFO read pointer offset for interface de-skew.

◆ XRFDC_FEND_DAT_CTRL_MASK

#define XRFDC_FEND_DAT_CTRL_MASK   0x000000FFU

#include <xrfdc_hw.h>

raw data and cal coefficient to be streamed to memory

◆ XRFDC_FIFO_EN_MASK

#define XRFDC_FIFO_EN_MASK   0x00000001U

#include <xrfdc_hw.h>

FIFO enable/disable.

◆ XRFDC_FIFO_ENABLE

#define XRFDC_FIFO_ENABLE   0x230U

#include <xrfdc_hw.h>

FIFO Enable and Disable.

◆ XRFDC_FIFO_LTNCY_DIS_MASK

#define XRFDC_FIFO_LTNCY_DIS_MASK   0x000000010U

#include <xrfdc_hw.h>

Disable FIFO Latency measurement.

◆ XRFDC_FIFO_LTNCY_DONE_MASK

#define XRFDC_FIFO_LTNCY_DONE_MASK   0x00008000U

#include <xrfdc_hw.h>

Latency measurement done flag.

◆ XRFDC_FIFO_LTNCY_KEY_MASK

#define XRFDC_FIFO_LTNCY_KEY_MASK   0x00004000U

#include <xrfdc_hw.h>

Latency measurement result identification key.

◆ XRFDC_FIFO_LTNCY_PRD_MASK

#define XRFDC_FIFO_LTNCY_PRD_MASK   0x00000007U

#include <xrfdc_hw.h>

Set FIFO Latency measurement period.

◆ XRFDC_FIFO_LTNCY_RES_MASK

#define XRFDC_FIFO_LTNCY_RES_MASK   0x00000FFFU

#include <xrfdc_hw.h>

Latency measurement result.

◆ XRFDC_FIFO_LTNCY_RESTRT_MASK

#define XRFDC_FIFO_LTNCY_RESTRT_MASK   0x00000008U

#include <xrfdc_hw.h>

Restart FIFO Latency measurement.

◆ XRFDC_FINE_MIX_SCALE_MASK

#define XRFDC_FINE_MIX_SCALE_MASK   0x00000010U

#include <xrfdc_hw.h>

NCO output scale.

◆ XRFDC_HSCOM_PWR_OFFSET

#define XRFDC_HSCOM_PWR_OFFSET   0x094

#include <xrfdc_hw.h>

Control register during power-up sequence.

◆ XRFDC_HSCOM_PWR_STATE_MASK

#define XRFDC_HSCOM_PWR_STATE_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

powerup state mask

◆ XRFDC_HSCOM_UPDT_DYN_OFFSET

#define XRFDC_HSCOM_UPDT_DYN_OFFSET   0x0B8

#include <xrfdc_hw.h>

Trigger the update dynamic event.

◆ XRFDC_I_IQ_COS_MINSIN

#define XRFDC_I_IQ_COS_MINSIN   0x00000C00U

#include <xrfdc_hw.h>

Select NCO phases for I output.

◆ XRFDC_INTERP_MODE_MASK

#define XRFDC_INTERP_MODE_MASK   0x00000007U

#include <xrfdc_hw.h>

Interpolation filter mode mask.

◆ XRFDC_INTR_ENABLE

#define XRFDC_INTR_ENABLE   0x204U

#include <xrfdc_hw.h>

Intr enable register.

◆ XRFDC_INTR_OVR_RANGE_MASK

#define XRFDC_INTR_OVR_RANGE_MASK   0x00000008U

#include <xrfdc_hw.h>

Over Range interrupt mask.

◆ XRFDC_INTR_OVR_VOLTAGE_MASK

#define XRFDC_INTR_OVR_VOLTAGE_MASK   0x00000004U

#include <xrfdc_hw.h>

Over Voltage interrupt mask.

◆ XRFDC_INTR_STS

#define XRFDC_INTR_STS   0x200U

#include <xrfdc_hw.h>

Intr status register.

◆ XRFDC_MC_CFG0_MIX_MODE_MASK

#define XRFDC_MC_CFG0_MIX_MODE_MASK   0x00000002U

#include <xrfdc_hw.h>

Enable Mixing mode.

◆ XRFDC_MIX_CFG0_MASK

#define XRFDC_MIX_CFG0_MASK   0x00000FFFU

#include <xrfdc_hw.h>

Mixer Config0 Mask.

◆ XRFDC_MIX_CFG1_MASK

#define XRFDC_MIX_CFG1_MASK   0x00000FFFU

#include <xrfdc_hw.h>

Mixer Config0 Mask.

◆ XRFDC_MIX_I_DAT_WRD0_MASK

#define XRFDC_MIX_I_DAT_WRD0_MASK   0x00000007U

#include <xrfdc_hw.h>

Output data word[0] of I channel.

◆ XRFDC_MIX_I_DAT_WRD1_MASK

#define XRFDC_MIX_I_DAT_WRD1_MASK   0x00000038U

#include <xrfdc_hw.h>

Output data word[1] of I channel.

◆ XRFDC_MIX_I_DAT_WRD2_MASK

#define XRFDC_MIX_I_DAT_WRD2_MASK   0x000001C0U

#include <xrfdc_hw.h>

Output data word[2] of I channel.

◆ XRFDC_MIX_I_DAT_WRD3_MASK

#define XRFDC_MIX_I_DAT_WRD3_MASK   0x00000E00U

#include <xrfdc_hw.h>

Output data word[3] of I channel.

◆ XRFDC_MIX_Q_DAT_WRD0_MASK

#define XRFDC_MIX_Q_DAT_WRD0_MASK   0x00000007U

#include <xrfdc_hw.h>

Output data word[0] of Q channel.

◆ XRFDC_MIX_Q_DAT_WRD1_MASK

#define XRFDC_MIX_Q_DAT_WRD1_MASK   0x00000038U

#include <xrfdc_hw.h>

Output data word[1] of Q channel.

◆ XRFDC_MIX_Q_DAT_WRD2_MASK

#define XRFDC_MIX_Q_DAT_WRD2_MASK   0x000001C0U

#include <xrfdc_hw.h>

Output data word[2] of Q channel.

◆ XRFDC_MIX_Q_DAT_WRD3_MASK

#define XRFDC_MIX_Q_DAT_WRD3_MASK   0x00000E00U

#include <xrfdc_hw.h>

Output data word[3] of Q channel.

◆ XRFDC_MXR_MODE_OFFSET

#define XRFDC_MXR_MODE_OFFSET   0x088U

#include <xrfdc_hw.h>

ADC/DAC mixer mode Register.

◆ XRFDC_NCO_FQWD_LOW_MASK

#define XRFDC_NCO_FQWD_LOW_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

NCO Phase increment[15:0].

◆ XRFDC_NCO_FQWD_MASK

#define XRFDC_NCO_FQWD_MASK   0x0000FFFFFFFFFFFFU

#include <xrfdc_hw.h>

NCO Freq offset[48:0].

◆ XRFDC_NCO_FQWD_MID_MASK

#define XRFDC_NCO_FQWD_MID_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

NCO Phase increment[31:16].

◆ XRFDC_NCO_FQWD_UPP_MASK

#define XRFDC_NCO_FQWD_UPP_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

NCO Phase increment[47:32].

◆ XRFDC_NCO_PHASE_LOW_MASK

#define XRFDC_NCO_PHASE_LOW_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

NCO Phase offset[15:0].

◆ XRFDC_NCO_PHASE_LOW_OFFSET

#define XRFDC_NCO_PHASE_LOW_OFFSET   0x0A4U

#include <xrfdc_hw.h>

ADC/DAC NCO Phase[15:0] Register.

◆ XRFDC_NCO_PHASE_MASK

#define XRFDC_NCO_PHASE_MASK   0x0003FFFFU

#include <xrfdc_hw.h>

NCO Phase offset[17:0].

◆ XRFDC_NCO_PHASE_MOD_4PHASE

#define XRFDC_NCO_PHASE_MOD_4PHASE   0x00000003U

#include <xrfdc_hw.h>

NCO output 4 successive phase.

◆ XRFDC_NCO_PHASE_MOD_EVEN

#define XRFDC_NCO_PHASE_MOD_EVEN   0x00000001U

#include <xrfdc_hw.h>

NCO output even phase.

◆ XRFDC_NCO_PHASE_MOD_MASK

#define XRFDC_NCO_PHASE_MOD_MASK   0x00000003U

#include <xrfdc_hw.h>

NCO mode of operation mask.

◆ XRFDC_NCO_PHASE_MODE_ODD

#define XRFDC_NCO_PHASE_MODE_ODD   0x00000002U

#include <xrfdc_hw.h>

NCO output odd phase.

◆ XRFDC_NCO_PHASE_RST_MASK

#define XRFDC_NCO_PHASE_RST_MASK   0x00000001U

#include <xrfdc_hw.h>

Reset NCO Phase of current slice.

◆ XRFDC_NCO_PHASE_UPP_MASK

#define XRFDC_NCO_PHASE_UPP_MASK   0x00000003U

#include <xrfdc_hw.h>

NCO Phase offset[17:16].

◆ XRFDC_NCO_PHASE_UPP_OFFSET

#define XRFDC_NCO_PHASE_UPP_OFFSET   0x0A0U

#include <xrfdc_hw.h>

ADC/DAC NCO Phase[17:16] Register.

◆ XRFDC_NCO_RST_OFFSET

#define XRFDC_NCO_RST_OFFSET   0x090U

#include <xrfdc_hw.h>

ADC/DAC NCO Phase Reset Register.

◆ XRFDC_NCO_UPDT_DLY_MASK

#define XRFDC_NCO_UPDT_DLY_MASK   0x00001FF8U

#include <xrfdc_hw.h>

delay in clk_dp cycles in application of event after arrival

◆ XRFDC_NCO_UPDT_MODE_FABRIC

#define XRFDC_NCO_UPDT_MODE_FABRIC   0x00000005U

#include <xrfdc_hw.h>

NCO event source selection is fabric.

◆ XRFDC_NCO_UPDT_MODE_GRP

#define XRFDC_NCO_UPDT_MODE_GRP   0x00000000U

#include <xrfdc_hw.h>

NCO event source selection is Group.

◆ XRFDC_NCO_UPDT_MODE_MARKER

#define XRFDC_NCO_UPDT_MODE_MARKER   0x00000004U

#include <xrfdc_hw.h>

NCO event source selection is Marker.

◆ XRFDC_NCO_UPDT_MODE_MASK

#define XRFDC_NCO_UPDT_MODE_MASK   0x00000007U

#include <xrfdc_hw.h>

NCO event source selection mask.

◆ XRFDC_NCO_UPDT_MODE_SLICE

#define XRFDC_NCO_UPDT_MODE_SLICE   0x00000001U

#include <xrfdc_hw.h>

NCO event source selection is slice.

◆ XRFDC_NCO_UPDT_MODE_SYSREF

#define XRFDC_NCO_UPDT_MODE_SYSREF   0x00000003U

#include <xrfdc_hw.h>

NCO event source selection is Sysref.

◆ XRFDC_NCO_UPDT_MODE_TILE

#define XRFDC_NCO_UPDT_MODE_TILE   0x00000002U

#include <xrfdc_hw.h>

NCO event source selection is tile.

◆ XRFDC_NCO_UPDT_OFFSET

#define XRFDC_NCO_UPDT_OFFSET   0x08CU

#include <xrfdc_hw.h>

ADC/DAC NCO Update mode Register.

◆ XRFDC_NCO_UPDT_RST_DLY_MASK

#define XRFDC_NCO_UPDT_RST_DLY_MASK   0x0000D000U

#include <xrfdc_hw.h>

optional delay on the NCO phase reset delay

◆ XRFDC_PLL_LOCKED_MASK

#define XRFDC_PLL_LOCKED_MASK   0x00000008U

#include <xrfdc_hw.h>

PLL Locked mask.

◆ XRFDC_PWR_STATE_MASK

#define XRFDC_PWR_STATE_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

State mask.

◆ XRFDC_PWR_UP_STAT_MASK

#define XRFDC_PWR_UP_STAT_MASK   0x00000004U

#include <xrfdc_hw.h>

Power Up state mask.

◆ XRFDC_Q_IQ_SIN_COS

#define XRFDC_Q_IQ_SIN_COS   0x00001000U

#include <xrfdc_hw.h>

Select NCO phases for Q output.

◆ XRFDC_QMC_CFG_EN_GAIN_MASK

#define XRFDC_QMC_CFG_EN_GAIN_MASK   0x00000001U

#include <xrfdc_hw.h>

enable QMC gain correction mask

◆ XRFDC_QMC_CFG_EN_PHASE_MASK

#define XRFDC_QMC_CFG_EN_PHASE_MASK   0x00000002U

#include <xrfdc_hw.h>

enable QMC Phase correction mask

◆ XRFDC_QMC_CFG_OFFSET

#define XRFDC_QMC_CFG_OFFSET   0x0CCU

#include <xrfdc_hw.h>

ADC/DAC QMC Config Register.

◆ XRFDC_QMC_GAIN_CRCTN_MASK

#define XRFDC_QMC_GAIN_CRCTN_MASK   0x00003FFFU

#include <xrfdc_hw.h>

QMC gain correction factor.

◆ XRFDC_QMC_GAIN_OFFSET

#define XRFDC_QMC_GAIN_OFFSET   0x0D4U

#include <xrfdc_hw.h>

ADC/DAC QMC Gain Correction Register.

◆ XRFDC_QMC_OFF_OFFSET

#define XRFDC_QMC_OFF_OFFSET   0x0D0U

#include <xrfdc_hw.h>

ADC/DAC QMC Offset Correction Register.

◆ XRFDC_QMC_OFFST_CRCTN_MASK

#define XRFDC_QMC_OFFST_CRCTN_MASK   0x00000FFFU

#include <xrfdc_hw.h>

QMC offset correction factor.

◆ XRFDC_QMC_PHASE_CRCTN_MASK

#define XRFDC_QMC_PHASE_CRCTN_MASK   0x00000FFFU

#include <xrfdc_hw.h>

QMC phase correction factor.

◆ XRFDC_QMC_PHASE_OFFSET

#define XRFDC_QMC_PHASE_OFFSET   0x0D8U

#include <xrfdc_hw.h>

ADC/DAC QMC Phase Correction Register.

◆ XRFDC_QMC_UPDT_DLY_MASK

#define XRFDC_QMC_UPDT_DLY_MASK   0x00001FF8U

#include <xrfdc_hw.h>

delay in clk_dp cycles in application of event after arrival

◆ XRFDC_QMC_UPDT_MODE_FABRIC

#define XRFDC_QMC_UPDT_MODE_FABRIC   0x00000005U

#include <xrfdc_hw.h>

QMC event source selection is fabric.

◆ XRFDC_QMC_UPDT_MODE_GRP

#define XRFDC_QMC_UPDT_MODE_GRP   0x00000000U

#include <xrfdc_hw.h>

QMC event source selection is group.

◆ XRFDC_QMC_UPDT_MODE_MARKER

#define XRFDC_QMC_UPDT_MODE_MARKER   0x00000004U

#include <xrfdc_hw.h>

QMC event source selection is Marker.

◆ XRFDC_QMC_UPDT_MODE_MASK

#define XRFDC_QMC_UPDT_MODE_MASK   0x00000007U

#include <xrfdc_hw.h>

QMC event source selection mask.

◆ XRFDC_QMC_UPDT_MODE_SLICE

#define XRFDC_QMC_UPDT_MODE_SLICE   0x00000001U

#include <xrfdc_hw.h>

QMC event source selection is slice.

◆ XRFDC_QMC_UPDT_MODE_SYSREF

#define XRFDC_QMC_UPDT_MODE_SYSREF   0x00000003U

#include <xrfdc_hw.h>

QMC event source selection is Sysref.

◆ XRFDC_QMC_UPDT_MODE_TILE

#define XRFDC_QMC_UPDT_MODE_TILE   0x00000002U

#include <xrfdc_hw.h>

QMC event source selection is tile.

◆ XRFDC_QMC_UPDT_OFFSET

#define XRFDC_QMC_UPDT_OFFSET   0x0C8U

#include <xrfdc_hw.h>

ADC/DAC QMC Update Mode Register.

◆ XRFdc_ReadReg

#define XRFdc_ReadReg (   InstancePtr,
  BaseAddress,
  RegOffset 
)    XRFdc_In32((InstancePtr->io), (BaseAddress + RegOffset))

#include <xrfdc_hw.h>

Read a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to the target register.
Returns
The value read from the register.
Note
C-Style signature: u32 XRFdc_ReadReg(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)

◆ XRFdc_ReadReg16

#define XRFdc_ReadReg16 (   InstancePtr,
  BaseAddress,
  RegOffset 
)    XRFdc_In16((InstancePtr->io), (RegOffset + BaseAddress))

#include <xrfdc_hw.h>

Read a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to the target register.
Returns
The value read from the register.
Note
C-Style signature: u16 XRFdc_ReadReg(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)

Referenced by XRFdc_IntrHandler().

◆ XRFdc_ReadReg64

#define XRFdc_ReadReg64 (   InstancePtr,
  BaseAddress,
  RegOffset 
)    XRFdc_In64(InstancePtr->io, (RegOffset + BaseAddress))

#include <xrfdc_hw.h>

Read a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to the target register.
Returns
The value read from the register.
Note
C-Style signature: u32 XRFdc_ReadReg(XRFdc *InstancePtr. u32 BaseAddress, s32 RegOffset)

◆ XRFdc_ReadReg8

#define XRFdc_ReadReg8 (   InstancePtr,
  BaseAddress,
  RegOffset 
)    XRFdc_In8((InstancePtr->io), (RegOffset + BaseAddress))

#include <xrfdc_hw.h>

Read a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to the target register.
Returns
The value read from the register.
Note
C-Style signature: u8 XRFdc_ReadReg(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)

◆ XRFDC_RESET_OFFSET

#define XRFDC_RESET_OFFSET   0x00U

#include <xrfdc_hw.h>

Tile reset register.

◆ XRFDC_RESTART_OFFSET

#define XRFDC_RESTART_OFFSET   0x04U

#include <xrfdc_hw.h>

Tile restart register.

◆ XRFDC_RESTART_STATE_OFFSET

#define XRFDC_RESTART_STATE_OFFSET   0x08U

#include <xrfdc_hw.h>

Tile restart state register.

◆ XRFDC_RX_MC_CFG0_MASK

#define XRFDC_RX_MC_CFG0_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX MC config0.

◆ XRFDC_RX_MC_CFG1_MASK

#define XRFDC_RX_MC_CFG1_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX MC Config1.

◆ XRFDC_RX_MC_CFG2_MASK

#define XRFDC_RX_MC_CFG2_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX MC Config2.

◆ XRFDC_RX_MC_PWRDWN_MASK

#define XRFDC_RX_MC_PWRDWN_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX MC power down.

◆ XRFDC_RX_PR_MC_CFG0_MASK

#define XRFDC_RX_PR_MC_CFG0_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX Pair MC Config0.

◆ XRFDC_RX_PR_MC_CFG1_MASK

#define XRFDC_RX_PR_MC_CFG1_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

RX Pair MC Config1.

◆ XRFDC_SEL_CB_TO_DECI_MASK

#define XRFDC_SEL_CB_TO_DECI_MASK   0x00000020U

#include <xrfdc_hw.h>

Control crossbar switch that select the data to decimation filter.

◆ XRFDC_SEL_CB_TO_MIX0_MASK

#define XRFDC_SEL_CB_TO_MIX0_MASK   0x0000000CU

#include <xrfdc_hw.h>

Control crossbar switch that select the data to mixer block mux0.

◆ XRFDC_SEL_CB_TO_MIX1_MASK

#define XRFDC_SEL_CB_TO_MIX1_MASK   0x00000003U

#include <xrfdc_hw.h>

Control crossbar switch that select the data to mixer block mux1.

◆ XRFDC_SEL_CB_TO_QMC_MASK

#define XRFDC_SEL_CB_TO_QMC_MASK   0x00000010U

#include <xrfdc_hw.h>

Control crossbar switch that select the data to QMC.

◆ XRFDC_SEL_I_IQ_MASK

#define XRFDC_SEL_I_IQ_MASK   0x00000F00U

#include <xrfdc_hw.h>

Select NCO phases for I output.

◆ XRFDC_SEL_Q_IQ_MASK

#define XRFDC_SEL_Q_IQ_MASK   0x0000F000U

#include <xrfdc_hw.h>

Select NCO phases for Q output.

◆ XRFDC_STATUS_OFFSET

#define XRFDC_STATUS_OFFSET   0x228U

#include <xrfdc_hw.h>

Common status register.

◆ XRFDC_SUBDRP_ADC0_ADDR_MASK

#define XRFDC_SUBDRP_ADC0_ADDR_MASK   0x000000FFU

#include <xrfdc_hw.h>

sub-drp0 address

◆ XRFDC_SUBDRP_ADC0_DAT_MASK

#define XRFDC_SUBDRP_ADC0_DAT_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

sub-drp0 data for read or write transaction

◆ XRFDC_SUBDRP_ADC1_ADDR_MASK

#define XRFDC_SUBDRP_ADC1_ADDR_MASK   0x000000FFU

#include <xrfdc_hw.h>

sub-drp1 address

◆ XRFDC_SUBDRP_ADC1_DAT_MASK

#define XRFDC_SUBDRP_ADC1_DAT_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

sub-drp1 data for read or write transaction

◆ XRFDC_SUBDRP_ADC2_ADDR_MASK

#define XRFDC_SUBDRP_ADC2_ADDR_MASK   0x000000FFU

#include <xrfdc_hw.h>

sub-drp2 address

◆ XRFDC_SUBDRP_ADC2_DAT_MASK

#define XRFDC_SUBDRP_ADC2_DAT_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

sub-drp2 data for read or write transaction

◆ XRFDC_SUBDRP_ADC3_ADDR_MASK

#define XRFDC_SUBDRP_ADC3_ADDR_MASK   0x000000FFU

#include <xrfdc_hw.h>

sub-drp3 address

◆ XRFDC_SUBDRP_ADC3_DAT_MASK

#define XRFDC_SUBDRP_ADC3_DAT_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

sub-drp3 data for read or write transaction

◆ XRFDC_TI_DCB_CTRL0_MASK

#define XRFDC_TI_DCB_CTRL0_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

TI DCB gain and offset correction.

◆ XRFDC_TI_DCB_CTRL1_MASK

#define XRFDC_TI_DCB_CTRL1_MASK   0x00001FFFU

#include <xrfdc_hw.h>

TI DCB gain and offset correction.

◆ XRFDC_TI_DCB_CTRL2_MASK

#define XRFDC_TI_DCB_CTRL2_MASK   0x00001FFFU

#include <xrfdc_hw.h>

TI DCB gain and offset correction.

◆ XRFDC_TI_DCB_STS0_BG_MASK

#define XRFDC_TI_DCB_STS0_BG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status0 BG.

◆ XRFDC_TI_DCB_STS0_FG_MASK

#define XRFDC_TI_DCB_STS0_FG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status0 FG.

◆ XRFDC_TI_DCB_STS1_BG_MASK

#define XRFDC_TI_DCB_STS1_BG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status1 BG.

◆ XRFDC_TI_DCB_STS1_FG_MASK

#define XRFDC_TI_DCB_STS1_FG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status1 FG.

◆ XRFDC_TI_DCB_STS2_BG_MASK

#define XRFDC_TI_DCB_STS2_BG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status2 BG.

◆ XRFDC_TI_DCB_STS2_FG_MASK

#define XRFDC_TI_DCB_STS2_FG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status2 FG.

◆ XRFDC_TI_DCB_STS3_BG_MASK

#define XRFDC_TI_DCB_STS3_BG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status3 BG.

◆ XRFDC_TI_DCB_STS3_FG_MASK

#define XRFDC_TI_DCB_STS3_FG_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

DCB Status3 FG.

◆ XRFDC_TI_DCB_STS4_LSB_MASK

#define XRFDC_TI_DCB_STS4_LSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc0 lsb bits(subadc chan0)

◆ XRFDC_TI_DCB_STS4_MSB_MASK

#define XRFDC_TI_DCB_STS4_MSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc0 msb bits(subadc chan0)

◆ XRFDC_TI_DCB_STS5_LSB_MASK

#define XRFDC_TI_DCB_STS5_LSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc1 lsb bits(subadc chan1)

◆ XRFDC_TI_DCB_STS5_MSB_MASK

#define XRFDC_TI_DCB_STS5_MSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc1 msb bits(subadc chan1)

◆ XRFDC_TI_DCB_STS6_LSB_MASK

#define XRFDC_TI_DCB_STS6_LSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc2 lsb bits(subadc chan2)

◆ XRFDC_TI_DCB_STS6_MSB_MASK

#define XRFDC_TI_DCB_STS6_MSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc2 msb bits(subadc chan2)

◆ XRFDC_TI_DCB_STS7_LSB_MASK

#define XRFDC_TI_DCB_STS7_LSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc3 lsb bits(subadc chan3)

◆ XRFDC_TI_DCB_STS7_MSB_MASK

#define XRFDC_TI_DCB_STS7_MSB_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

read the status of gcb acc3 msb bits(subadc chan3)

◆ XRFDC_TI_TISK_CHOP_EN_MASK

#define XRFDC_TI_TISK_CHOP_EN_MASK   0x00000008U

#include <xrfdc_hw.h>

enable chopping mode

◆ XRFDC_TI_TISK_DBG_CTRL_MASK

#define XRFDC_TI_TISK_DBG_CTRL_MASK   0x0000F000U

#include <xrfdc_hw.h>

Debug control.

◆ XRFDC_TI_TISK_DBG_UPDT_RT_MASK

#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK   0x00001000U

#include <xrfdc_hw.h>

Debug update rate.

◆ XRFDC_TI_TISK_DITH_DLY_MASK

#define XRFDC_TI_TISK_DITH_DLY_MASK   0x0000E000U

#include <xrfdc_hw.h>

Programmable delay on dither path to match data path.

◆ XRFDC_TI_TISK_EN_MASK

#define XRFDC_TI_TISK_EN_MASK   0x00000001U

#include <xrfdc_hw.h>

Block Enable.

◆ XRFDC_TI_TISK_MODE_MASK

#define XRFDC_TI_TISK_MODE_MASK   0x00000002U

#include <xrfdc_hw.h>

Mode (2G/4G)

◆ XRFDC_TI_TISK_MU_CM_MASK

#define XRFDC_TI_TISK_MU_CM_MASK   0x000000F0U

#include <xrfdc_hw.h>

Constant mu_cm multiplying common mode path.

◆ XRFDC_TI_TISK_MU_DF_MASK

#define XRFDC_TI_TISK_MU_DF_MASK   0x00000F00U

#include <xrfdc_hw.h>

Constant mu_df multiplying differential path.

◆ XRFDC_TI_TISK_ZONE_MASK

#define XRFDC_TI_TISK_ZONE_MASK   0x00000004U

#include <xrfdc_hw.h>

Specifies Nyquist zone.

◆ XRFDC_TILE_RESET_MASK

#define XRFDC_TILE_RESET_MASK   0x00000001U

#include <xrfdc_hw.h>

Tile reset mask.

◆ XRFDC_TISK_BYPASS0_MASK

#define XRFDC_TISK_BYPASS0_MASK   0x00000080U

#include <xrfdc_hw.h>

ByPass filter0.

◆ XRFDC_TISK_BYPASS1_MASK

#define XRFDC_TISK_BYPASS1_MASK   0x00008000U

#include <xrfdc_hw.h>

Filter1 multiplying factor.

◆ XRFDC_TISK_CHOP_EN_MASK

#define XRFDC_TISK_CHOP_EN_MASK   0x00000008U

#include <xrfdc_hw.h>

enable chopping mode

◆ XRFDC_TISK_DAC0_CODE_MASK

#define XRFDC_TISK_DAC0_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch0 front end switch0.

◆ XRFDC_TISK_DAC0_OVRID_EN_MASK

#define XRFDC_TISK_DAC0_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DAC1_CODE_MASK

#define XRFDC_TISK_DAC1_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch1 front end switch0.

◆ XRFDC_TISK_DAC1_OVRID_EN_MASK

#define XRFDC_TISK_DAC1_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DAC2_CODE_MASK

#define XRFDC_TISK_DAC2_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch2 front end switch0.

◆ XRFDC_TISK_DAC2_OVRID_EN_MASK

#define XRFDC_TISK_DAC2_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DAC3_CODE_MASK

#define XRFDC_TISK_DAC3_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch3 front end switch0.

◆ XRFDC_TISK_DAC3_OVRID_EN_MASK

#define XRFDC_TISK_DAC3_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DACP0_CODE_MASK

#define XRFDC_TISK_DACP0_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch0 front end switch1.

◆ XRFDC_TISK_DACP0_OVRID_EN_MASK

#define XRFDC_TISK_DACP0_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DACP1_CODE_MASK

#define XRFDC_TISK_DACP1_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch1 front end switch1.

◆ XRFDC_TISK_DACP1_OVRID_EN_MASK

#define XRFDC_TISK_DACP1_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DACP2_CODE_MASK

#define XRFDC_TISK_DACP2_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch2 front end switch1.

◆ XRFDC_TISK_DACP2_OVRID_EN_MASK

#define XRFDC_TISK_DACP2_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DACP3_CODE_MASK

#define XRFDC_TISK_DACP3_CODE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Code to correction DAC of subadc ch3 front end switch1.

◆ XRFDC_TISK_DACP3_OVRID_EN_MASK

#define XRFDC_TISK_DACP3_OVRID_EN_MASK   0x00008000U

#include <xrfdc_hw.h>

override enable

◆ XRFDC_TISK_DBG_CTRL_MASK

#define XRFDC_TISK_DBG_CTRL_MASK   0x0000F000U

#include <xrfdc_hw.h>

Debug control.

◆ XRFDC_TISK_DBG_UPDT_RT_MASK

#define XRFDC_TISK_DBG_UPDT_RT_MASK   0x00001000U

#include <xrfdc_hw.h>

Debug update rate.

◆ XRFDC_TISK_DITH_DLY_MASK

#define XRFDC_TISK_DITH_DLY_MASK   0x0000E000U

#include <xrfdc_hw.h>

Programmable delay on dither path to match data path.

◆ XRFDC_TISK_DZ_MAX_VAL_MASK

#define XRFDC_TISK_DZ_MAX_VAL_MASK   0x0000FF00U

#include <xrfdc_hw.h>

Deadzone max.

◆ XRFDC_TISK_DZ_MIN_VAL_MASK

#define XRFDC_TISK_DZ_MIN_VAL_MASK   0x000000FFU

#include <xrfdc_hw.h>

Deadzone min.

◆ XRFDC_TISK_EN_MASK

#define XRFDC_TISK_EN_MASK   0x00000001U

#include <xrfdc_hw.h>

Block Enable.

◆ XRFDC_TISK_MODE_MASK

#define XRFDC_TISK_MODE_MASK   0x00000002U

#include <xrfdc_hw.h>

Mode (2G/4G)

◆ XRFDC_TISK_MU0_MASK

#define XRFDC_TISK_MU0_MASK   0x0000000FU

#include <xrfdc_hw.h>

Filter0 multiplying factor.

◆ XRFDC_TISK_MU1_MASK

#define XRFDC_TISK_MU1_MASK   0x00000F00U

#include <xrfdc_hw.h>

Filter1 multiplying factor.

◆ XRFDC_TISK_MU_CM_MASK

#define XRFDC_TISK_MU_CM_MASK   0x000000F0U

#include <xrfdc_hw.h>

Constant mu_cm multiplying common mode path.

◆ XRFDC_TISK_MU_DF_MASK

#define XRFDC_TISK_MU_DF_MASK   0x00000F00U

#include <xrfdc_hw.h>

Constant mu_df multiplying differential path.

◆ XRFDC_TISK_SETTLE_MASK

#define XRFDC_TISK_SETTLE_MASK   0x000000FFU

#include <xrfdc_hw.h>

Settling time following code update.

◆ XRFDC_TISK_ZONE_MASK

#define XRFDC_TISK_ZONE_MASK   0x00000004U

#include <xrfdc_hw.h>

Specifies Nyquist zone.

◆ XRFDC_TRSHD0_AVG_LOW_MASK

#define XRFDC_TRSHD0_AVG_LOW_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

Threshold0 under Averaging[15:0].

◆ XRFDC_TRSHD0_AVG_UPP_MASK

#define XRFDC_TRSHD0_AVG_UPP_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

Threshold0 under Averaging[31:16].

◆ XRFDC_TRSHD0_CLR_MOD_MASK

#define XRFDC_TRSHD0_CLR_MOD_MASK   0x00000004U

#include <xrfdc_hw.h>

Clear mode.

◆ XRFDC_TRSHD0_EN_MOD_MASK

#define XRFDC_TRSHD0_EN_MOD_MASK   0x00000003U

#include <xrfdc_hw.h>

Enable Threshold0 block.

◆ XRFDC_TRSHD0_OVER_MASK

#define XRFDC_TRSHD0_OVER_MASK   0x00007FFFU

#include <xrfdc_hw.h>

Threshold0 under Threshold[14:0].

◆ XRFDC_TRSHD0_STIKY_CLR_MASK

#define XRFDC_TRSHD0_STIKY_CLR_MASK   0x00000008U

#include <xrfdc_hw.h>

Clear sticky bit.

◆ XRFDC_TRSHD0_UNDER_MASK

#define XRFDC_TRSHD0_UNDER_MASK   0x00007FFFU

#include <xrfdc_hw.h>

Threshold0 under Threshold[14:0].

◆ XRFDC_TRSHD1_AVG_LOW_MASK

#define XRFDC_TRSHD1_AVG_LOW_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

Threshold1 under Averaging[15:0].

◆ XRFDC_TRSHD1_AVG_UPP_MASK

#define XRFDC_TRSHD1_AVG_UPP_MASK   0x0000FFFFU

#include <xrfdc_hw.h>

Threshold1 under Averaging[31:16].

◆ XRFDC_TRSHD1_CLR_MOD_MASK

#define XRFDC_TRSHD1_CLR_MOD_MASK   0x00000004U

#include <xrfdc_hw.h>

Clear mode.

◆ XRFDC_TRSHD1_EN_MOD_MASK

#define XRFDC_TRSHD1_EN_MOD_MASK   0x00000003U

#include <xrfdc_hw.h>

Enable Threshold1 block.

◆ XRFDC_TRSHD1_OVER_MASK

#define XRFDC_TRSHD1_OVER_MASK   0x00007FFFU

#include <xrfdc_hw.h>

Threshold1 under Threshold[14:0].

◆ XRFDC_TRSHD1_STIKY_CLR_MASK

#define XRFDC_TRSHD1_STIKY_CLR_MASK   0x00000008U

#include <xrfdc_hw.h>

Clear sticky bit.

◆ XRFDC_TRSHD1_UNDER_MASK

#define XRFDC_TRSHD1_UNDER_MASK   0x00007FFFU

#include <xrfdc_hw.h>

Threshold1 under Threshold[14:0].

◆ XRFDC_UPDT_EVNT_MASK

#define XRFDC_UPDT_EVNT_MASK   0x0000000FU

#include <xrfdc_hw.h>

Update event mask.

◆ XRFDC_UPDT_EVNT_NCO_MASK

#define XRFDC_UPDT_EVNT_NCO_MASK   0x00000002U

#include <xrfdc_hw.h>

Trigger a update event apply to NCO_DCONFIG reg.

◆ XRFDC_UPDT_EVNT_QMC_MASK

#define XRFDC_UPDT_EVNT_QMC_MASK   0x00000004U

#include <xrfdc_hw.h>

Trigger a update event apply to QMC_DCONFIG reg.

◆ XRFDC_UPDT_EVNT_SLICE_MASK

#define XRFDC_UPDT_EVNT_SLICE_MASK   0x00000001U

#include <xrfdc_hw.h>

Trigger a slice update event apply to _DCONFIG reg.

◆ XRFdc_WriteReg

#define XRFdc_WriteReg (   InstancePtr,
  BaseAddress,
  RegOffset,
  RegisterValue 
)    XRFdc_Out32((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))

#include <xrfdc_hw.h>

Write to a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to target register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset, u32 RegisterValue)

◆ XRFdc_WriteReg16

#define XRFdc_WriteReg16 (   InstancePtr,
  BaseAddress,
  RegOffset,
  RegisterValue 
)    XRFdc_Out16((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))

#include <xrfdc_hw.h>

Write to a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to target register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset, u16 RegisterValue)

◆ XRFdc_WriteReg64

#define XRFdc_WriteReg64 (   InstancePtr,
  BaseAddress,
  RegOffset,
  RegisterValue 
)

#include <xrfdc_hw.h>

Value:
XRFdc_Out64((InstancePtr->io), (RegOffset + BaseAddress), \
(RegisterValue))

Write to a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to target register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, s32 RegOffset, u64 RegisterValue)

◆ XRFdc_WriteReg8

#define XRFdc_WriteReg8 (   InstancePtr,
  BaseAddress,
  RegOffset,
  RegisterValue 
)    XRFdc_Out8((InstancePtr->io), (RegOffset + BaseAddress), (RegisterValue))

#include <xrfdc_hw.h>

Write to a register.

Parameters
InstancePtris a pointer to the XRfdc instance.
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to target register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset, u8 RegisterValue)

Typedef Documentation

◆ XRFdc_StatusHandler

typedef void(* XRFdc_StatusHandler) (void *CallBackRef, u32 Type, int Tile_Id, u32 Block_Id, u32 StatusEvent)

#include <xrfdc.h>

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters
CallBackRefis the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
Typeindicates ADC/DAC.
Tile_Idindicates Tile number (0-3).
Block_Idindicates Block number (0-3).
StatusEventindicates one or more interrupt occurred.

Function Documentation

◆ XRFdc_CfgInitialize()

int XRFdc_CfgInitialize ( XRFdc InstancePtr,
XRFdc_Config Config 
)

#include <xrfdc.h>

Initializes a specific XRFdc instance such that the driver is ready to use.

Parameters
InstancePtris a pointer to the XRfdc instance.
Configis a reference to a structure containing information about xrfdc. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
Returns
  • XRFDC_SUCCESS if successful.
Note
The user needs to first call the XRFdc_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XRFdc_CfgInitialize() API.

◆ XRFdc_DumpRegs()

void XRFdc_DumpRegs ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id 
)

#include <xrfdc.h>

This Prints the offset of the register along with the content.

This API is meant to be used for debug purposes. It prints to the console the contents of registers for the passed Tile_Id. If -1 is passed, it prints the contents of the registers for all the tiles for the respective ADC or DAC

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Returns
None
Note
None

◆ XRFdc_GetBlockStatus()

int XRFdc_GetBlockStatus ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_BlockStatus BlockStatus 
)

#include <xrfdc.h>

The API returns the requested block status.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3. XRFdc_BlockStatus.
BlockStatusis Pointer to the XRFdc_BlockStatus structure through which the ADC/DAC block status is returned.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Common API for ADC/DAC blocks.

◆ XRFdc_GetCoarseDelaySettings()

int XRFdc_GetCoarseDelaySettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_CoarseDelay_Settings CoarseDelay_Settings 
)

#include <xrfdc.h>

Coarse delay settings are returned back to the caller.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
CoarseDelay_SettingsPointer to the XRFdc_CoarseDelay_Settings structure in which the Coarse Delay settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None.

◆ XRFdc_GetDecimationFactor()

int XRFdc_GetDecimationFactor ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32 *  DecimationFactor 
)

#include <xrfdc.h>

Decimation factor are returned back to the caller.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
DecimationFactorPointer to return the Decimation factor for DAC blocks.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for ADC blocks

◆ XRFdc_GetDecoderMode()

int XRFdc_GetDecoderMode ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32 *  DecoderMode 
)

#include <xrfdc.h>

Decoder mode is read and returned back.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis DAC block number inside the tile. Valid values are 0-3.
DecoderModeValid values are 1 (Maximum SNR, for non-randomized decoder), 2 (Maximum Linearity, for randomized decoder)
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for DAC blocks

◆ XRFdc_GetFabRdVldWords()

int XRFdc_GetFabRdVldWords ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32 *  FabricRdVldWords 
)

#include <xrfdc.h>

This API returns the the number of fabric read valid words requested for the block.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
FabricRdVldWordsPointer to return the fabric data rate for ADC/DAC block
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
ADC/DAC blocks

◆ XRFdc_GetFabWrVldWords()

int XRFdc_GetFabWrVldWords ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32 *  FabricWrVldWords 
)

#include <xrfdc.h>

This API returns the the number of fabric write valid words requested for the block.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
FabricWrVldWordsPointer to return the fabric data rate for DAC block
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
ADC/DAC blocks

◆ XRFdc_GetInterpolationFactor()

int XRFdc_GetInterpolationFactor ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32 *  InterpolationFactor 
)

#include <xrfdc.h>

Interpolation factor are returned back to the caller.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
InterpolationFactorPointer to return the interpolation factor for DAC blocks.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for DAC blocks

◆ XRFdc_GetIntrStatus()

u32 XRFdc_GetIntrStatus ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id 
)

#include <xrfdc.h>

This function returns the interrupt status read from Interrupt Status Register(ISR).

Parameters
InstancePtris a pointer to the XSysMonPsu instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Returns
A 32-bit value representing the contents of the Interrupt Status Registers (FIFO interface, Decoder interface, Data Path Interface)
Note
None.

◆ XRFdc_GetIPStatus()

int XRFdc_GetIPStatus ( XRFdc InstancePtr,
XRFdc_IPStatus IPStatus 
)

#include <xrfdc.h>

The API returns the IP status.

Parameters
InstancePtris a pointer to the XRfdc instance.
IPStatusPointer to the XRFdc_IPStatus structure through which the status is returned.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if IP not ready.
Note
None.

◆ XRFdc_GetMixerSettings()

int XRFdc_GetMixerSettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_Mixer_Settings Mixer_Settings 
)

#include <xrfdc.h>

The API returns back Mixer/NCO settings to the caller.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Mixer_SettingsPointer to the XRFdc_Mixer_Settings structure in which the Mixer/NCO settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_GetNyquistZone()

int XRFdc_GetNyquistZone ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32 *  NyquistZone 
)

#include <xrfdc.h>

Get the Nyquist zone.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
NyquistZonePointer to return the Nyquist zone.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Tile not enabled.
Note
Common API for ADC/DAC blocks

◆ XRFdc_GetOutputCurr()

int XRFdc_GetOutputCurr ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
int *  OutputCurr 
)

#include <xrfdc.h>

Get Output Current for DAC block.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
OutputCurrpointer to return the output current.
Returns
  • Return Output Current for DAC block

◆ XRFdc_GetQMCSettings()

int XRFdc_GetQMCSettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_QMC_Settings QMC_Settings 
)

#include <xrfdc.h>

QMC settings are returned back to the caller through this API.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
QMC_SettingsPointer to the XRFdc_QMC_Settings structure in which the QMC settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_GetSignalFlow()

void XRFdc_GetSignalFlow ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  AnalogDataPath,
u32 *  ConnectedIData,
u32 *  ConnectedQData 
)

#include <xrfdc.h>

Reads back the multiband configuration.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
AnalogDataPathfor which the multi band configuration is targeted
ConnectedIDatais Connected I data path to be readback
ConnectedQDatais Connected Q data path to be readback
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Common API for ADC/DAC blocks

◆ XRFdc_GetThresholdSettings()

int XRFdc_GetThresholdSettings ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
XRFdc_Threshold_Settings Threshold_Settings 
)

#include <xrfdc.h>

Threshold settings are read from the corresponding registers and are passed back to the caller.

There can be two threshold settings: threshold0 and threshold1. Both of them are independent of each other. The function returns the requested threshold (which can be threshold0, threshold1, or both.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Threshold_SettingsPointer through which the register settings for thresholds are passed back..
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for ADC blocks

◆ XRFdc_IntrClr()

void XRFdc_IntrClr ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32  IntrMask 
)

#include <xrfdc.h>

This function clear the interrupts.

Parameters
InstancePtris a pointer to the XSysMonPsu instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
IntrMaskcontains the interrupts to be cleared.
Returns
A 32-bit value representing the contents of the Interrupt Status Registers (FIFO interface, Decoder interface, Data Path Interface)
Note
None.

◆ XRFdc_IntrDisable()

void XRFdc_IntrDisable ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32  IntrMask 
)

#include <xrfdc.h>

This function clears the interrupt mask.

Parameters
InstancePtris a pointer to the XRFdc instance
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
IntrMaskcontains the interrupts to be disabled. '1' disables an interrupt, and '0' remains no change.
Returns
None.
Note
None.

◆ XRFdc_IntrEnable()

void XRFdc_IntrEnable ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32  IntrMask 
)

#include <xrfdc.h>

This function sets the interrupt mask.

Parameters
InstancePtris a pointer to the XRFdc instance
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
IntrMaskcontains the interrupts to be enabled. '1' enables an interrupt, and '0' disables.
Returns
None.
Note
None.

◆ XRFdc_IntrHandler()

int XRFdc_IntrHandler ( int  Vector,
void *  XRFdcPtr 
)

#include <xrfdc.h>

This function is the interrupt handler for the driver.

It must be connected to an interrupt system by the application such that it can be called when an interrupt occurs.

Parameters
Vectoris interrupt vector number. Libmetal status handler expects two parameters in the handler prototype, hence kept this parameter. This is not used inside the interrupt handler API.
XRFdcPtrcontains a pointer to the driver instance
Returns
None.
Note
Vector param is not useful inside the interrupt handler, hence typecast with void to remove compilation warning.

References XRFDC_COMMON_INTR_STS, XRFDC_EN_INTR_ADC_TILE0_MASK, XRFDC_EN_INTR_ADC_TILE1_MASK, XRFDC_EN_INTR_ADC_TILE2_MASK, XRFDC_EN_INTR_ADC_TILE3_MASK, XRFDC_EN_INTR_DAC_TILE0_MASK, XRFDC_EN_INTR_DAC_TILE1_MASK, XRFDC_EN_INTR_DAC_TILE2_MASK, XRFDC_EN_INTR_DAC_TILE3_MASK, and XRFdc_ReadReg16.

◆ XRFdc_LookupConfig()

XRFdc_Config * XRFdc_LookupConfig ( u16  DeviceId)

#include <xrfdc.h>

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters
DeviceIdcontains the ID of the device to look up the configuration for.
Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xrfdc.h for the definition of XRFdc_Config.

Note
None.

◆ XRFdc_Reset()

int XRFdc_Reset ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id 
)

#include <xrfdc.h>

The API resets the requested tile.

It can reset all the tiles as well. In the process, all existing register settings are cleared and are replaced with the settings initially configured (through the GUI).

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if tile is not enabled or available
Note
None

◆ XRFdc_ResetNCOPhase()

int XRFdc_ResetNCOPhase ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id 
)

#include <xrfdc.h>

Resets the NCO phase of the current block phase accumulator.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_SetCoarseDelaySettings()

int XRFdc_SetCoarseDelaySettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_CoarseDelay_Settings CoarseDelay_Settings 
)

#include <xrfdc.h>

Coarse delay settings passed are used to update the corresponding block level registers.

Driver structure is updated with the new values.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
CoarseDelay_Settingsis Pointer to the XRFdc_CoarseDelay_Settings structure in which the CoarseDelay settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_SetDecoderMode()

int XRFdc_SetDecoderMode ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32  DecoderMode 
)

#include <xrfdc.h>

Decoder mode is updated into the relevant registers.

Driver structure is updated with the new values.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis DAC block number inside the tile. Valid values are 0-3.
DecoderModeValid values are 1 (Maximum SNR, for non- randomized decoder), 2 (Maximum Linearity, for randomized decoder)
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only DAC blocks

◆ XRFdc_SetFabRdVldWords()

int XRFdc_SetFabRdVldWords ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32  FabricRdVldWords 
)

#include <xrfdc.h>

Fabric data rate for the requested ADC block is set by writing to the corresponding register.

The function writes the number of valid read words for the requested ADC block.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC block number inside the tile. Valid values are 0-3.
FabricRdVldWordsis Read fabric rate to be set for ADC block.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for ADC blocks

◆ XRFdc_SetFabWrVldWords()

int XRFdc_SetFabWrVldWords ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
u32  FabricWrVldWords 
)

#include <xrfdc.h>

Fabric data rate for the requested DAC block is set by writing to the corresponding register.

The function writes the number of valid write words for the requested DAC block.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
FabricWrVldWordsis write fabric rate to be set for DAC block.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only for DAC blocks

◆ XRFdc_SetMixerSettings()

int XRFdc_SetMixerSettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_Mixer_Settings Mixer_Settings 
)

#include <xrfdc.h>

The API is used to update various mixer settings, fine, coarse, NCO etc.

Mixer/NCO settings passed are used to update the corresponding block level registers. Driver structure is updated with the new values.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Mixer_SettingsPointer to the XRFdc_Mixer_Settings structure in which the Mixer/NCO settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_SetNyquistZone()

int XRFdc_SetNyquistZone ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32  NyquistZone 
)

#include <xrfdc.h>

Set the Nyquist zone.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
NyquistZonevalid values are 1 (Odd),2 (Even).
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Tile not enabled.
Note
Common API for ADC/DAC blocks

◆ XRFdc_SetQMCSettings()

int XRFdc_SetQMCSettings ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
XRFdc_QMC_Settings QMC_Settings 
)

#include <xrfdc.h>

This API is used to update various QMC settings, eg gain, phase, offset etc.

QMC settings passed are used to update the corresponding block level registers. Driver structure is updated with the new values.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
QMC_Settingsis Pointer to the XRFdc_QMC_Settings structure in which the QMC settings are passed.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
None

◆ XRFdc_SetSignalFlow()

void XRFdc_SetSignalFlow ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  AnalogDataPath,
u32  ConnectIData,
u32  ConnectQData 
)

#include <xrfdc.h>

Sets up multiband configuration.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
AnalogDataPathto be connected to the requested I or Q data
ConnectIDatais I data path to be connected to a requested analog data path
ConnectQDatais Q data path to be connected to a requested analog data path
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Common API for ADC/DAC blocks

◆ XRFdc_SetStatusHandler()

void XRFdc_SetStatusHandler ( XRFdc InstancePtr,
void *  CallBackRef,
XRFdc_StatusHandler  FunctionPtr 
)

#include <xrfdc.h>

This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.

The handler executes in an interrupt context, so the amount of processing should be minimized

Parameters
InstancePtris a pointer to the XRFdc instance.
CallBackRefis the upper layer callback reference passed back when the callback function is invoked.
FunctionPtris the pointer to the callback function.
Returns
None.
Note

The handler is called within interrupt context, so it should finish its work quickly.

◆ XRFdc_SetThresholdSettings()

int XRFdc_SetThresholdSettings ( XRFdc InstancePtr,
int  Tile_Id,
u32  Block_Id,
XRFdc_Threshold_Settings Threshold_Settings 
)

#include <xrfdc.h>

Threshold settings are updated into the relevant registers.

Driver structure is updated with the new values. There can be two threshold settings: threshold0 and threshold1. Both of them are independent of each other. The function returns the requested threshold (which can be threshold0, threshold1, or both.

Parameters
InstancePtris a pointer to the XRfdc instance.
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Threshold_SettingsPointer through which the register settings for thresholds are passed to the API.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Only ADC blocks

◆ XRFdc_SetupFIFO()

int XRFdc_SetupFIFO ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u8  Enable 
)

#include <xrfdc.h>

Enable and Disable the ADC/DAC FIFO.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Enablevalid values are 1 (FIFO enable) and 0 (FIFO Disable)
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Tile not enabled.
Note
Common API for ADC/DAC blocks

◆ XRFdc_Shutdown()

int XRFdc_Shutdown ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id 
)

#include <xrfdc.h>

The API stops the tile as requested.

It can also stop all the tiles if asked for. It does not clear any of the existing register settings. It just stops the requested tile(s).

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if tile is not enabled or available
Note
None

◆ XRFdc_StartUp()

int XRFdc_StartUp ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id 
)

#include <xrfdc.h>

The API Restarts the requested tile.

It can restart a single tile and alternatively can restart all the tiles. Existing register settings are not lost or altered in the process. It just starts the requested tile(s).

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3, and -1.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if tile is not enabled or available
Note
None

◆ XRFdc_UpdateEvent()

int XRFdc_UpdateEvent ( XRFdc InstancePtr,
u32  Type,
int  Tile_Id,
u32  Block_Id,
u32  Event 
)

#include <xrfdc.h>

This function will trigger the update event for an event.

Parameters
InstancePtris a pointer to the XRfdc instance.
Typeis ADC or DAC. 0 for ADC and 1 for DAC
Tile_IdValid values are 0-3.
Block_Idis ADC/DAC block number inside the tile. Valid values are 0-3.
Eventis for which dynamic update event will trigger. XRFDC_EVENT_* defines the different events.
Returns
  • XRFDC_SUCCESS if successful.
  • XRFDC_FAILURE if Block not enabled.
Note
Common API for ADC/DAC blocks

Variable Documentation

◆ XRFdc_ConfigTable [1/2]

XRFdc_Config XRFdc_ConfigTable[]

#include <xrfdc_sinit.c>

The configuration table for devices.

◆ XRFdc_ConfigTable [2/2]

XRFdc_Config XRFdc_ConfigTable[XPAR_XRFDC_NUM_INSTANCES]

#include <xrfdc_g.c>

The configuration table for devices.