sdps
Xilinx SDK Drivers API Documentation
Sdps_v3_3

Data Structures

struct  XSdPs_Config
 This typedef contains configuration information for the device. More...
 
struct  XSdPs
 The XSdPs driver instance data. More...
 

Macros

#define XSDPS_CT_ERROR   0x2U
 Command timeout flag. More...
 
#define MAX_TUNING_COUNT   40U
 Maximum Tuning count. More...
 

Functions

u32 XSdPs_FrameCmd (XSdPs *InstancePtr, u32 Cmd)
 This function frames the Command register for a particular command. More...
 
s32 XSdPs_CmdTransfer (XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
 This function does SD command generation. More...
 
void XSdPs_SetupADMA2DescTbl (XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
 API to setup ADMA2 descriptor table. More...
 
s32 XSdPs_CfgInitialize (XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, u32 EffectiveAddr)
 Initializes a specific XSdPs instance such that the driver is ready to use. More...
 
s32 XSdPs_SdCardInitialize (XSdPs *InstancePtr)
 SD initialization is done in this function. More...
 
s32 XSdPs_CardInitialize (XSdPs *InstancePtr)
 Initialize Card with Identification mode sequence. More...
 
s32 XSdPs_ReadPolled (XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
 This function performs SD read in polled mode. More...
 
s32 XSdPs_WritePolled (XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
 This function performs SD write in polled mode. More...
 
s32 XSdPs_Select_Card (XSdPs *InstancePtr)
 Selects card and sets default block size. More...
 
s32 XSdPs_MmcCardInitialize (XSdPs *InstancePtr)
 Mmc initialization is done in this function. More...
 
XSdPs_ConfigXSdPs_LookupConfig (u16 DeviceId)
 Looks up the device configuration based on the unique device ID. More...
 
s32 XSdPs_SetBlkSize (XSdPs *InstancePtr, u16 BlkSize)
 Update Block size for read/write operations. More...
 
s32 XSdPs_Change_ClkFreq (XSdPs *InstancePtr, u32 SelFreq)
 API to change clock freq to given value. More...
 
s32 XSdPs_Change_BusWidth (XSdPs *InstancePtr)
 API to set bus width to 4-bit in card and host. More...
 
s32 XSdPs_Change_BusSpeed (XSdPs *InstancePtr)
 API to set high speed in card and host. More...
 
s32 XSdPs_Get_BusWidth (XSdPs *InstancePtr, u8 *SCR)
 API to get bus width support by card. More...
 
s32 XSdPs_Get_BusSpeed (XSdPs *InstancePtr, u8 *ReadBuff)
 API to get bus speed supported by card. More...
 
s32 XSdPs_Pullup (XSdPs *InstancePtr)
 API to send pullup command to card before using DAT line 3(using 4-bit bus) More...
 
s32 XSdPs_Get_Mmc_ExtCsd (XSdPs *InstancePtr, u8 *ReadBuff)
 API to get EXT_CSD register of eMMC. More...
 
s32 XSdPs_Set_Mmc_ExtCsd (XSdPs *InstancePtr, u32 Arg)
 API to write EXT_CSD register of eMMC. More...
 

Register Map

Register offsets from the base address of an SD device.

#define XSDPS_SDMA_SYS_ADDR_OFFSET   0x00U
 SDMA System Address Register. More...
 
#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET   XSDPS_SDMA_SYS_ADDR_OFFSET
 SDMA System Address Low Register. More...
 
#define XSDPS_ARGMT2_LO_OFFSET   0x00U
 Argument2 Low Register. More...
 
#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET   0x02U
 SDMA System Address High Register. More...
 
#define XSDPS_ARGMT2_HI_OFFSET   0x02U
 Argument2 High Register. More...
 
#define XSDPS_BLK_SIZE_OFFSET   0x04U
 Block Size Register. More...
 
#define XSDPS_BLK_CNT_OFFSET   0x06U
 Block Count Register. More...
 
#define XSDPS_ARGMT_OFFSET   0x08U
 Argument Register. More...
 
#define XSDPS_ARGMT1_LO_OFFSET   XSDPS_ARGMT_OFFSET
 Argument1 Register. More...
 
#define XSDPS_ARGMT1_HI_OFFSET   0x0AU
 Argument1 Register. More...
 
#define XSDPS_XFER_MODE_OFFSET   0x0CU
 Transfer Mode Register. More...
 
#define XSDPS_CMD_OFFSET   0x0EU
 Command Register. More...
 
#define XSDPS_RESP0_OFFSET   0x10U
 Response0 Register. More...
 
#define XSDPS_RESP1_OFFSET   0x14U
 Response1 Register. More...
 
#define XSDPS_RESP2_OFFSET   0x18U
 Response2 Register. More...
 
#define XSDPS_RESP3_OFFSET   0x1CU
 Response3 Register. More...
 
#define XSDPS_BUF_DAT_PORT_OFFSET   0x20U
 Buffer Data Port. More...
 
#define XSDPS_PRES_STATE_OFFSET   0x24U
 Present State. More...
 
#define XSDPS_HOST_CTRL1_OFFSET   0x28U
 Host Control 1. More...
 
#define XSDPS_POWER_CTRL_OFFSET   0x29U
 Power Control. More...
 
#define XSDPS_BLK_GAP_CTRL_OFFSET   0x2AU
 Block Gap Control. More...
 
#define XSDPS_WAKE_UP_CTRL_OFFSET   0x2BU
 Wake Up Control. More...
 
#define XSDPS_CLK_CTRL_OFFSET   0x2CU
 Clock Control. More...
 
#define XSDPS_TIMEOUT_CTRL_OFFSET   0x2EU
 Timeout Control. More...
 
#define XSDPS_SW_RST_OFFSET   0x2FU
 Software Reset. More...
 
#define XSDPS_NORM_INTR_STS_OFFSET   0x30U
 Normal Interrupt Status Register. More...
 
#define XSDPS_ERR_INTR_STS_OFFSET   0x32U
 Error Interrupt Status Register. More...
 
#define XSDPS_NORM_INTR_STS_EN_OFFSET   0x34U
 Normal Interrupt Status Enable Register. More...
 
#define XSDPS_ERR_INTR_STS_EN_OFFSET   0x36U
 Error Interrupt Status Enable Register. More...
 
#define XSDPS_NORM_INTR_SIG_EN_OFFSET   0x38U
 Normal Interrupt Signal Enable Register. More...
 
#define XSDPS_ERR_INTR_SIG_EN_OFFSET   0x3AU
 Error Interrupt Signal Enable Register. More...
 
#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET   0x3CU
 Auto CMD12 Error Status Register. More...
 
#define XSDPS_HOST_CTRL2_OFFSET   0x3EU
 Host Control2 Register. More...
 
#define XSDPS_CAPS_OFFSET   0x40U
 Capabilities Register. More...
 
#define XSDPS_CAPS_EXT_OFFSET   0x44U
 Capabilities Extended. More...
 
#define XSDPS_MAX_CURR_CAPS_OFFSET   0x48U
 Maximum Current Capabilities Register. More...
 
#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET   0x4CU
 Maximum Current Capabilities Ext Register. More...
 
#define XSDPS_FE_ERR_INT_STS_OFFSET   0x52U
 Force Event for Error Interrupt Status. More...
 
#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET   0x50U
 Auto CM12 Error Interrupt Status Register. More...
 
#define XSDPS_ADMA_ERR_STS_OFFSET   0x54U
 ADMA Error Status Register. More...
 
#define XSDPS_ADMA_SAR_OFFSET   0x58U
 ADMA System Address Register. More...
 
#define XSDPS_ADMA_SAR_EXT_OFFSET   0x5CU
 ADMA System Address Extended Register. More...
 
#define XSDPS_PRE_VAL_1_OFFSET   0x60U
 Preset Value Register. More...
 
#define XSDPS_PRE_VAL_2_OFFSET   0x64U
 Preset Value Register. More...
 
#define XSDPS_PRE_VAL_3_OFFSET   0x68U
 Preset Value Register. More...
 
#define XSDPS_PRE_VAL_4_OFFSET   0x6CU
 Preset Value Register. More...
 
#define XSDPS_BOOT_TOUT_CTRL_OFFSET   0x70U
 Boot timeout control register. More...
 
#define XSDPS_SHARED_BUS_CTRL_OFFSET   0xE0U
 Shared Bus Control Register. More...
 
#define XSDPS_SLOT_INTR_STS_OFFSET   0xFCU
 Slot Interrupt Status Register. More...
 
#define XSDPS_HOST_CTRL_VER_OFFSET   0xFEU
 Host Controller Version Register. More...
 

Control Register - Host control, Power control,

Block Gap control and Wakeup control

This register contains bits for various configuration options of the SD host controller. Read/Write apart from the reserved bits.

#define XSDPS_HC_LED_MASK   0x00000001U
 LED Control. More...
 
#define XSDPS_HC_WIDTH_MASK   0x00000002U
 Bus width. More...
 
#define XSDPS_HC_BUS_WIDTH_4   0x00000002U
 
#define XSDPS_HC_SPEED_MASK   0x00000004U
 High Speed. More...
 
#define XSDPS_HC_DMA_MASK   0x00000018U
 DMA Mode Select. More...
 
#define XSDPS_HC_DMA_SDMA_MASK   0x00000000U
 SDMA Mode. More...
 
#define XSDPS_HC_DMA_ADMA1_MASK   0x00000008U
 ADMA1 Mode. More...
 
#define XSDPS_HC_DMA_ADMA2_32_MASK   0x00000010U
 ADMA2 Mode - 32 bit. More...
 
#define XSDPS_HC_DMA_ADMA2_64_MASK   0x00000018U
 ADMA2 Mode - 64 bit. More...
 
#define XSDPS_HC_EXT_BUS_WIDTH   0x00000020U
 Bus width - 8 bit. More...
 
#define XSDPS_HC_CARD_DET_TL_MASK   0x00000040U
 Card Detect Tst Lvl. More...
 
#define XSDPS_HC_CARD_DET_SD_MASK   0x00000080U
 Card Detect Sig Det. More...
 
#define XSDPS_PC_BUS_PWR_MASK   0x00000001U
 Bus Power Control. More...
 
#define XSDPS_PC_BUS_VSEL_MASK   0x0000000EU
 Bus Voltage Select. More...
 
#define XSDPS_PC_BUS_VSEL_3V3_MASK   0x0000000EU
 Bus Voltage 3.3V. More...
 
#define XSDPS_PC_BUS_VSEL_3V0_MASK   0x0000000CU
 Bus Voltage 3.0V. More...
 
#define XSDPS_PC_BUS_VSEL_1V8_MASK   0x0000000AU
 Bus Voltage 1.8V. More...
 
#define XSDPS_PC_EMMC_HW_RST_MASK   0x00000010U
 HW reset for eMMC. More...
 
#define XSDPS_BGC_STP_REQ_MASK   0x00000001U
 Block Gap Stop Req. More...
 
#define XSDPS_BGC_CNT_REQ_MASK   0x00000002U
 Block Gap Cont Req. More...
 
#define XSDPS_BGC_RWC_MASK   0x00000004U
 Block Gap Rd Wait. More...
 
#define XSDPS_BGC_INTR_MASK   0x00000008U
 Block Gap Intr. More...
 
#define XSDPS_BGC_SPI_MODE_MASK   0x00000010U
 Block Gap SPI Mode. More...
 
#define XSDPS_BGC_BOOT_EN_MASK   0x00000020U
 Block Gap Boot Enb. More...
 
#define XSDPS_BGC_ALT_BOOT_EN_MASK   0x00000040U
 Block Gap Alt BootEn. More...
 
#define XSDPS_BGC_BOOT_ACK_MASK   0x00000080U
 Block Gap Boot Ack. More...
 
#define XSDPS_WC_WUP_ON_INTR_MASK   0x00000001U
 Wakeup Card Intr. More...
 
#define XSDPS_WC_WUP_ON_INSRT_MASK   0x00000002U
 Wakeup Card Insert. More...
 
#define XSDPS_WC_WUP_ON_REM_MASK   0x00000004U
 Wakeup Card Removal. More...
 

Control Register - Clock control, Timeout control & Software reset

This register contains bits for configuration options of clock, timeout and software reset.

Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.

#define XSDPS_CC_INT_CLK_EN_MASK   0x00000001U
 
#define XSDPS_CC_INT_CLK_STABLE_MASK   0x00000002U
 
#define XSDPS_CC_SD_CLK_EN_MASK   0x00000004U
 
#define XSDPS_CC_SD_CLK_GEN_SEL_MASK   0x00000020U
 
#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK   0x000000C0U
 
#define XSDPS_CC_SDCLK_FREQ_SEL_MASK   0x0000FF00U
 
#define XSDPS_CC_SDCLK_FREQ_D256_MASK   0x00008000U
 
#define XSDPS_CC_SDCLK_FREQ_D128_MASK   0x00004000U
 
#define XSDPS_CC_SDCLK_FREQ_D64_MASK   0x00002000U
 
#define XSDPS_CC_SDCLK_FREQ_D32_MASK   0x00001000U
 
#define XSDPS_CC_SDCLK_FREQ_D16_MASK   0x00000800U
 
#define XSDPS_CC_SDCLK_FREQ_D8_MASK   0x00000400U
 
#define XSDPS_CC_SDCLK_FREQ_D4_MASK   0x00000200U
 
#define XSDPS_CC_SDCLK_FREQ_D2_MASK   0x00000100U
 
#define XSDPS_CC_SDCLK_FREQ_BASE_MASK   0x00000000U
 
#define XSDPS_CC_MAX_DIV_CNT   256U
 
#define XSDPS_CC_EXT_MAX_DIV_CNT   2046U
 
#define XSDPS_CC_EXT_DIV_SHIFT   6U
 
#define XSDPS_TC_CNTR_VAL_MASK   0x0000000FU
 
#define XSDPS_SWRST_ALL_MASK   0x00000001U
 
#define XSDPS_SWRST_CMD_LINE_MASK   0x00000002U
 
#define XSDPS_SWRST_DAT_LINE_MASK   0x00000004U
 
#define XSDPS_CC_MAX_NUM_OF_DIV   9U
 
#define XSDPS_CC_DIV_SHIFT   8U
 

SD Interrupt Registers

Normal and Error Interrupt Status Register This register shows the normal and error interrupt status.

Status enable register affects reads of this register. If Signal enable register is set and the corresponding status bit is set, interrupt is generated. Write to clear except Error_interrupt and Card_Interrupt bits - Read only

Normal and Error Interrupt Status Enable Register Setting this register bits enables Interrupt status. Read/Write except Fixed_to_0 bit (Read only)

Normal and Error Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the interrupt. Read/Write except Fixed_to_0 bit (Read only)

All three registers have same bit definitions

#define XSDPS_INTR_CC_MASK   0x00000001U
 Command Complete. More...
 
#define XSDPS_INTR_TC_MASK   0x00000002U
 Transfer Complete. More...
 
#define XSDPS_INTR_BGE_MASK   0x00000004U
 Block Gap Event. More...
 
#define XSDPS_INTR_DMA_MASK   0x00000008U
 DMA Interrupt. More...
 
#define XSDPS_INTR_BWR_MASK   0x00000010U
 Buffer Write Ready. More...
 
#define XSDPS_INTR_BRR_MASK   0x00000020U
 Buffer Read Ready. More...
 
#define XSDPS_INTR_CARD_INSRT_MASK   0x00000040U
 Card Insert. More...
 
#define XSDPS_INTR_CARD_REM_MASK   0x00000080U
 Card Remove. More...
 
#define XSDPS_INTR_CARD_MASK   0x00000100U
 Card Interrupt. More...
 
#define XSDPS_INTR_INT_A_MASK   0x00000200U
 INT A Interrupt. More...
 
#define XSDPS_INTR_INT_B_MASK   0x00000400U
 INT B Interrupt. More...
 
#define XSDPS_INTR_INT_C_MASK   0x00000800U
 INT C Interrupt. More...
 
#define XSDPS_INTR_RE_TUNING_MASK   0x00001000U
 Re-Tuning Interrupt. More...
 
#define XSDPS_INTR_BOOT_ACK_RECV_MASK   0x00002000U
 Boot Ack Recv Interrupt. More...
 
#define XSDPS_INTR_BOOT_TERM_MASK   0x00004000U
 Boot Terminate Interrupt. More...
 
#define XSDPS_INTR_ERR_MASK   0x00008000U
 Error Interrupt. More...
 
#define XSDPS_NORM_INTR_ALL_MASK   0x0000FFFFU
 
#define XSDPS_INTR_ERR_CT_MASK   0x00000001U
 Command Timeout Error. More...
 
#define XSDPS_INTR_ERR_CCRC_MASK   0x00000002U
 Command CRC Error. More...
 
#define XSDPS_INTR_ERR_CEB_MASK   0x00000004U
 Command End Bit Error. More...
 
#define XSDPS_INTR_ERR_CI_MASK   0x00000008U
 Command Index Error. More...
 
#define XSDPS_INTR_ERR_DT_MASK   0x00000010U
 Data Timeout Error. More...
 
#define XSDPS_INTR_ERR_DCRC_MASK   0x00000020U
 Data CRC Error. More...
 
#define XSDPS_INTR_ERR_DEB_MASK   0x00000040U
 Data End Bit Error. More...
 
#define XSDPS_INTR_ERR_CUR_LMT_MASK   0x00000080U
 Current Limit Error. More...
 
#define XSDPS_INTR_ERR_AUTO_CMD12_MASK   0x00000100U
 Auto CMD12 Error. More...
 
#define XSDPS_INTR_ERR_ADMA_MASK   0x00000200U
 ADMA Error. More...
 
#define XSDPS_INTR_ERR_TR_MASK   0x00001000U
 Tuning Error. More...
 
#define XSDPS_INTR_VEND_SPF_ERR_MASK   0x0000E000U
 Vendor Specific Error. More...
 
#define XSDPS_ERROR_INTR_ALL_MASK   0x0000F3FFU
 Mask for error bits. More...
 

Block Size and Block Count Register

This register contains the block count for current transfer, block size and SDMA buffer size.

Read/Write except for reserved bits.

#define XSDPS_BLK_SIZE_MASK   0x00000FFFU
 Transfer Block Size. More...
 
#define XSDPS_SDMA_BUFF_SIZE_MASK   0x00007000U
 Host SDMA Buffer Size. More...
 
#define XSDPS_BLK_SIZE_1024   0x400U
 
#define XSDPS_BLK_SIZE_2048   0x800U
 
#define XSDPS_BLK_CNT_MASK   0x0000FFFFU
 Block Count for Current Transfer. More...
 

Transfer Mode and Command Register

The Transfer Mode register is used to control the data transfers and Command register is used for command generation Read/Write except for reserved bits.

#define XSDPS_TM_DMA_EN_MASK   0x00000001U
 DMA Enable. More...
 
#define XSDPS_TM_BLK_CNT_EN_MASK   0x00000002U
 Block Count Enable. More...
 
#define XSDPS_TM_AUTO_CMD12_EN_MASK   0x00000004U
 Auto CMD12 Enable. More...
 
#define XSDPS_TM_DAT_DIR_SEL_MASK   0x00000010U
 Data Transfer Direction Select. More...
 
#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK   0x00000020U
 Multi/Single Block Select. More...
 
#define XSDPS_CMD_RESP_SEL_MASK   0x00000003U
 Response Type Select. More...
 
#define XSDPS_CMD_RESP_NONE_MASK   0x00000000U
 No Response. More...
 
#define XSDPS_CMD_RESP_L136_MASK   0x00000001U
 Response length 138. More...
 
#define XSDPS_CMD_RESP_L48_MASK   0x00000002U
 Response length 48. More...
 
#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK   0x00000003U
 Response length 48 & check busy after response. More...
 
#define XSDPS_CMD_CRC_CHK_EN_MASK   0x00000008U
 Command CRC Check Enable. More...
 
#define XSDPS_CMD_INX_CHK_EN_MASK   0x00000010U
 Command Index Check Enable. More...
 
#define XSDPS_DAT_PRESENT_SEL_MASK   0x00000020U
 Data Present Select. More...
 
#define XSDPS_CMD_TYPE_MASK   0x000000C0U
 Command Type. More...
 
#define XSDPS_CMD_TYPE_NORM_MASK   0x00000000U
 CMD Type - Normal. More...
 
#define XSDPS_CMD_TYPE_SUSPEND_MASK   0x00000040U
 CMD Type - Suspend. More...
 
#define XSDPS_CMD_TYPE_RESUME_MASK   0x00000080U
 CMD Type - Resume. More...
 
#define XSDPS_CMD_TYPE_ABORT_MASK   0x000000C0U
 CMD Type - Abort. More...
 
#define XSDPS_CMD_MASK   0x00003F00U
 Command Index Mask - Set to CMD0-63, AMCD0-63. More...
 

Auto CMD Error Status Register

This register is read only register which contains information about the error status of Auto CMD 12 and 23.

Read Only

#define XSDPS_AUTO_CMD12_NT_EX_MASK   0x0001U
 Auto CMD12 Not executed. More...
 
#define XSDPS_AUTO_CMD_TOUT_MASK   0x0002U
 Auto CMD Timeout Error. More...
 
#define XSDPS_AUTO_CMD_CRC_MASK   0x0004U
 Auto CMD CRC Error. More...
 
#define XSDPS_AUTO_CMD_EB_MASK   0x0008U
 Auto CMD End Bit Error. More...
 
#define XSDPS_AUTO_CMD_IND_MASK   0x0010U
 Auto CMD Index Error. More...
 
#define XSDPS_AUTO_CMD_CNI_ERR_MASK   0x0080U
 Command not issued by Auto CMD12 Error. More...
 

Host Control2 Register

This register contains extended configuration bits.

Read Write

#define XSDPS_HC2_UHS_MODE_MASK   0x0007U
 UHS Mode select bits. More...
 
#define XSDPS_HC2_UHS_MODE_SDR12_MASK   0x0000U
 SDR12 UHS Mode. More...
 
#define XSDPS_HC2_UHS_MODE_SDR25_MASK   0x0001U
 SDR25 UHS Mode. More...
 
#define XSDPS_HC2_UHS_MODE_SDR50_MASK   0x0002U
 SDR50 UHS Mode. More...
 
#define XSDPS_HC2_UHS_MODE_SDR104_MASK   0x0003U
 SDR104 UHS Mode. More...
 
#define XSDPS_HC2_UHS_MODE_DDR50_MASK   0x0004U
 DDR50 UHS Mode. More...
 
#define XSDPS_HC2_1V8_EN_MASK   0x0008U
 1.8V Signal Enable More...
 
#define XSDPS_HC2_DRV_STR_SEL_MASK   0x0030U
 Driver Strength Selection. More...
 
#define XSDPS_HC2_DRV_STR_B_MASK   0x0000U
 Driver Strength B. More...
 
#define XSDPS_HC2_DRV_STR_A_MASK   0x0010U
 Driver Strength A. More...
 
#define XSDPS_HC2_DRV_STR_C_MASK   0x0020U
 Driver Strength C. More...
 
#define XSDPS_HC2_DRV_STR_D_MASK   0x0030U
 Driver Strength D. More...
 
#define XSDPS_HC2_EXEC_TNG_MASK   0x0040U
 Execute Tuning. More...
 
#define XSDPS_HC2_SAMP_CLK_SEL_MASK   0x0080U
 Sampling Clock Selection. More...
 
#define XSDPS_HC2_ASYNC_INTR_EN_MASK   0x4000U
 Asynchronous Interrupt Enable. More...
 
#define XSDPS_HC2_PRE_VAL_EN_MASK   0x8000U
 Preset Value Enable. More...
 

Capabilities Register

Capabilities register is a read only register which contains information about the host controller.

Sufficient if read once after power on. Read Only

#define XSDPS_CAP_TOUT_CLK_FREQ_MASK   0x0000003FU
 Timeout clock freq select. More...
 
#define XSDPS_CAP_TOUT_CLK_UNIT_MASK   0x00000080U
 Timeout clock unit - MHz/KHz. More...
 
#define XSDPS_CAP_MAX_BLK_LEN_MASK   0x00030000U
 Max block length. More...
 
#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK   0x00000000U
 Max block 512 bytes. More...
 
#define XSDPS_CAP_MAX_BL_LN_1024_MASK   0x00010000U
 Max block 1024 bytes. More...
 
#define XSDPS_CAP_MAX_BL_LN_2048_MASK   0x00020000U
 Max block 2048 bytes. More...
 
#define XSDPS_CAP_MAX_BL_LN_4096_MASK   0x00030000U
 Max block 4096 bytes. More...
 
#define XSDPS_CAP_EXT_MEDIA_BUS_MASK   0x00040000U
 Extended media bus. More...
 
#define XSDPS_CAP_ADMA2_MASK   0x00080000U
 ADMA2 support. More...
 
#define XSDPS_CAP_HIGH_SPEED_MASK   0x00200000U
 High speed support. More...
 
#define XSDPS_CAP_SDMA_MASK   0x00400000U
 SDMA support. More...
 
#define XSDPS_CAP_SUSP_RESUME_MASK   0x00800000U
 Suspend/Resume support. More...
 
#define XSDPS_CAP_VOLT_3V3_MASK   0x01000000U
 3.3V support More...
 
#define XSDPS_CAP_VOLT_3V0_MASK   0x02000000U
 3.0V support More...
 
#define XSDPS_CAP_VOLT_1V8_MASK   0x04000000U
 1.8V support More...
 
#define XSDPS_CAP_SYS_BUS_64_MASK   0x10000000U
 64 bit system bus support More...
 
#define XSDPS_CAP_INTR_MODE_MASK   0x08000000U
 Interrupt mode support. More...
 
#define XSDPS_CAP_SPI_MODE_MASK   0x20000000U
 SPI mode. More...
 
#define XSDPS_CAP_SPI_BLOCK_MODE_MASK   0x40000000U
 SPI block mode. More...
 
#define XSDPS_CAPS_ASYNC_INTR_MASK   0x20000000U
 Async Interrupt support. More...
 
#define XSDPS_CAPS_SLOT_TYPE_MASK   0xC0000000U
 Slot Type. More...
 
#define XSDPS_CAPS_REM_CARD   0x00000000U
 Removable Slot. More...
 
#define XSDPS_CAPS_EMB_SLOT   0x40000000U
 Embedded Slot. More...
 
#define XSDPS_CAPS_SHR_BUS   0x80000000U
 Shared Bus Slot. More...
 
#define XSDPS_ECAPS_SDR50_MASK   0x00000001U
 SDR50 Mode support. More...
 
#define XSDPS_ECAPS_SDR104_MASK   0x00000002U
 SDR104 Mode support. More...
 
#define XSDPS_ECAPS_DDR50_MASK   0x00000004U
 DDR50 Mode support. More...
 
#define XSDPS_ECAPS_DRV_TYPE_A_MASK   0x00000010U
 DriverType A support. More...
 
#define XSDPS_ECAPS_DRV_TYPE_C_MASK   0x00000020U
 DriverType C support. More...
 
#define XSDPS_ECAPS_DRV_TYPE_D_MASK   0x00000040U
 DriverType D support. More...
 
#define XSDPS_ECAPS_TMR_CNT_MASK   0x00000F00U
 Timer Count for Re-tuning. More...
 
#define XSDPS_ECAPS_USE_TNG_SDR50_MASK   0x00002000U
 SDR50 Mode needs tuning. More...
 
#define XSDPS_ECAPS_RE_TNG_MODES_MASK   0x0000C000U
 Re-tuning modes support. More...
 
#define XSDPS_ECAPS_RE_TNG_MODE1_MASK   0x00000000U
 Re-tuning mode 1. More...
 
#define XSDPS_ECAPS_RE_TNG_MODE2_MASK   0x00004000U
 Re-tuning mode 2. More...
 
#define XSDPS_ECAPS_RE_TNG_MODE3_MASK   0x00008000U
 Re-tuning mode 3. More...
 
#define XSDPS_ECAPS_CLK_MULT_MASK   0x00FF0000U
 Clock Multiplier value for Programmable clock mode. More...
 
#define XSDPS_ECAPS_SPI_MODE_MASK   0x01000000U
 SPI mode. More...
 
#define XSDPS_ECAPS_SPI_BLK_MODE_MASK   0x02000000U
 SPI block mode. More...
 

Present State Register

Gives the current status of the host controller Read Only

#define XSDPS_PSR_INHIBIT_CMD_MASK   0x00000001U
 Command inhibit - CMD. More...
 
#define XSDPS_PSR_INHIBIT_DAT_MASK   0x00000002U
 Command Inhibit - DAT. More...
 
#define XSDPS_PSR_DAT_ACTIVE_MASK   0x00000004U
 DAT line active. More...
 
#define XSDPS_PSR_RE_TUNING_REQ_MASK   0x00000008U
 Re-tuning request. More...
 
#define XSDPS_PSR_WR_ACTIVE_MASK   0x00000100U
 Write transfer active. More...
 
#define XSDPS_PSR_RD_ACTIVE_MASK   0x00000200U
 Read transfer active. More...
 
#define XSDPS_PSR_BUFF_WR_EN_MASK   0x00000400U
 Buffer write enable. More...
 
#define XSDPS_PSR_BUFF_RD_EN_MASK   0x00000800U
 Buffer read enable. More...
 
#define XSDPS_PSR_CARD_INSRT_MASK   0x00010000U
 Card inserted. More...
 
#define XSDPS_PSR_CARD_STABLE_MASK   0x00020000U
 Card state stable. More...
 
#define XSDPS_PSR_CARD_DPL_MASK   0x00040000U
 Card detect pin level. More...
 
#define XSDPS_PSR_WPS_PL_MASK   0x00080000U
 Write protect switch pin level. More...
 
#define XSDPS_PSR_DAT30_SG_LVL_MASK   0x00F00000U
 Data 3:0 signal lvl. More...
 
#define XSDPS_PSR_CMD_SG_LVL_MASK   0x01000000U
 Cmd Line signal lvl. More...
 
#define XSDPS_PSR_DAT74_SG_LVL_MASK   0x1E000000U
 Data 7:4 signal lvl. More...
 

Maximum Current Capablities Register

This register is read only register which contains information about current capabilities at each voltage levels.

Read Only

#define XSDPS_MAX_CUR_CAPS_1V8_MASK   0x00000F00U
 Maximum Current Capability at 1.8V. More...
 
#define XSDPS_MAX_CUR_CAPS_3V0_MASK   0x000000F0U
 Maximum Current Capability at 3.0V. More...
 
#define XSDPS_MAX_CUR_CAPS_3V3_MASK   0x0000000FU
 Maximum Current Capability at 3.3V. More...
 

Force Event for Auto CMD Error Status Register

This register is write only register which contains control bits to generate events for Auto CMD error status.

Write Only

#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK   0x0001U
 Auto CMD12 Not executed. More...
 
#define XSDPS_FE_AUTO_CMD_TOUT_MASK   0x0002U
 Auto CMD Timeout Error. More...
 
#define XSDPS_FE_AUTO_CMD_CRC_MASK   0x0004U
 Auto CMD CRC Error. More...
 
#define XSDPS_FE_AUTO_CMD_EB_MASK   0x0008U
 Auto CMD End Bit Error. More...
 
#define XSDPS_FE_AUTO_CMD_IND_MASK   0x0010U
 Auto CMD Index Error. More...
 
#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK   0x0080U
 Command not issued by Auto CMD12 Error. More...
 

Force Event for Error Interrupt Status Register

This register is write only register which contains control bits to generate events of error interrupt status register.

Write Only

#define XSDPS_FE_INTR_ERR_CT_MASK   0x0001U
 Command Timeout Error. More...
 
#define XSDPS_FE_INTR_ERR_CCRC_MASK   0x0002U
 Command CRC Error. More...
 
#define XSDPS_FE_INTR_ERR_CEB_MASK   0x0004U
 Command End Bit Error. More...
 
#define XSDPS_FE_INTR_ERR_CI_MASK   0x0008U
 Command Index Error. More...
 
#define XSDPS_FE_INTR_ERR_DT_MASK   0x0010U
 Data Timeout Error. More...
 
#define XSDPS_FE_INTR_ERR_DCRC_MASK   0x0020U
 Data CRC Error. More...
 
#define XSDPS_FE_INTR_ERR_DEB_MASK   0x0040U
 Data End Bit Error. More...
 
#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK   0x0080U
 Current Limit Error. More...
 
#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK   0x0100U
 Auto CMD Error. More...
 
#define XSDPS_FE_INTR_ERR_ADMA_MASK   0x0200U
 ADMA Error. More...
 
#define XSDPS_FE_INTR_ERR_TR_MASK   0x1000U
 Target Reponse. More...
 
#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK   0xE000U
 Vendor Specific Error. More...
 

ADMA Error Status Register

This register is read only register which contains status information about ADMA errors.

Read Only

#define XSDPS_ADMA_ERR_MM_LEN_MASK   0x04U
 ADMA Length Mismatch Error. More...
 
#define XSDPS_ADMA_ERR_STATE_MASK   0x03U
 ADMA Error State. More...
 
#define XSDPS_ADMA_ERR_STATE_STOP_MASK   0x00U
 ADMA Error State STOP. More...
 
#define XSDPS_ADMA_ERR_STATE_FDS_MASK   0x01U
 ADMA Error State FDS. More...
 
#define XSDPS_ADMA_ERR_STATE_TFR_MASK   0x03U
 ADMA Error State TFR. More...
 

Preset Values Register

This register is read only register which contains preset values for each of speed modes.

Read Only

#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK   0x03FFU
 SDCLK Frequency Select Value. More...
 
#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK   0x0400U
 Clock Generator Mode Select. More...
 
#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK   0xC000U
 Driver Strength Select Value. More...
 

Slot Interrupt Status Register

This register is read only register which contains interrupt slot signal for each slot.

Read Only

#define XSDPS_SLOT_INTR_STS_INT_MASK   0x0007U
 Interrupt Signal mask. More...
 

Host Controller Version Register

This register is read only register which contains Host Controller and Vendor Specific version.

Read Only

#define XSDPS_HC_VENDOR_VER   0xFF00U
 Vendor Specification version mask. More...
 
#define XSDPS_HC_SPEC_VER_MASK   0x00FFU
 Host Specification version mask. More...
 
#define XSDPS_HC_SPEC_V3   0x0002U
 
#define XSDPS_HC_SPEC_V2   0x0001U
 
#define XSDPS_HC_SPEC_V1   0x0000U
 

Block size mask for 512 bytes

Block size mask for 512 bytes - This is the default block size.

#define XSDPS_BLK_SIZE_512_MASK   0x200U
 

Commands

Constant definitions for commands and response related to SD

#define XSDPS_APP_CMD_PREFIX   0x8000U
 
#define CMD0   0x0000U
 
#define CMD1   0x0100U
 
#define CMD2   0x0200U
 
#define CMD3   0x0300U
 
#define CMD4   0x0400U
 
#define CMD5   0x0500U
 
#define CMD6   0x0600U
 
#define ACMD6   (XSDPS_APP_CMD_PREFIX + 0x0600U)
 
#define CMD7   0x0700U
 
#define CMD8   0x0800U
 
#define CMD9   0x0900U
 
#define CMD10   0x0A00U
 
#define CMD11   0x0B00U
 
#define CMD12   0x0C00U
 
#define ACMD13   (XSDPS_APP_CMD_PREFIX + 0x0D00U)
 
#define CMD16   0x1000U
 
#define CMD17   0x1100U
 
#define CMD18   0x1200U
 
#define CMD19   0x1300U
 
#define CMD21   0x1500U
 
#define CMD23   0x1700U
 
#define ACMD23   (XSDPS_APP_CMD_PREFIX + 0x1700U)
 
#define CMD24   0x1800U
 
#define CMD25   0x1900U
 
#define CMD41   0x2900U
 
#define ACMD41   (XSDPS_APP_CMD_PREFIX + 0x2900U)
 
#define ACMD42   (XSDPS_APP_CMD_PREFIX + 0x2A00U)
 
#define ACMD51   (XSDPS_APP_CMD_PREFIX + 0x3300U)
 
#define CMD52   0x3400U
 
#define CMD55   0x3700U
 
#define CMD58   0x3A00U
 
#define RESP_NONE   (u32)XSDPS_CMD_RESP_NONE_MASK
 
#define RESP_R1
 
#define RESP_R1B
 
#define RESP_R2   (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
 
#define RESP_R3   (u32)XSDPS_CMD_RESP_L48_MASK
 
#define RESP_R6
 

Macro Definition Documentation

◆ MAX_TUNING_COUNT

#define MAX_TUNING_COUNT   40U

#include <xsdps.h>

Maximum Tuning count.

◆ XSDPS_ADMA_ERR_MM_LEN_MASK

#define XSDPS_ADMA_ERR_MM_LEN_MASK   0x04U

#include <xsdps_hw.h>

ADMA Length Mismatch Error.

◆ XSDPS_ADMA_ERR_STATE_FDS_MASK

#define XSDPS_ADMA_ERR_STATE_FDS_MASK   0x01U

#include <xsdps_hw.h>

ADMA Error State FDS.

◆ XSDPS_ADMA_ERR_STATE_MASK

#define XSDPS_ADMA_ERR_STATE_MASK   0x03U

#include <xsdps_hw.h>

ADMA Error State.

◆ XSDPS_ADMA_ERR_STATE_STOP_MASK

#define XSDPS_ADMA_ERR_STATE_STOP_MASK   0x00U

#include <xsdps_hw.h>

ADMA Error State STOP.

◆ XSDPS_ADMA_ERR_STATE_TFR_MASK

#define XSDPS_ADMA_ERR_STATE_TFR_MASK   0x03U

#include <xsdps_hw.h>

ADMA Error State TFR.

◆ XSDPS_ADMA_ERR_STS_OFFSET

#define XSDPS_ADMA_ERR_STS_OFFSET   0x54U

#include <xsdps_hw.h>

ADMA Error Status Register.

◆ XSDPS_ADMA_SAR_EXT_OFFSET

#define XSDPS_ADMA_SAR_EXT_OFFSET   0x5CU

#include <xsdps_hw.h>

ADMA System Address Extended Register.

◆ XSDPS_ADMA_SAR_OFFSET

#define XSDPS_ADMA_SAR_OFFSET   0x58U

#include <xsdps_hw.h>

ADMA System Address Register.

◆ XSDPS_ARGMT1_HI_OFFSET

#define XSDPS_ARGMT1_HI_OFFSET   0x0AU

#include <xsdps_hw.h>

Argument1 Register.

◆ XSDPS_ARGMT1_LO_OFFSET

#define XSDPS_ARGMT1_LO_OFFSET   XSDPS_ARGMT_OFFSET

#include <xsdps_hw.h>

Argument1 Register.

◆ XSDPS_ARGMT2_HI_OFFSET

#define XSDPS_ARGMT2_HI_OFFSET   0x02U

#include <xsdps_hw.h>

Argument2 High Register.

◆ XSDPS_ARGMT2_LO_OFFSET

#define XSDPS_ARGMT2_LO_OFFSET   0x00U

#include <xsdps_hw.h>

Argument2 Low Register.

◆ XSDPS_ARGMT_OFFSET

#define XSDPS_ARGMT_OFFSET   0x08U

#include <xsdps_hw.h>

Argument Register.

◆ XSDPS_AUTO_CMD12_ERR_STS_OFFSET

#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET   0x3CU

#include <xsdps_hw.h>

Auto CMD12 Error Status Register.

◆ XSDPS_AUTO_CMD12_NT_EX_MASK

#define XSDPS_AUTO_CMD12_NT_EX_MASK   0x0001U

#include <xsdps_hw.h>

Auto CMD12 Not executed.

◆ XSDPS_AUTO_CMD_CNI_ERR_MASK

#define XSDPS_AUTO_CMD_CNI_ERR_MASK   0x0080U

#include <xsdps_hw.h>

Command not issued by Auto CMD12 Error.

◆ XSDPS_AUTO_CMD_CRC_MASK

#define XSDPS_AUTO_CMD_CRC_MASK   0x0004U

#include <xsdps_hw.h>

Auto CMD CRC Error.

◆ XSDPS_AUTO_CMD_EB_MASK

#define XSDPS_AUTO_CMD_EB_MASK   0x0008U

#include <xsdps_hw.h>

Auto CMD End Bit Error.

◆ XSDPS_AUTO_CMD_IND_MASK

#define XSDPS_AUTO_CMD_IND_MASK   0x0010U

#include <xsdps_hw.h>

Auto CMD Index Error.

◆ XSDPS_AUTO_CMD_TOUT_MASK

#define XSDPS_AUTO_CMD_TOUT_MASK   0x0002U

#include <xsdps_hw.h>

Auto CMD Timeout Error.

◆ XSDPS_BGC_ALT_BOOT_EN_MASK

#define XSDPS_BGC_ALT_BOOT_EN_MASK   0x00000040U

#include <xsdps_hw.h>

Block Gap Alt BootEn.

◆ XSDPS_BGC_BOOT_ACK_MASK

#define XSDPS_BGC_BOOT_ACK_MASK   0x00000080U

#include <xsdps_hw.h>

Block Gap Boot Ack.

◆ XSDPS_BGC_BOOT_EN_MASK

#define XSDPS_BGC_BOOT_EN_MASK   0x00000020U

#include <xsdps_hw.h>

Block Gap Boot Enb.

◆ XSDPS_BGC_CNT_REQ_MASK

#define XSDPS_BGC_CNT_REQ_MASK   0x00000002U

#include <xsdps_hw.h>

Block Gap Cont Req.

◆ XSDPS_BGC_INTR_MASK

#define XSDPS_BGC_INTR_MASK   0x00000008U

#include <xsdps_hw.h>

Block Gap Intr.

◆ XSDPS_BGC_RWC_MASK

#define XSDPS_BGC_RWC_MASK   0x00000004U

#include <xsdps_hw.h>

Block Gap Rd Wait.

◆ XSDPS_BGC_SPI_MODE_MASK

#define XSDPS_BGC_SPI_MODE_MASK   0x00000010U

#include <xsdps_hw.h>

Block Gap SPI Mode.

◆ XSDPS_BGC_STP_REQ_MASK

#define XSDPS_BGC_STP_REQ_MASK   0x00000001U

#include <xsdps_hw.h>

Block Gap Stop Req.

◆ XSDPS_BLK_CNT_MASK

#define XSDPS_BLK_CNT_MASK   0x0000FFFFU

#include <xsdps_hw.h>

Block Count for Current Transfer.

◆ XSDPS_BLK_CNT_OFFSET

#define XSDPS_BLK_CNT_OFFSET   0x06U

#include <xsdps_hw.h>

Block Count Register.

◆ XSDPS_BLK_GAP_CTRL_OFFSET

#define XSDPS_BLK_GAP_CTRL_OFFSET   0x2AU

#include <xsdps_hw.h>

Block Gap Control.

◆ XSDPS_BLK_SIZE_MASK

#define XSDPS_BLK_SIZE_MASK   0x00000FFFU

#include <xsdps_hw.h>

Transfer Block Size.

◆ XSDPS_BLK_SIZE_OFFSET

#define XSDPS_BLK_SIZE_OFFSET   0x04U

#include <xsdps_hw.h>

Block Size Register.

◆ XSDPS_BOOT_TOUT_CTRL_OFFSET

#define XSDPS_BOOT_TOUT_CTRL_OFFSET   0x70U

#include <xsdps_hw.h>

Boot timeout control register.

◆ XSDPS_BUF_DAT_PORT_OFFSET

#define XSDPS_BUF_DAT_PORT_OFFSET   0x20U

#include <xsdps_hw.h>

Buffer Data Port.

◆ XSDPS_CAP_ADMA2_MASK

#define XSDPS_CAP_ADMA2_MASK   0x00080000U

#include <xsdps_hw.h>

ADMA2 support.

◆ XSDPS_CAP_EXT_MEDIA_BUS_MASK

#define XSDPS_CAP_EXT_MEDIA_BUS_MASK   0x00040000U

#include <xsdps_hw.h>

Extended media bus.

◆ XSDPS_CAP_HIGH_SPEED_MASK

#define XSDPS_CAP_HIGH_SPEED_MASK   0x00200000U

#include <xsdps_hw.h>

High speed support.

◆ XSDPS_CAP_INTR_MODE_MASK

#define XSDPS_CAP_INTR_MODE_MASK   0x08000000U

#include <xsdps_hw.h>

Interrupt mode support.

◆ XSDPS_CAP_MAX_BL_LN_1024_MASK

#define XSDPS_CAP_MAX_BL_LN_1024_MASK   0x00010000U

#include <xsdps_hw.h>

Max block 1024 bytes.

◆ XSDPS_CAP_MAX_BL_LN_2048_MASK

#define XSDPS_CAP_MAX_BL_LN_2048_MASK   0x00020000U

#include <xsdps_hw.h>

Max block 2048 bytes.

◆ XSDPS_CAP_MAX_BL_LN_4096_MASK

#define XSDPS_CAP_MAX_BL_LN_4096_MASK   0x00030000U

#include <xsdps_hw.h>

Max block 4096 bytes.

◆ XSDPS_CAP_MAX_BLK_LEN_512B_MASK

#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK   0x00000000U

#include <xsdps_hw.h>

Max block 512 bytes.

◆ XSDPS_CAP_MAX_BLK_LEN_MASK

#define XSDPS_CAP_MAX_BLK_LEN_MASK   0x00030000U

#include <xsdps_hw.h>

Max block length.

◆ XSDPS_CAP_SDMA_MASK

#define XSDPS_CAP_SDMA_MASK   0x00400000U

#include <xsdps_hw.h>

SDMA support.

◆ XSDPS_CAP_SPI_BLOCK_MODE_MASK

#define XSDPS_CAP_SPI_BLOCK_MODE_MASK   0x40000000U

#include <xsdps_hw.h>

SPI block mode.

◆ XSDPS_CAP_SPI_MODE_MASK

#define XSDPS_CAP_SPI_MODE_MASK   0x20000000U

#include <xsdps_hw.h>

SPI mode.

◆ XSDPS_CAP_SUSP_RESUME_MASK

#define XSDPS_CAP_SUSP_RESUME_MASK   0x00800000U

#include <xsdps_hw.h>

Suspend/Resume support.

◆ XSDPS_CAP_SYS_BUS_64_MASK

#define XSDPS_CAP_SYS_BUS_64_MASK   0x10000000U

#include <xsdps_hw.h>

64 bit system bus support

◆ XSDPS_CAP_TOUT_CLK_FREQ_MASK

#define XSDPS_CAP_TOUT_CLK_FREQ_MASK   0x0000003FU

#include <xsdps_hw.h>

Timeout clock freq select.

◆ XSDPS_CAP_TOUT_CLK_UNIT_MASK

#define XSDPS_CAP_TOUT_CLK_UNIT_MASK   0x00000080U

#include <xsdps_hw.h>

Timeout clock unit - MHz/KHz.

◆ XSDPS_CAP_VOLT_1V8_MASK

#define XSDPS_CAP_VOLT_1V8_MASK   0x04000000U

#include <xsdps_hw.h>

1.8V support

◆ XSDPS_CAP_VOLT_3V0_MASK

#define XSDPS_CAP_VOLT_3V0_MASK   0x02000000U

#include <xsdps_hw.h>

3.0V support

◆ XSDPS_CAP_VOLT_3V3_MASK

#define XSDPS_CAP_VOLT_3V3_MASK   0x01000000U

#include <xsdps_hw.h>

3.3V support

◆ XSDPS_CAPS_ASYNC_INTR_MASK

#define XSDPS_CAPS_ASYNC_INTR_MASK   0x20000000U

#include <xsdps_hw.h>

Async Interrupt support.

◆ XSDPS_CAPS_EMB_SLOT

#define XSDPS_CAPS_EMB_SLOT   0x40000000U

#include <xsdps_hw.h>

Embedded Slot.

◆ XSDPS_CAPS_EXT_OFFSET

#define XSDPS_CAPS_EXT_OFFSET   0x44U

#include <xsdps_hw.h>

Capabilities Extended.

◆ XSDPS_CAPS_OFFSET

#define XSDPS_CAPS_OFFSET   0x40U

#include <xsdps_hw.h>

Capabilities Register.

◆ XSDPS_CAPS_REM_CARD

#define XSDPS_CAPS_REM_CARD   0x00000000U

#include <xsdps_hw.h>

Removable Slot.

◆ XSDPS_CAPS_SHR_BUS

#define XSDPS_CAPS_SHR_BUS   0x80000000U

#include <xsdps_hw.h>

Shared Bus Slot.

◆ XSDPS_CAPS_SLOT_TYPE_MASK

#define XSDPS_CAPS_SLOT_TYPE_MASK   0xC0000000U

#include <xsdps_hw.h>

Slot Type.

◆ XSDPS_CLK_CTRL_OFFSET

#define XSDPS_CLK_CTRL_OFFSET   0x2CU

#include <xsdps_hw.h>

Clock Control.

◆ XSDPS_CMD_CRC_CHK_EN_MASK

#define XSDPS_CMD_CRC_CHK_EN_MASK   0x00000008U

#include <xsdps_hw.h>

Command CRC Check Enable.

◆ XSDPS_CMD_INX_CHK_EN_MASK

#define XSDPS_CMD_INX_CHK_EN_MASK   0x00000010U

#include <xsdps_hw.h>

Command Index Check Enable.

◆ XSDPS_CMD_MASK

#define XSDPS_CMD_MASK   0x00003F00U

#include <xsdps_hw.h>

Command Index Mask - Set to CMD0-63, AMCD0-63.

◆ XSDPS_CMD_OFFSET

#define XSDPS_CMD_OFFSET   0x0EU

#include <xsdps_hw.h>

Command Register.

◆ XSDPS_CMD_RESP_L136_MASK

#define XSDPS_CMD_RESP_L136_MASK   0x00000001U

#include <xsdps_hw.h>

Response length 138.

◆ XSDPS_CMD_RESP_L48_BSY_CHK_MASK

#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK   0x00000003U

#include <xsdps_hw.h>

Response length 48 & check busy after response.

◆ XSDPS_CMD_RESP_L48_MASK

#define XSDPS_CMD_RESP_L48_MASK   0x00000002U

#include <xsdps_hw.h>

Response length 48.

◆ XSDPS_CMD_RESP_NONE_MASK

#define XSDPS_CMD_RESP_NONE_MASK   0x00000000U

#include <xsdps_hw.h>

No Response.

◆ XSDPS_CMD_RESP_SEL_MASK

#define XSDPS_CMD_RESP_SEL_MASK   0x00000003U

#include <xsdps_hw.h>

Response Type Select.

◆ XSDPS_CMD_TYPE_ABORT_MASK

#define XSDPS_CMD_TYPE_ABORT_MASK   0x000000C0U

#include <xsdps_hw.h>

CMD Type - Abort.

◆ XSDPS_CMD_TYPE_MASK

#define XSDPS_CMD_TYPE_MASK   0x000000C0U

#include <xsdps_hw.h>

Command Type.

◆ XSDPS_CMD_TYPE_NORM_MASK

#define XSDPS_CMD_TYPE_NORM_MASK   0x00000000U

#include <xsdps_hw.h>

CMD Type - Normal.

◆ XSDPS_CMD_TYPE_RESUME_MASK

#define XSDPS_CMD_TYPE_RESUME_MASK   0x00000080U

#include <xsdps_hw.h>

CMD Type - Resume.

◆ XSDPS_CMD_TYPE_SUSPEND_MASK

#define XSDPS_CMD_TYPE_SUSPEND_MASK   0x00000040U

#include <xsdps_hw.h>

CMD Type - Suspend.

◆ XSDPS_CT_ERROR

#define XSDPS_CT_ERROR   0x2U

#include <xsdps.h>

Command timeout flag.

◆ XSDPS_DAT_PRESENT_SEL_MASK

#define XSDPS_DAT_PRESENT_SEL_MASK   0x00000020U

#include <xsdps_hw.h>

Data Present Select.

◆ XSDPS_ECAPS_CLK_MULT_MASK

#define XSDPS_ECAPS_CLK_MULT_MASK   0x00FF0000U

#include <xsdps_hw.h>

Clock Multiplier value for Programmable clock mode.

◆ XSDPS_ECAPS_DDR50_MASK

#define XSDPS_ECAPS_DDR50_MASK   0x00000004U

#include <xsdps_hw.h>

DDR50 Mode support.

◆ XSDPS_ECAPS_DRV_TYPE_A_MASK

#define XSDPS_ECAPS_DRV_TYPE_A_MASK   0x00000010U

#include <xsdps_hw.h>

DriverType A support.

◆ XSDPS_ECAPS_DRV_TYPE_C_MASK

#define XSDPS_ECAPS_DRV_TYPE_C_MASK   0x00000020U

#include <xsdps_hw.h>

DriverType C support.

◆ XSDPS_ECAPS_DRV_TYPE_D_MASK

#define XSDPS_ECAPS_DRV_TYPE_D_MASK   0x00000040U

#include <xsdps_hw.h>

DriverType D support.

◆ XSDPS_ECAPS_RE_TNG_MODE1_MASK

#define XSDPS_ECAPS_RE_TNG_MODE1_MASK   0x00000000U

#include <xsdps_hw.h>

Re-tuning mode 1.

◆ XSDPS_ECAPS_RE_TNG_MODE2_MASK

#define XSDPS_ECAPS_RE_TNG_MODE2_MASK   0x00004000U

#include <xsdps_hw.h>

Re-tuning mode 2.

◆ XSDPS_ECAPS_RE_TNG_MODE3_MASK

#define XSDPS_ECAPS_RE_TNG_MODE3_MASK   0x00008000U

#include <xsdps_hw.h>

Re-tuning mode 3.

◆ XSDPS_ECAPS_RE_TNG_MODES_MASK

#define XSDPS_ECAPS_RE_TNG_MODES_MASK   0x0000C000U

#include <xsdps_hw.h>

Re-tuning modes support.

◆ XSDPS_ECAPS_SDR104_MASK

#define XSDPS_ECAPS_SDR104_MASK   0x00000002U

#include <xsdps_hw.h>

SDR104 Mode support.

◆ XSDPS_ECAPS_SDR50_MASK

#define XSDPS_ECAPS_SDR50_MASK   0x00000001U

#include <xsdps_hw.h>

SDR50 Mode support.

◆ XSDPS_ECAPS_SPI_BLK_MODE_MASK

#define XSDPS_ECAPS_SPI_BLK_MODE_MASK   0x02000000U

#include <xsdps_hw.h>

SPI block mode.

◆ XSDPS_ECAPS_SPI_MODE_MASK

#define XSDPS_ECAPS_SPI_MODE_MASK   0x01000000U

#include <xsdps_hw.h>

SPI mode.

◆ XSDPS_ECAPS_TMR_CNT_MASK

#define XSDPS_ECAPS_TMR_CNT_MASK   0x00000F00U

#include <xsdps_hw.h>

Timer Count for Re-tuning.

◆ XSDPS_ECAPS_USE_TNG_SDR50_MASK

#define XSDPS_ECAPS_USE_TNG_SDR50_MASK   0x00002000U

#include <xsdps_hw.h>

SDR50 Mode needs tuning.

◆ XSDPS_ERR_INTR_SIG_EN_OFFSET

#define XSDPS_ERR_INTR_SIG_EN_OFFSET   0x3AU

#include <xsdps_hw.h>

Error Interrupt Signal Enable Register.

◆ XSDPS_ERR_INTR_STS_EN_OFFSET

#define XSDPS_ERR_INTR_STS_EN_OFFSET   0x36U

#include <xsdps_hw.h>

Error Interrupt Status Enable Register.

◆ XSDPS_ERR_INTR_STS_OFFSET

#define XSDPS_ERR_INTR_STS_OFFSET   0x32U

#include <xsdps_hw.h>

Error Interrupt Status Register.

◆ XSDPS_ERROR_INTR_ALL_MASK

#define XSDPS_ERROR_INTR_ALL_MASK   0x0000F3FFU

#include <xsdps_hw.h>

Mask for error bits.

◆ XSDPS_FE_AUTO_CMD12_EIS_OFFSET

#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET   0x50U

#include <xsdps_hw.h>

Auto CM12 Error Interrupt Status Register.

◆ XSDPS_FE_AUTO_CMD12_NT_EX_MASK

#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK   0x0001U

#include <xsdps_hw.h>

Auto CMD12 Not executed.

◆ XSDPS_FE_AUTO_CMD_CNI_ERR_MASK

#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK   0x0080U

#include <xsdps_hw.h>

Command not issued by Auto CMD12 Error.

◆ XSDPS_FE_AUTO_CMD_CRC_MASK

#define XSDPS_FE_AUTO_CMD_CRC_MASK   0x0004U

#include <xsdps_hw.h>

Auto CMD CRC Error.

◆ XSDPS_FE_AUTO_CMD_EB_MASK

#define XSDPS_FE_AUTO_CMD_EB_MASK   0x0008U

#include <xsdps_hw.h>

Auto CMD End Bit Error.

◆ XSDPS_FE_AUTO_CMD_IND_MASK

#define XSDPS_FE_AUTO_CMD_IND_MASK   0x0010U

#include <xsdps_hw.h>

Auto CMD Index Error.

◆ XSDPS_FE_AUTO_CMD_TOUT_MASK

#define XSDPS_FE_AUTO_CMD_TOUT_MASK   0x0002U

#include <xsdps_hw.h>

Auto CMD Timeout Error.

◆ XSDPS_FE_ERR_INT_STS_OFFSET

#define XSDPS_FE_ERR_INT_STS_OFFSET   0x52U

#include <xsdps_hw.h>

Force Event for Error Interrupt Status.

◆ XSDPS_FE_INTR_ERR_ADMA_MASK

#define XSDPS_FE_INTR_ERR_ADMA_MASK   0x0200U

#include <xsdps_hw.h>

ADMA Error.

◆ XSDPS_FE_INTR_ERR_AUTO_CMD_MASK

#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK   0x0100U

#include <xsdps_hw.h>

Auto CMD Error.

◆ XSDPS_FE_INTR_ERR_CCRC_MASK

#define XSDPS_FE_INTR_ERR_CCRC_MASK   0x0002U

#include <xsdps_hw.h>

Command CRC Error.

◆ XSDPS_FE_INTR_ERR_CEB_MASK

#define XSDPS_FE_INTR_ERR_CEB_MASK   0x0004U

#include <xsdps_hw.h>

Command End Bit Error.

◆ XSDPS_FE_INTR_ERR_CI_MASK

#define XSDPS_FE_INTR_ERR_CI_MASK   0x0008U

#include <xsdps_hw.h>

Command Index Error.

◆ XSDPS_FE_INTR_ERR_CT_MASK

#define XSDPS_FE_INTR_ERR_CT_MASK   0x0001U

#include <xsdps_hw.h>

Command Timeout Error.

◆ XSDPS_FE_INTR_ERR_CUR_LMT_MASK

#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK   0x0080U

#include <xsdps_hw.h>

Current Limit Error.

◆ XSDPS_FE_INTR_ERR_DCRC_MASK

#define XSDPS_FE_INTR_ERR_DCRC_MASK   0x0020U

#include <xsdps_hw.h>

Data CRC Error.

◆ XSDPS_FE_INTR_ERR_DEB_MASK

#define XSDPS_FE_INTR_ERR_DEB_MASK   0x0040U

#include <xsdps_hw.h>

Data End Bit Error.

◆ XSDPS_FE_INTR_ERR_DT_MASK

#define XSDPS_FE_INTR_ERR_DT_MASK   0x0010U

#include <xsdps_hw.h>

Data Timeout Error.

◆ XSDPS_FE_INTR_ERR_TR_MASK

#define XSDPS_FE_INTR_ERR_TR_MASK   0x1000U

#include <xsdps_hw.h>

Target Reponse.

◆ XSDPS_FE_INTR_VEND_SPF_ERR_MASK

#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK   0xE000U

#include <xsdps_hw.h>

Vendor Specific Error.

◆ XSDPS_HC2_1V8_EN_MASK

#define XSDPS_HC2_1V8_EN_MASK   0x0008U

#include <xsdps_hw.h>

1.8V Signal Enable

◆ XSDPS_HC2_ASYNC_INTR_EN_MASK

#define XSDPS_HC2_ASYNC_INTR_EN_MASK   0x4000U

#include <xsdps_hw.h>

Asynchronous Interrupt Enable.

◆ XSDPS_HC2_DRV_STR_A_MASK

#define XSDPS_HC2_DRV_STR_A_MASK   0x0010U

#include <xsdps_hw.h>

Driver Strength A.

◆ XSDPS_HC2_DRV_STR_B_MASK

#define XSDPS_HC2_DRV_STR_B_MASK   0x0000U

#include <xsdps_hw.h>

Driver Strength B.

◆ XSDPS_HC2_DRV_STR_C_MASK

#define XSDPS_HC2_DRV_STR_C_MASK   0x0020U

#include <xsdps_hw.h>

Driver Strength C.

◆ XSDPS_HC2_DRV_STR_D_MASK

#define XSDPS_HC2_DRV_STR_D_MASK   0x0030U

#include <xsdps_hw.h>

Driver Strength D.

◆ XSDPS_HC2_DRV_STR_SEL_MASK

#define XSDPS_HC2_DRV_STR_SEL_MASK   0x0030U

#include <xsdps_hw.h>

Driver Strength Selection.

◆ XSDPS_HC2_EXEC_TNG_MASK

#define XSDPS_HC2_EXEC_TNG_MASK   0x0040U

#include <xsdps_hw.h>

Execute Tuning.

◆ XSDPS_HC2_PRE_VAL_EN_MASK

#define XSDPS_HC2_PRE_VAL_EN_MASK   0x8000U

#include <xsdps_hw.h>

Preset Value Enable.

◆ XSDPS_HC2_SAMP_CLK_SEL_MASK

#define XSDPS_HC2_SAMP_CLK_SEL_MASK   0x0080U

#include <xsdps_hw.h>

Sampling Clock Selection.

◆ XSDPS_HC2_UHS_MODE_DDR50_MASK

#define XSDPS_HC2_UHS_MODE_DDR50_MASK   0x0004U

#include <xsdps_hw.h>

DDR50 UHS Mode.

◆ XSDPS_HC2_UHS_MODE_MASK

#define XSDPS_HC2_UHS_MODE_MASK   0x0007U

#include <xsdps_hw.h>

UHS Mode select bits.

◆ XSDPS_HC2_UHS_MODE_SDR104_MASK

#define XSDPS_HC2_UHS_MODE_SDR104_MASK   0x0003U

#include <xsdps_hw.h>

SDR104 UHS Mode.

◆ XSDPS_HC2_UHS_MODE_SDR12_MASK

#define XSDPS_HC2_UHS_MODE_SDR12_MASK   0x0000U

#include <xsdps_hw.h>

SDR12 UHS Mode.

◆ XSDPS_HC2_UHS_MODE_SDR25_MASK

#define XSDPS_HC2_UHS_MODE_SDR25_MASK   0x0001U

#include <xsdps_hw.h>

SDR25 UHS Mode.

◆ XSDPS_HC2_UHS_MODE_SDR50_MASK

#define XSDPS_HC2_UHS_MODE_SDR50_MASK   0x0002U

#include <xsdps_hw.h>

SDR50 UHS Mode.

◆ XSDPS_HC_CARD_DET_SD_MASK

#define XSDPS_HC_CARD_DET_SD_MASK   0x00000080U

#include <xsdps_hw.h>

Card Detect Sig Det.

◆ XSDPS_HC_CARD_DET_TL_MASK

#define XSDPS_HC_CARD_DET_TL_MASK   0x00000040U

#include <xsdps_hw.h>

Card Detect Tst Lvl.

◆ XSDPS_HC_DMA_ADMA1_MASK

#define XSDPS_HC_DMA_ADMA1_MASK   0x00000008U

#include <xsdps_hw.h>

ADMA1 Mode.

◆ XSDPS_HC_DMA_ADMA2_32_MASK

#define XSDPS_HC_DMA_ADMA2_32_MASK   0x00000010U

#include <xsdps_hw.h>

ADMA2 Mode - 32 bit.

◆ XSDPS_HC_DMA_ADMA2_64_MASK

#define XSDPS_HC_DMA_ADMA2_64_MASK   0x00000018U

#include <xsdps_hw.h>

ADMA2 Mode - 64 bit.

◆ XSDPS_HC_DMA_MASK

#define XSDPS_HC_DMA_MASK   0x00000018U

#include <xsdps_hw.h>

DMA Mode Select.

◆ XSDPS_HC_DMA_SDMA_MASK

#define XSDPS_HC_DMA_SDMA_MASK   0x00000000U

#include <xsdps_hw.h>

SDMA Mode.

◆ XSDPS_HC_EXT_BUS_WIDTH

#define XSDPS_HC_EXT_BUS_WIDTH   0x00000020U

#include <xsdps_hw.h>

Bus width - 8 bit.

◆ XSDPS_HC_LED_MASK

#define XSDPS_HC_LED_MASK   0x00000001U

#include <xsdps_hw.h>

LED Control.

◆ XSDPS_HC_SPEC_VER_MASK

#define XSDPS_HC_SPEC_VER_MASK   0x00FFU

#include <xsdps_hw.h>

Host Specification version mask.

◆ XSDPS_HC_SPEED_MASK

#define XSDPS_HC_SPEED_MASK   0x00000004U

#include <xsdps_hw.h>

High Speed.

◆ XSDPS_HC_VENDOR_VER

#define XSDPS_HC_VENDOR_VER   0xFF00U

#include <xsdps_hw.h>

Vendor Specification version mask.

◆ XSDPS_HC_WIDTH_MASK

#define XSDPS_HC_WIDTH_MASK   0x00000002U

#include <xsdps_hw.h>

Bus width.

◆ XSDPS_HOST_CTRL1_OFFSET

#define XSDPS_HOST_CTRL1_OFFSET   0x28U

#include <xsdps_hw.h>

Host Control 1.

◆ XSDPS_HOST_CTRL2_OFFSET

#define XSDPS_HOST_CTRL2_OFFSET   0x3EU

#include <xsdps_hw.h>

Host Control2 Register.

◆ XSDPS_HOST_CTRL_VER_OFFSET

#define XSDPS_HOST_CTRL_VER_OFFSET   0xFEU

#include <xsdps_hw.h>

Host Controller Version Register.

◆ XSDPS_INTR_BGE_MASK

#define XSDPS_INTR_BGE_MASK   0x00000004U

#include <xsdps_hw.h>

Block Gap Event.

◆ XSDPS_INTR_BOOT_ACK_RECV_MASK

#define XSDPS_INTR_BOOT_ACK_RECV_MASK   0x00002000U

#include <xsdps_hw.h>

Boot Ack Recv Interrupt.

◆ XSDPS_INTR_BOOT_TERM_MASK

#define XSDPS_INTR_BOOT_TERM_MASK   0x00004000U

#include <xsdps_hw.h>

Boot Terminate Interrupt.

◆ XSDPS_INTR_BRR_MASK

#define XSDPS_INTR_BRR_MASK   0x00000020U

#include <xsdps_hw.h>

Buffer Read Ready.

◆ XSDPS_INTR_BWR_MASK

#define XSDPS_INTR_BWR_MASK   0x00000010U

#include <xsdps_hw.h>

Buffer Write Ready.

◆ XSDPS_INTR_CARD_INSRT_MASK

#define XSDPS_INTR_CARD_INSRT_MASK   0x00000040U

#include <xsdps_hw.h>

Card Insert.

◆ XSDPS_INTR_CARD_MASK

#define XSDPS_INTR_CARD_MASK   0x00000100U

#include <xsdps_hw.h>

Card Interrupt.

◆ XSDPS_INTR_CARD_REM_MASK

#define XSDPS_INTR_CARD_REM_MASK   0x00000080U

#include <xsdps_hw.h>

Card Remove.

◆ XSDPS_INTR_CC_MASK

#define XSDPS_INTR_CC_MASK   0x00000001U

#include <xsdps_hw.h>

Command Complete.

◆ XSDPS_INTR_DMA_MASK

#define XSDPS_INTR_DMA_MASK   0x00000008U

#include <xsdps_hw.h>

DMA Interrupt.

◆ XSDPS_INTR_ERR_ADMA_MASK

#define XSDPS_INTR_ERR_ADMA_MASK   0x00000200U

#include <xsdps_hw.h>

ADMA Error.

◆ XSDPS_INTR_ERR_AUTO_CMD12_MASK

#define XSDPS_INTR_ERR_AUTO_CMD12_MASK   0x00000100U

#include <xsdps_hw.h>

Auto CMD12 Error.

◆ XSDPS_INTR_ERR_CCRC_MASK

#define XSDPS_INTR_ERR_CCRC_MASK   0x00000002U

#include <xsdps_hw.h>

Command CRC Error.

◆ XSDPS_INTR_ERR_CEB_MASK

#define XSDPS_INTR_ERR_CEB_MASK   0x00000004U

#include <xsdps_hw.h>

Command End Bit Error.

◆ XSDPS_INTR_ERR_CI_MASK

#define XSDPS_INTR_ERR_CI_MASK   0x00000008U

#include <xsdps_hw.h>

Command Index Error.

◆ XSDPS_INTR_ERR_CT_MASK

#define XSDPS_INTR_ERR_CT_MASK   0x00000001U

#include <xsdps_hw.h>

Command Timeout Error.

◆ XSDPS_INTR_ERR_CUR_LMT_MASK

#define XSDPS_INTR_ERR_CUR_LMT_MASK   0x00000080U

#include <xsdps_hw.h>

Current Limit Error.

◆ XSDPS_INTR_ERR_DCRC_MASK

#define XSDPS_INTR_ERR_DCRC_MASK   0x00000020U

#include <xsdps_hw.h>

Data CRC Error.

◆ XSDPS_INTR_ERR_DEB_MASK

#define XSDPS_INTR_ERR_DEB_MASK   0x00000040U

#include <xsdps_hw.h>

Data End Bit Error.

◆ XSDPS_INTR_ERR_DT_MASK

#define XSDPS_INTR_ERR_DT_MASK   0x00000010U

#include <xsdps_hw.h>

Data Timeout Error.

◆ XSDPS_INTR_ERR_MASK

#define XSDPS_INTR_ERR_MASK   0x00008000U

#include <xsdps_hw.h>

Error Interrupt.

◆ XSDPS_INTR_ERR_TR_MASK

#define XSDPS_INTR_ERR_TR_MASK   0x00001000U

#include <xsdps_hw.h>

Tuning Error.

◆ XSDPS_INTR_INT_A_MASK

#define XSDPS_INTR_INT_A_MASK   0x00000200U

#include <xsdps_hw.h>

INT A Interrupt.

◆ XSDPS_INTR_INT_B_MASK

#define XSDPS_INTR_INT_B_MASK   0x00000400U

#include <xsdps_hw.h>

INT B Interrupt.

◆ XSDPS_INTR_INT_C_MASK

#define XSDPS_INTR_INT_C_MASK   0x00000800U

#include <xsdps_hw.h>

INT C Interrupt.

◆ XSDPS_INTR_RE_TUNING_MASK

#define XSDPS_INTR_RE_TUNING_MASK   0x00001000U

#include <xsdps_hw.h>

Re-Tuning Interrupt.

◆ XSDPS_INTR_TC_MASK

#define XSDPS_INTR_TC_MASK   0x00000002U

#include <xsdps_hw.h>

Transfer Complete.

◆ XSDPS_INTR_VEND_SPF_ERR_MASK

#define XSDPS_INTR_VEND_SPF_ERR_MASK   0x0000E000U

#include <xsdps_hw.h>

Vendor Specific Error.

◆ XSDPS_MAX_CUR_CAPS_1V8_MASK

#define XSDPS_MAX_CUR_CAPS_1V8_MASK   0x00000F00U

#include <xsdps_hw.h>

Maximum Current Capability at 1.8V.

◆ XSDPS_MAX_CUR_CAPS_3V0_MASK

#define XSDPS_MAX_CUR_CAPS_3V0_MASK   0x000000F0U

#include <xsdps_hw.h>

Maximum Current Capability at 3.0V.

◆ XSDPS_MAX_CUR_CAPS_3V3_MASK

#define XSDPS_MAX_CUR_CAPS_3V3_MASK   0x0000000FU

#include <xsdps_hw.h>

Maximum Current Capability at 3.3V.

◆ XSDPS_MAX_CURR_CAPS_EXT_OFFSET

#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET   0x4CU

#include <xsdps_hw.h>

Maximum Current Capabilities Ext Register.

◆ XSDPS_MAX_CURR_CAPS_OFFSET

#define XSDPS_MAX_CURR_CAPS_OFFSET   0x48U

#include <xsdps_hw.h>

Maximum Current Capabilities Register.

◆ XSDPS_NORM_INTR_SIG_EN_OFFSET

#define XSDPS_NORM_INTR_SIG_EN_OFFSET   0x38U

#include <xsdps_hw.h>

Normal Interrupt Signal Enable Register.

◆ XSDPS_NORM_INTR_STS_EN_OFFSET

#define XSDPS_NORM_INTR_STS_EN_OFFSET   0x34U

#include <xsdps_hw.h>

Normal Interrupt Status Enable Register.

◆ XSDPS_NORM_INTR_STS_OFFSET

#define XSDPS_NORM_INTR_STS_OFFSET   0x30U

#include <xsdps_hw.h>

Normal Interrupt Status Register.

◆ XSDPS_PC_BUS_PWR_MASK

#define XSDPS_PC_BUS_PWR_MASK   0x00000001U

#include <xsdps_hw.h>

Bus Power Control.

◆ XSDPS_PC_BUS_VSEL_1V8_MASK

#define XSDPS_PC_BUS_VSEL_1V8_MASK   0x0000000AU

#include <xsdps_hw.h>

Bus Voltage 1.8V.

◆ XSDPS_PC_BUS_VSEL_3V0_MASK

#define XSDPS_PC_BUS_VSEL_3V0_MASK   0x0000000CU

#include <xsdps_hw.h>

Bus Voltage 3.0V.

◆ XSDPS_PC_BUS_VSEL_3V3_MASK

#define XSDPS_PC_BUS_VSEL_3V3_MASK   0x0000000EU

#include <xsdps_hw.h>

Bus Voltage 3.3V.

◆ XSDPS_PC_BUS_VSEL_MASK

#define XSDPS_PC_BUS_VSEL_MASK   0x0000000EU

#include <xsdps_hw.h>

Bus Voltage Select.

◆ XSDPS_PC_EMMC_HW_RST_MASK

#define XSDPS_PC_EMMC_HW_RST_MASK   0x00000010U

#include <xsdps_hw.h>

HW reset for eMMC.

◆ XSDPS_POWER_CTRL_OFFSET

#define XSDPS_POWER_CTRL_OFFSET   0x29U

#include <xsdps_hw.h>

Power Control.

◆ XSDPS_PRE_VAL_1_OFFSET

#define XSDPS_PRE_VAL_1_OFFSET   0x60U

#include <xsdps_hw.h>

Preset Value Register.

◆ XSDPS_PRE_VAL_2_OFFSET

#define XSDPS_PRE_VAL_2_OFFSET   0x64U

#include <xsdps_hw.h>

Preset Value Register.

◆ XSDPS_PRE_VAL_3_OFFSET

#define XSDPS_PRE_VAL_3_OFFSET   0x68U

#include <xsdps_hw.h>

Preset Value Register.

◆ XSDPS_PRE_VAL_4_OFFSET

#define XSDPS_PRE_VAL_4_OFFSET   0x6CU

#include <xsdps_hw.h>

Preset Value Register.

◆ XSDPS_PRE_VAL_CLK_GEN_SEL_MASK

#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK   0x0400U

#include <xsdps_hw.h>

Clock Generator Mode Select.

◆ XSDPS_PRE_VAL_DRV_STR_SEL_MASK

#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK   0xC000U

#include <xsdps_hw.h>

Driver Strength Select Value.

◆ XSDPS_PRE_VAL_SDCLK_FSEL_MASK

#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK   0x03FFU

#include <xsdps_hw.h>

SDCLK Frequency Select Value.

◆ XSDPS_PRES_STATE_OFFSET

#define XSDPS_PRES_STATE_OFFSET   0x24U

#include <xsdps_hw.h>

Present State.

Referenced by XSdPs_CmdTransfer(), and XSdPs_SetBlkSize().

◆ XSDPS_PSR_BUFF_RD_EN_MASK

#define XSDPS_PSR_BUFF_RD_EN_MASK   0x00000800U

#include <xsdps_hw.h>

Buffer read enable.

◆ XSDPS_PSR_BUFF_WR_EN_MASK

#define XSDPS_PSR_BUFF_WR_EN_MASK   0x00000400U

#include <xsdps_hw.h>

Buffer write enable.

◆ XSDPS_PSR_CARD_DPL_MASK

#define XSDPS_PSR_CARD_DPL_MASK   0x00040000U

#include <xsdps_hw.h>

Card detect pin level.

◆ XSDPS_PSR_CARD_INSRT_MASK

#define XSDPS_PSR_CARD_INSRT_MASK   0x00010000U

#include <xsdps_hw.h>

Card inserted.

◆ XSDPS_PSR_CARD_STABLE_MASK

#define XSDPS_PSR_CARD_STABLE_MASK   0x00020000U

#include <xsdps_hw.h>

Card state stable.

◆ XSDPS_PSR_CMD_SG_LVL_MASK

#define XSDPS_PSR_CMD_SG_LVL_MASK   0x01000000U

#include <xsdps_hw.h>

Cmd Line signal lvl.

◆ XSDPS_PSR_DAT30_SG_LVL_MASK

#define XSDPS_PSR_DAT30_SG_LVL_MASK   0x00F00000U

#include <xsdps_hw.h>

Data 3:0 signal lvl.

◆ XSDPS_PSR_DAT74_SG_LVL_MASK

#define XSDPS_PSR_DAT74_SG_LVL_MASK   0x1E000000U

#include <xsdps_hw.h>

Data 7:4 signal lvl.

◆ XSDPS_PSR_DAT_ACTIVE_MASK

#define XSDPS_PSR_DAT_ACTIVE_MASK   0x00000004U

#include <xsdps_hw.h>

DAT line active.

◆ XSDPS_PSR_INHIBIT_CMD_MASK

#define XSDPS_PSR_INHIBIT_CMD_MASK   0x00000001U

#include <xsdps_hw.h>

Command inhibit - CMD.

Referenced by XSdPs_CmdTransfer(), and XSdPs_SetBlkSize().

◆ XSDPS_PSR_INHIBIT_DAT_MASK

#define XSDPS_PSR_INHIBIT_DAT_MASK   0x00000002U

#include <xsdps_hw.h>

Command Inhibit - DAT.

Referenced by XSdPs_SetBlkSize().

◆ XSDPS_PSR_RD_ACTIVE_MASK

#define XSDPS_PSR_RD_ACTIVE_MASK   0x00000200U

#include <xsdps_hw.h>

Read transfer active.

Referenced by XSdPs_SetBlkSize().

◆ XSDPS_PSR_RE_TUNING_REQ_MASK

#define XSDPS_PSR_RE_TUNING_REQ_MASK   0x00000008U

#include <xsdps_hw.h>

Re-tuning request.

◆ XSDPS_PSR_WPS_PL_MASK

#define XSDPS_PSR_WPS_PL_MASK   0x00080000U

#include <xsdps_hw.h>

Write protect switch pin level.

◆ XSDPS_PSR_WR_ACTIVE_MASK

#define XSDPS_PSR_WR_ACTIVE_MASK   0x00000100U

#include <xsdps_hw.h>

Write transfer active.

Referenced by XSdPs_SetBlkSize().

◆ XSDPS_RESP0_OFFSET

#define XSDPS_RESP0_OFFSET   0x10U

#include <xsdps_hw.h>

Response0 Register.

◆ XSDPS_RESP1_OFFSET

#define XSDPS_RESP1_OFFSET   0x14U

#include <xsdps_hw.h>

Response1 Register.

◆ XSDPS_RESP2_OFFSET

#define XSDPS_RESP2_OFFSET   0x18U

#include <xsdps_hw.h>

Response2 Register.

◆ XSDPS_RESP3_OFFSET

#define XSDPS_RESP3_OFFSET   0x1CU

#include <xsdps_hw.h>

Response3 Register.

◆ XSDPS_SDMA_BUFF_SIZE_MASK

#define XSDPS_SDMA_BUFF_SIZE_MASK   0x00007000U

#include <xsdps_hw.h>

Host SDMA Buffer Size.

◆ XSDPS_SDMA_SYS_ADDR_HI_OFFSET

#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET   0x02U

#include <xsdps_hw.h>

SDMA System Address High Register.

◆ XSDPS_SDMA_SYS_ADDR_LO_OFFSET

#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET   XSDPS_SDMA_SYS_ADDR_OFFSET

#include <xsdps_hw.h>

SDMA System Address Low Register.

◆ XSDPS_SDMA_SYS_ADDR_OFFSET

#define XSDPS_SDMA_SYS_ADDR_OFFSET   0x00U

#include <xsdps_hw.h>

SDMA System Address Register.

◆ XSDPS_SHARED_BUS_CTRL_OFFSET

#define XSDPS_SHARED_BUS_CTRL_OFFSET   0xE0U

#include <xsdps_hw.h>

Shared Bus Control Register.

◆ XSDPS_SLOT_INTR_STS_INT_MASK

#define XSDPS_SLOT_INTR_STS_INT_MASK   0x0007U

#include <xsdps_hw.h>

Interrupt Signal mask.

◆ XSDPS_SLOT_INTR_STS_OFFSET

#define XSDPS_SLOT_INTR_STS_OFFSET   0xFCU

#include <xsdps_hw.h>

Slot Interrupt Status Register.

◆ XSDPS_SW_RST_OFFSET

#define XSDPS_SW_RST_OFFSET   0x2FU

#include <xsdps_hw.h>

Software Reset.

◆ XSDPS_TIMEOUT_CTRL_OFFSET

#define XSDPS_TIMEOUT_CTRL_OFFSET   0x2EU

#include <xsdps_hw.h>

Timeout Control.

◆ XSDPS_TM_AUTO_CMD12_EN_MASK

#define XSDPS_TM_AUTO_CMD12_EN_MASK   0x00000004U

#include <xsdps_hw.h>

Auto CMD12 Enable.

◆ XSDPS_TM_BLK_CNT_EN_MASK

#define XSDPS_TM_BLK_CNT_EN_MASK   0x00000002U

#include <xsdps_hw.h>

Block Count Enable.

◆ XSDPS_TM_DAT_DIR_SEL_MASK

#define XSDPS_TM_DAT_DIR_SEL_MASK   0x00000010U

#include <xsdps_hw.h>

Data Transfer Direction Select.

◆ XSDPS_TM_DMA_EN_MASK

#define XSDPS_TM_DMA_EN_MASK   0x00000001U

#include <xsdps_hw.h>

DMA Enable.

◆ XSDPS_TM_MUL_SIN_BLK_SEL_MASK

#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK   0x00000020U

#include <xsdps_hw.h>

Multi/Single Block Select.

◆ XSDPS_WAKE_UP_CTRL_OFFSET

#define XSDPS_WAKE_UP_CTRL_OFFSET   0x2BU

#include <xsdps_hw.h>

Wake Up Control.

◆ XSDPS_WC_WUP_ON_INSRT_MASK

#define XSDPS_WC_WUP_ON_INSRT_MASK   0x00000002U

#include <xsdps_hw.h>

Wakeup Card Insert.

◆ XSDPS_WC_WUP_ON_INTR_MASK

#define XSDPS_WC_WUP_ON_INTR_MASK   0x00000001U

#include <xsdps_hw.h>

Wakeup Card Intr.

◆ XSDPS_WC_WUP_ON_REM_MASK

#define XSDPS_WC_WUP_ON_REM_MASK   0x00000004U

#include <xsdps_hw.h>

Wakeup Card Removal.

◆ XSDPS_XFER_MODE_OFFSET

#define XSDPS_XFER_MODE_OFFSET   0x0CU

#include <xsdps_hw.h>

Transfer Mode Register.

Function Documentation

◆ XSdPs_CardInitialize()

s32 XSdPs_CardInitialize ( XSdPs InstancePtr)

#include <xsdps.c>

Initialize Card with Identification mode sequence.

Parameters
InstancePtris a pointer to the instance to be worked on.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because a) SD is already initialized b) There is no card inserted c) One of the steps (commands) in the initialization cycle failed

References XSdPs::BusWidth, and XSdPs::IsReady.

◆ XSdPs_CfgInitialize()

s32 XSdPs_CfgInitialize ( XSdPs InstancePtr,
XSdPs_Config ConfigPtr,
u32  EffectiveAddr 
)

#include <xsdps.c>

Initializes a specific XSdPs instance such that the driver is ready to use.

Parameters
InstancePtris a pointer to the XSdPs instance.
ConfigPtris a reference to a structure containing information about a specific SD device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddris the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.
Returns
  • XST_SUCCESS if successful.
  • XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.
Note
This function initializes the host controller. Initial clock of 400KHz is set. Voltage of 3.3V is selected as that is supported by host. Interrupts status is enabled and signal disabled by default. Default data direction is card to host and 32 bit ADMA2 is selected. Defualt Block size is 512 bytes.

References XSdPs_Config::BaseAddress, XSdPs_Config::BusWidth, XSdPs_Config::CardDetect, XSdPs::Config, XSdPs_Config::DeviceId, XSdPs_Config::InputClockHz, XSdPs::IsReady, and XSdPs_Config::WriteProtect.

◆ XSdPs_Change_BusSpeed()

s32 XSdPs_Change_BusSpeed ( XSdPs InstancePtr)

#include <xsdps.h>

API to set high speed in card and host.

Changes clock in host accordingly.

Parameters
InstancePtris a pointer to the XSdPs instance.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::CardType, and XSdPs::IsReady.

◆ XSdPs_Change_BusWidth()

s32 XSdPs_Change_BusWidth ( XSdPs InstancePtr)

#include <xsdps.h>

API to set bus width to 4-bit in card and host.

Parameters
InstancePtris a pointer to the XSdPs instance.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::HC_Version, and XSdPs::IsReady.

◆ XSdPs_Change_ClkFreq()

s32 XSdPs_Change_ClkFreq ( XSdPs InstancePtr,
u32  SelFreq 
)

#include <xsdps.h>

API to change clock freq to given value.

Parameters
InstancePtris a pointer to the XSdPs instance.
SelFreq- Clock frequency in Hz.
Returns
None
Note
This API will change clock frequency to the value less than or equal to the given value using the permissible dividors.

References XSdPs::IsReady.

◆ XSdPs_CmdTransfer()

s32 XSdPs_CmdTransfer ( XSdPs InstancePtr,
u32  Cmd,
u32  Arg,
u32  BlkCnt 
)

#include <xsdps.c>

This function does SD command generation.

Parameters
InstancePtris a pointer to the instance to be worked on.
Cmdis the command to be sent.
Argis the argument to be sent along with the command. This could be address or any other information
BlkCnt- Block count passed by the user.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because another transfer is in progress or command or data inhibit is set

References XSdPs_Config::BaseAddress, XSdPs::Config, XSdPs::IsReady, XSDPS_PRES_STATE_OFFSET, XSDPS_PSR_INHIBIT_CMD_MASK, and XSdPs_ReadReg.

Referenced by XSdPs_Get_BusWidth(), XSdPs_Pullup(), XSdPs_Select_Card(), XSdPs_Set_Mmc_ExtCsd(), and XSdPs_SetBlkSize().

◆ XSdPs_FrameCmd()

u32 XSdPs_FrameCmd ( XSdPs InstancePtr,
u32  Cmd 
)

#include <xsdps.c>

This function frames the Command register for a particular command.

Note that this generates only the command register value i.e. the upper 16 bits of the transfer mode and command register. This value is already shifted to be upper 16 bits and can be directly OR'ed with transfer mode register value.

Parameters
Commandto be sent.
Returns
Command register value complete with response type and data, CRC and index related flags.

◆ XSdPs_Get_BusSpeed()

s32 XSdPs_Get_BusSpeed ( XSdPs InstancePtr,
u8 *  ReadBuff 
)

#include <xsdps.h>

API to get bus speed supported by card.

Parameters
InstancePtris a pointer to the XSdPs instance.
ReadBuff- buffer to store function group support data returned by card.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::IsReady.

◆ XSdPs_Get_BusWidth()

s32 XSdPs_Get_BusWidth ( XSdPs InstancePtr,
u8 *  SCR 
)

#include <xsdps.h>

API to get bus width support by card.

Parameters
InstancePtris a pointer to the XSdPs instance.
SCR- buffer to store SCR register returned by card.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::IsReady, and XSdPs_CmdTransfer().

◆ XSdPs_Get_Mmc_ExtCsd()

s32 XSdPs_Get_Mmc_ExtCsd ( XSdPs InstancePtr,
u8 *  ReadBuff 
)

#include <xsdps.h>

API to get EXT_CSD register of eMMC.

Parameters
InstancePtris a pointer to the XSdPs instance.
ReadBuff- buffer to store EXT_CSD
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::IsReady.

◆ XSdPs_LookupConfig()

XSdPs_Config * XSdPs_LookupConfig ( u16  DeviceId)

#include <xsdps.h>

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters
DeviceIdcontains the ID of the device to look up the configuration for.
Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xsdps.h for the definition of XSdPs_Config.

Note
None.

◆ XSdPs_MmcCardInitialize()

s32 XSdPs_MmcCardInitialize ( XSdPs InstancePtr)

#include <xsdps.c>

Mmc initialization is done in this function.

Parameters
InstancePtris a pointer to the instance to be worked on.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because a) MMC is already initialized b) There is no card inserted c) One of the steps (commands) in the initialization cycle failed
Note
This function initializes the SD card by following its initialization and identification state diagram. CMD0 is sent to reset card. CMD1 sent to identify voltage and high capacity support CMD2 and CMD3 are sent to obtain Card ID and Relative card address respectively. CMD9 is sent to read the card specific data.

References XSdPs::HC_Version, and XSdPs::IsReady.

◆ XSdPs_Pullup()

s32 XSdPs_Pullup ( XSdPs InstancePtr)

#include <xsdps.h>

API to send pullup command to card before using DAT line 3(using 4-bit bus)

Parameters
InstancePtris a pointer to the XSdPs instance.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs::IsReady, and XSdPs_CmdTransfer().

◆ XSdPs_ReadPolled()

s32 XSdPs_ReadPolled ( XSdPs InstancePtr,
u32  Arg,
u32  BlkCnt,
u8 *  Buff 
)

#include <xsdps.c>

This function performs SD read in polled mode.

Parameters
InstancePtris a pointer to the instance to be worked on.
Argis the address passed by the user that is to be sent as argument along with the command.
BlkCnt- Block count passed by the user.
Buff- Pointer to the data buffer for a DMA transfer.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because another transfer is in progress or command or data inhibit is set

References XSdPs::HC_Version.

◆ XSdPs_SdCardInitialize()

s32 XSdPs_SdCardInitialize ( XSdPs InstancePtr)

#include <xsdps.c>

SD initialization is done in this function.

Parameters
InstancePtris a pointer to the instance to be worked on.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because a) SD is already initialized b) There is no card inserted c) One of the steps (commands) in the initialization cycle failed
Note
This function initializes the SD card by following its initialization and identification state diagram. CMD0 is sent to reset card. CMD8 and ACDM41 are sent to identify voltage and high capacity support CMD2 and CMD3 are sent to obtain Card ID and Relative card address respectively. CMD9 is sent to read the card specific data.

References XSdPs::HC_Version, and XSdPs::IsReady.

◆ XSdPs_Select_Card()

s32 XSdPs_Select_Card ( XSdPs InstancePtr)

#include <xsdps.c>

Selects card and sets default block size.

Parameters
InstancePtris a pointer to the XSdPs instance.
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs_CmdTransfer().

◆ XSdPs_Set_Mmc_ExtCsd()

s32 XSdPs_Set_Mmc_ExtCsd ( XSdPs InstancePtr,
u32  Arg 
)

#include <xsdps.h>

API to write EXT_CSD register of eMMC.

Parameters
InstancePtris a pointer to the XSdPs instance.
Argis the argument to be sent along with the command
Returns
  • XST_SUCCESS if successful.
  • XST_FAILURE if fail.
Note
None.

References XSdPs_CmdTransfer().

◆ XSdPs_SetBlkSize()

s32 XSdPs_SetBlkSize ( XSdPs InstancePtr,
u16  BlkSize 
)

#include <xsdps.h>

Update Block size for read/write operations.

Parameters
InstancePtris a pointer to the instance to be worked on.
BlkSize- Block size passed by the user.
Returns
None

References XSdPs_Config::BaseAddress, XSdPs::Config, XSdPs::IsReady, XSdPs_CmdTransfer(), XSDPS_PRES_STATE_OFFSET, XSDPS_PSR_INHIBIT_CMD_MASK, XSDPS_PSR_INHIBIT_DAT_MASK, XSDPS_PSR_RD_ACTIVE_MASK, XSDPS_PSR_WR_ACTIVE_MASK, and XSdPs_ReadReg.

◆ XSdPs_SetupADMA2DescTbl()

void XSdPs_SetupADMA2DescTbl ( XSdPs InstancePtr,
u32  BlkCnt,
const u8 *  Buff 
)

#include <xsdps.c>

API to setup ADMA2 descriptor table.

Parameters
InstancePtris a pointer to the XSdPs instance.
BlkCnt- block count.
Buffpointer to data buffer.
Returns
None
Note
None.

◆ XSdPs_WritePolled()

s32 XSdPs_WritePolled ( XSdPs InstancePtr,
u32  Arg,
u32  BlkCnt,
const u8 *  Buff 
)

#include <xsdps.c>

This function performs SD write in polled mode.

Parameters
InstancePtris a pointer to the instance to be worked on.
Argis the address passed by the user that is to be sent as argument along with the command.
BlkCnt- Block count passed by the user.
Buff- Pointer to the data buffer for a DMA transfer.
Returns
  • XST_SUCCESS if initialization was successful
  • XST_FAILURE if failure - could be because another transfer is in progress or command or data inhibit is set

References XSdPs::HC_Version.