mipicsiss
Xilinx SDK Drivers API Documentation
XCsiSs_Config Struct Reference

MIPI CSI Rx Subsystem configuration structure. More...

Data Fields

u32 DeviceId
 DeviceId is the unique ID of the device. More...
 
UINTPTR BaseAddr
 BaseAddress is the physical base address of the subsystem address range. More...
 
UINTPTR HighAddr
 HighAddress is the physical MAX address of the subsystem address range. More...
 
u32 IsIicPresent
 Flag for IIC presence in subsystem. More...
 
u32 LanesPresent
 Number of PPI Lanes in the design. More...
 
u32 PixelCount
 Number of Pixels per clock 1,2,4. More...
 
u32 PixelFormat
 The pixel format selected from all RGB, RAW and YUV422 8bit options. More...
 
u32 VcNo
 Number of Virtual Channels supported by system. More...
 
u32 CsiBuffDepth
 Line buffer Depth set. More...
 
u32 IsEmbNonImgPresent
 Flag for presence of Embedded Non Image data. More...
 
u32 IsDphyRegIntfcPresent
 Flag for DPHY register interface presence. More...
 
u32 DphyLineRate
 DPHY Line Rate ranging from 80-1500 Mbps. More...
 
u32 EnableCrc
 CRC Calculation optimization enabled. More...
 
u32 EnableActiveLanes
 Active Lanes programming optimization enabled. More...
 
CsiRxSsSubCore IicInfo
 IIC sub-core configuration. More...
 
CsiRxSsSubCore CsiInfo
 CSI sub-core configuration. More...
 
CsiRxSsSubCore DphyInfo
 DPHY sub-core configuration. More...
 

Detailed Description

MIPI CSI Rx Subsystem configuration structure.

Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem

Field Documentation

◆ BaseAddr

UINTPTR XCsiSs_Config::BaseAddr

BaseAddress is the physical base address of the subsystem address range.

Referenced by CsiSs_SelfTestExample(), and XCsiSs_CfgInitialize().

◆ CsiBuffDepth

u32 XCsiSs_Config::CsiBuffDepth

Line buffer Depth set.

◆ CsiInfo

CsiRxSsSubCore XCsiSs_Config::CsiInfo

CSI sub-core configuration.

◆ DeviceId

u32 XCsiSs_Config::DeviceId

DeviceId is the unique ID of the device.

◆ DphyInfo

CsiRxSsSubCore XCsiSs_Config::DphyInfo

DPHY sub-core configuration.

◆ DphyLineRate

u32 XCsiSs_Config::DphyLineRate

DPHY Line Rate ranging from 80-1500 Mbps.

◆ EnableActiveLanes

u32 XCsiSs_Config::EnableActiveLanes

Active Lanes programming optimization enabled.

◆ EnableCrc

u32 XCsiSs_Config::EnableCrc

CRC Calculation optimization enabled.

◆ HighAddr

UINTPTR XCsiSs_Config::HighAddr

HighAddress is the physical MAX address of the subsystem address range.

◆ IicInfo

CsiRxSsSubCore XCsiSs_Config::IicInfo

IIC sub-core configuration.

◆ IsDphyRegIntfcPresent

u32 XCsiSs_Config::IsDphyRegIntfcPresent

Flag for DPHY register interface presence.

Referenced by XCsiSs_Activate(), and XCsiSs_ReportCoreInfo().

◆ IsEmbNonImgPresent

u32 XCsiSs_Config::IsEmbNonImgPresent

Flag for presence of Embedded Non Image data.

◆ IsIicPresent

u32 XCsiSs_Config::IsIicPresent

Flag for IIC presence in subsystem.

◆ LanesPresent

u32 XCsiSs_Config::LanesPresent

Number of PPI Lanes in the design.

Referenced by XCsiSs_GetLaneInfo().

◆ PixelCount

u32 XCsiSs_Config::PixelCount

Number of Pixels per clock 1,2,4.

◆ PixelFormat

u32 XCsiSs_Config::PixelFormat

The pixel format selected from all RGB, RAW and YUV422 8bit options.

◆ VcNo

u32 XCsiSs_Config::VcNo

Number of Virtual Channels supported by system.

This can range from 1 - 4 to ALL