dp
Xilinx SDK Drivers API Documentation
Dp_v6_0

Data Structures

struct  XDp_Config
 This typedef contains configuration information for the DisplayPort core. More...
 
struct  XDp_TxSinkConfig
 This typedef contains configuration information about the RX device. More...
 
struct  XDp_TxLinkConfig
 This typedef contains configuration information about the main link settings. More...
 
struct  XDp_TxMainStreamAttributes
 This typedef contains the main stream attributes which determine how the video will be displayed. More...
 
struct  XDp_TxMstStream
 This typedef describes a stream when the driver is running in multi-stream transport (MST) mode. More...
 
struct  XDp_TxBoardChar
 This typedef describes some board characteristics information that affects link training. More...
 
struct  XDp_TxTopologyNode
 This typedef describes a downstream DisplayPort device when the driver is running in multi-stream transport (MST) mode. More...
 
struct  XDp_TxTopology
 This typedef describes a the entire topology of connected downstream DisplayPort devices (from the DisplayPort TX) when the driver is operating in multi-stream transport (MST) mode. More...
 
struct  XDp_SbMsgLinkAddressReplyPortDetail
 This typedef describes a port that is connected to a DisplayPort branch device. More...
 
struct  XDp_SbMsgLinkAddressReplyDeviceInfo
 This typedef describes a DisplayPort branch device. More...
 
struct  XDp_RxLinkConfig
 This typedef contains configuration information about the main link settings. More...
 
struct  XDp_RxIicMapEntry
 This typedef represents one I2C map entry for a device. More...
 
struct  XDp_RxDpcdMap
 This typedef represents the DPCD address map for a device. More...
 
struct  XDp_RxPort
 This typedef contains information on the directly connected ports to the RX branch. More...
 
struct  XDp_RxTopology
 This typedef contains topology information on directly connected sinks and of the RX branch itself. More...
 
struct  XDp_Tx
 The XDp driver instance data representing the TX mode of operation. More...
 
struct  XDp_Rx
 The XDp driver instance data representing the RX mode of operation. More...
 
struct  XDp
 The XDp instance data. More...
 

Macros

#define XDp_GetCoreType(InstancePtr)
 This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX). More...
 
#define XDp_TxCfgSetRGB(InstancePtr, Stream)
 The following functions set the color encoding scheme for a given stream. More...
 
#define XDP_TX_VC_PAYLOAD_BUFFER_ADDR   0x800
 Virtual channel payload table (0xFF bytes). More...
 
#define XDP_RX_HSYNC_WIDTH   0x050
 Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG). More...
 
#define XDP_RX_VSYNC_WIDTH   0x058
 Controls the timing of the active-high vertical sync pulse generated by the display timing generator (DTG). More...
 
#define XDP_RX_FAST_I2C_DIVIDER   0x060
 Fast I2C mode clock divider value. More...
 
#define XDP_RX_MST_ALLOC   0x06C
 Represents the content from the DPCD registers related to payload allocation. More...
 
#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT   3
 The number of I2C user- defined entries in the I2C map of each port. More...
 
#define XDP_GUID_NBYTES   16
 The number of bytes for the global unique ID. More...
 
#define XDP_MAX_NPORTS   16
 The maximum number of ports connected to a DisplayPort device. More...
 
#define XDp_ReadReg(BaseAddress, RegOffset)   XDp_In32((BaseAddress) + (RegOffset))
 This is a low-level function that reads from the specified register. More...
 
#define XDp_WriteReg(BaseAddress, RegOffset, Data)   XDp_Out32((BaseAddress) + (RegOffset), (Data))
 This is a low-level function that writes to the specified register. More...
 
#define XDp_TxIsEdidExtBlockDispId(Ext)   (Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID)
 Check if an Extended Display Identification Data (EDID) extension block is of type DisplayID. More...
 
#define XDp_TxGetDispIdTdtHTotal(Tdt)
 Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the tiled display. More...
 
#define XDp_TxGetDispIdTdtVTotal(Tdt)
 Given a Tiled Display Topology (TDT) data block, retrieve the total number of vertical tiles in the tiled display. More...
 
#define XDp_TxGetDispIdTdtHLoc(Tdt)
 Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled display. More...
 
#define XDp_TxGetDispIdTdtVLoc(Tdt)
 Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled display. More...
 
#define XDp_TxGetDispIdTdtNumTiles(Tdt)   (XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt))
 Given a Tiled Display Topology (TDT) data block, retrieve the total number of tiles in the tiled display. More...
 
#define XDp_TxGetDispIdTdtTileOrder(Tdt)
 Given a Tiled Display Topology (TDT) data block, calculate the tiling order of the associated tile. More...
 

Typedefs

typedef void(* XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds)
 Callback type which represents a custom timer wait handler. More...
 
typedef void(* XDp_IntrHandler) (void *InstancePtr)
 Callback type which represents the handler for interrupts. More...
 

Enumerations

enum  XDp_TxTrainingState
 This typedef enumerates the list of training states used in the state machine during the link training process. More...
 
enum  XDp_CoreType
 This typedef enumerates the RX and TX modes of operation for the DisplayPort core. More...
 
enum  XDp_DynamicRange
 This typedef enumerates the dynamic ranges available to the DisplayPort core. More...
 

Functions

void XDp_CfgInitialize (XDp *InstancePtr, XDp_Config *ConfigPtr, UINTPTR EffectiveAddr)
 This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure. More...
 
u32 XDp_Initialize (XDp *InstancePtr)
 This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode. More...
 
u32 XDp_TxGetRxCapabilities (XDp *InstancePtr)
 This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD). More...
 
u32 XDp_TxCfgMainLinkMax (XDp *InstancePtr)
 This function determines the common capabilities between the DisplayPort TX core and the RX device. More...
 
u32 XDp_TxEstablishLink (XDp *InstancePtr)
 This function checks if the link needs training and runs the training sequence if training is required. More...
 
u32 XDp_TxCheckLinkStatus (XDp *InstancePtr, u8 LaneCount)
 This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates the receiver has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use. More...
 
void XDp_TxEnableTrainAdaptive (XDp *InstancePtr, u8 Enable)
 This function enables or disables downshifting during the training process. More...
 
void XDp_TxSetHasRedriverInPath (XDp *InstancePtr, u8 Set)
 This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path. More...
 
void XDp_TxCfgTxVsOffset (XDp *InstancePtr, u8 Offset)
 This function sets the voltage swing offset to use during training when no redriver exists. More...
 
void XDp_TxCfgTxVsLevel (XDp *InstancePtr, u8 Level, u8 TxLevel)
 This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level. More...
 
void XDp_TxCfgTxPeLevel (XDp *InstancePtr, u8 Level, u8 TxLevel)
 This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level. More...
 
u32 XDp_TxIsConnected (XDp *InstancePtr)
 This function checks if there is a connected RX device. More...
 
u32 XDp_TxAuxRead (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToRead, void *ReadData)
 This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space. More...
 
u32 XDp_TxAuxWrite (XDp *InstancePtr, u32 DpcdAddress, u32 BytesToWrite, void *WriteData)
 This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space. More...
 
u32 XDp_TxIicRead (XDp *InstancePtr, u8 IicAddress, u16 Offset, u16 BytesToRead, void *ReadData)
 This function performs an I2C read over the AUX channel. More...
 
u32 XDp_TxIicWrite (XDp *InstancePtr, u8 IicAddress, u8 BytesToWrite, void *WriteData)
 This function performs an I2C write over the AUX channel. More...
 
u32 XDp_TxSetDownspread (XDp *InstancePtr, u8 Enable)
 This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device. More...
 
u32 XDp_TxSetEnhancedFrameMode (XDp *InstancePtr, u8 Enable)
 This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device. More...
 
u32 XDp_TxSetLaneCount (XDp *InstancePtr, u8 LaneCount)
 This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device. More...
 
u32 XDp_TxSetLinkRate (XDp *InstancePtr, u8 LinkRate)
 This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device. More...
 
u32 XDp_TxSetScrambler (XDp *InstancePtr, u8 Enable)
 This function enables or disables scrambling of symbols for both the DisplayPort and the RX device. More...
 
void XDp_TxEnableMainLink (XDp *InstancePtr)
 This function enables the main link. More...
 
void XDp_TxDisableMainLink (XDp *InstancePtr)
 This function disables the main link. More...
 
void XDp_TxResetPhy (XDp *InstancePtr, u32 Reset)
 This function does a PHY reset. More...
 
void XDp_TxSetPhyPolarityAll (XDp *InstancePtr, u8 Polarity)
 This function sets the PHY polarity on all lanes. More...
 
void XDp_TxSetPhyPolarityLane (XDp *InstancePtr, u8 Lane, u8 Polarity)
 This function sets the PHY polarity on a specified lane. More...
 
u32 XDp_RxCheckLinkStatus (XDp *InstancePtr)
 This function checks if the receiver's internal registers indicate that link training has complete. More...
 
void XDp_RxDtgEn (XDp *InstancePtr)
 This function enables the display timing generator (DTG). More...
 
void XDp_RxDtgDis (XDp *InstancePtr)
 This function disables the display timing generator (DTG). More...
 
void XDp_RxSetLinkRate (XDp *InstancePtr, u8 LinkRate)
 This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers. More...
 
void XDp_RxSetLaneCount (XDp *InstancePtr, u8 LaneCount)
 This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers. More...
 
void XDp_RxAudioEn (XDp *InstancePtr)
 This function enables audio stream packets on the main link. More...
 
void XDp_RxAudioDis (XDp *InstancePtr)
 This function disables audio stream packets on the main link. More...
 
void XDp_RxAudioReset (XDp *InstancePtr)
 This function resets the RX core's reception of audio stream packets on the main link. More...
 
void XDp_SetUserTimerHandler (XDp *InstancePtr, XDp_TimerHandler CallbackFunc, void *CallbackRef)
 This function installs a custom delay/sleep function to be used by the XDp driver. More...
 
void XDp_WaitUs (XDp *InstancePtr, u32 MicroSeconds)
 This function is the delay/sleep function for the XDp driver. More...
 
void XDp_TxSetLaneCountChangeCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the driver's lane count change function is called either directly by the user or during link training. More...
 
void XDp_TxSetLinkRateChangeCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the driver's link rate change function is called either directly by the user or during link training. More...
 
void XDp_TxSetPeVsAdjustCallback (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the driver's link rate change function is called during link training. More...
 
u8 XDp_IsLinkRateValid (XDp *InstancePtr, u8 LinkRate)
 This function checks the validity of the link rate. More...
 
u8 XDp_IsLaneCountValid (XDp *InstancePtr, u8 LaneCount)
 This function checks the validity of the lane count. More...
 
XDp_ConfigXDp_LookupConfig (u16 DeviceId)
 This function looks for the device configuration based on the unique device ID. More...
 
u32 XDp_TxGetEdid (XDp *InstancePtr, u8 *Edid)
 This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure. More...
 
u32 XDp_TxGetRemoteEdid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Edid)
 This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure. More...
 
u32 XDp_TxGetEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum)
 Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number. More...
 
u32 XDp_TxGetRemoteEdidBlock (XDp *InstancePtr, u8 *Data, u8 BlockNum, u8 LinkCountTotal, u8 *RelativeAddress)
 Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number. More...
 
u32 XDp_TxGetRemoteEdidDispIdExt (XDp *InstancePtr, u8 *Data, u8 LinkCountTotal, u8 *RelativeAddress)
 Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID. More...
 
u32 XDp_TxGetDispIdDataBlock (u8 *DisplayIdRaw, u8 SectionTag, u8 **DataBlockPtr)
 Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure. More...
 
u32 XDp_TxGetRemoteTiledDisplayDb (XDp *InstancePtr, u8 *EdidExt, u8 LinkCountTotal, u8 *RelativeAddress, u8 **DataBlockPtr)
 Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure. More...
 
void XDp_InterruptHandler (XDp *InstancePtr)
 This function is the interrupt handler for the XDp driver. More...
 
void XDp_TxSetHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a hot-plug-detect event interrupt occurs. More...
 
void XDp_TxSetHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a hot-plug-detect pulse interrupt occurs. More...
 
void XDp_TxSetDrvHpdEventHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a driver's internal callback function for when a hot-plug-detect event interrupt occurs. More...
 
void XDp_TxSetDrvHpdPulseHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a driver's internal callback function for when a hot-plug-detect pulse interrupt occurs. More...
 
void XDp_TxSetMsaHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the main stream attribute (MSA) values are updated. More...
 
void XDp_RxGenerateHpdInterrupt (XDp *InstancePtr, u16 DurationUs)
 This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration. More...
 
void XDp_RxInterruptEnable (XDp *InstancePtr, u32 Mask)
 This function enables interrupts associated with the specified mask. More...
 
void XDp_RxInterruptDisable (XDp *InstancePtr, u32 Mask)
 This function disables interrupts associated with the specified mask. More...
 
void XDp_RxSetIntrVmChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a video mode change interrupt occurs. More...
 
void XDp_RxSetIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the power state interrupt occurs. More...
 
void XDp_RxSetIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a no video interrupt occurs. More...
 
void XDp_RxSetIntrVBlankHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a vertical blanking interrupt occurs. More...
 
void XDp_RxSetIntrTrainingLostHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a training lost interrupt occurs. More...
 
void XDp_RxSetIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a valid video interrupt occurs. More...
 
void XDp_RxSetIntrInfoPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when an audio info packet interrupt occurs. More...
 
void XDp_RxSetIntrExtPktHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when an audio extension packet interrupt occurs. More...
 
void XDp_RxSetIntrTrainingDoneHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a training done interrupt occurs. More...
 
void XDp_RxSetIntrBwChangeHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a bandwidth change interrupt occurs. More...
 
void XDp_RxSetIntrTp1Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a training pattern 1 interrupt occurs. More...
 
void XDp_RxSetIntrTp2Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a training pattern 2 interrupt occurs. More...
 
void XDp_RxSetIntrTp3Handler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a training pattern 3 interrupt occurs. More...
 
void XDp_RxSetIntrDownReqHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a down request interrupt occurs. More...
 
void XDp_RxSetIntrDownReplyHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a down reply interrupt occurs. More...
 
void XDp_RxSetIntrAudioOverHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when an audio packet overflow interrupt occurs. More...
 
void XDp_RxSetIntrPayloadAllocHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when the RX's DPCD payload allocation registers have been written for allocation, de-allocation, or partial deletion. More...
 
void XDp_RxSetIntrActRxHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when an ACT received interrupt occurs. More...
 
void XDp_RxSetIntrCrcTestHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a CRC test start interrupt occurs. More...
 
void XDp_RxSetIntrHdcpDebugWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a write to any hdcp debug register occurs. More...
 
void XDp_RxSetIntrHdcpAksvWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a write to the hdcp Aksv MSB register occurs. More...
 
void XDp_RxSetIntrHdcpAnWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a write to the hdcp An MSB register occurs. More...
 
void XDp_RxSetIntrHdcpAinfoWriteHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a write to the hdcp Ainfo MSB register occurs. More...
 
void XDp_RxSetIntrHdcpRoReadHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a read of the hdcp Ro/Ri MSB register occurs. More...
 
void XDp_RxSetIntrHdcpBinfoReadHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when a read of the hdcp Binfo register occurs. More...
 
void XDp_RxSetIntrUnplugHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a callback function for when an unplug event interrupt occurs. More...
 
void XDp_RxSetDrvIntrVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a driver callback function for when a valid video interrupt occurs. More...
 
void XDp_RxSetDrvIntrPowerStateHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs a driver callback function for when the power state interrupt occurs. More...
 
void XDp_RxSetDrvIntrNoVideoHandler (XDp *InstancePtr, XDp_IntrHandler CallbackFunc, void *CallbackRef)
 This function installs driver callback function for when a no video interrupt occurs. More...
 
void XDp_TxMstCfgModeEnable (XDp *InstancePtr)
 This function will enable multi-stream transport (MST) mode for the driver. More...
 
void XDp_TxMstCfgModeDisable (XDp *InstancePtr)
 This function will disable multi-stream transport (MST) mode for the driver. More...
 
u32 XDp_TxMstCapable (XDp *InstancePtr)
 This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode. More...
 
u32 XDp_TxMstEnable (XDp *InstancePtr)
 This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device. More...
 
u32 XDp_TxMstDisable (XDp *InstancePtr)
 This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device. More...
 
void XDp_TxMstCfgStreamEnable (XDp *InstancePtr, u8 Stream)
 This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream. More...
 
void XDp_TxMstCfgStreamDisable (XDp *InstancePtr, u8 Stream)
 This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream. More...
 
u8 XDp_TxMstStreamIsEnabled (XDp *InstancePtr, u8 Stream)
 This function will check whether. More...
 
void XDp_TxSetStreamSelectFromSinkList (XDp *InstancePtr, u8 Stream, u8 SinkNum)
 This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList. More...
 
void XDp_TxSetStreamSinkRad (XDp *InstancePtr, u8 Stream, u8 LinkCountTotal, u8 *RelativeAddress)
 This function will map a stream to a downstream DisplayPort TX device determined by the relative address. More...
 
u32 XDp_TxDiscoverTopology (XDp *InstancePtr)
 This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX. More...
 
u32 XDp_TxFindAccessibleDpDevices (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress)
 This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters. More...
 
void XDp_TxTopologySwapSinks (XDp *InstancePtr, u8 Index0, u8 Index1)
 Swap the ordering of the sinks in the topology's sink list. More...
 
void XDp_TxTopologySortSinksByTiling (XDp *InstancePtr)
 Order the sink list with all sinks of the same tiled display being sorted by 'tile order'. More...
 
u32 XDp_TxRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
 This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message. More...
 
u32 XDp_TxRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
 This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message. More...
 
u32 XDp_TxRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u16 Offset, u16 BytesToRead, u8 *ReadData)
 This function performs a remote I2C read by sending a sideband message. More...
 
u32 XDp_TxRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicAddress, u8 BytesToWrite, u8 *WriteData)
 This function performs a remote I2C write by sending a sideband message. More...
 
u32 XDp_TxAllocatePayloadStreams (XDp *InstancePtr)
 This function will allocate bandwidth for all enabled stream. More...
 
u32 XDp_TxAllocatePayloadVcIdTable (XDp *InstancePtr, u8 VcId, u8 Ts, u8 StartTs)
 This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress. More...
 
u32 XDp_TxClearPayloadVcIdTable (XDp *InstancePtr)
 This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices. More...
 
u32 XDp_TxSendSbMsgRemoteDpcdWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToWrite, u8 *WriteData)
 This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device. More...
 
u32 XDp_TxSendSbMsgRemoteDpcdRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u32 DpcdAddress, u32 BytesToRead, u8 *ReadData)
 This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device. More...
 
u32 XDp_TxSendSbMsgRemoteIicWrite (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 BytesToWrite, u8 *WriteData)
 This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device. More...
 
u32 XDp_TxSendSbMsgRemoteIicRead (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 IicDeviceId, u8 Offset, u8 BytesToRead, u8 *ReadData)
 This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device. More...
 
u32 XDp_TxSendSbMsgLinkAddress (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, XDp_SbMsgLinkAddressReplyDeviceInfo *DeviceInfo)
 This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device. More...
 
u32 XDp_TxSendSbMsgEnumPathResources (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u16 *AvailPbn, u16 *FullPbn)
 This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device. More...
 
u32 XDp_TxSendSbMsgAllocatePayload (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 VcId, u16 Pbn)
 This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device. More...
 
u32 XDp_TxSendSbMsgClearPayloadIdTable (XDp *InstancePtr)
 This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables. More...
 
void XDp_TxWriteGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Guid)
 This function will write a global unique identifier (GUID) to the target DisplayPort device. More...
 
void XDp_TxGetGuid (XDp *InstancePtr, u8 LinkCountTotal, u8 *RelativeAddress, u8 *Guid)
 This function will obtain the global unique identifier (GUID) for the target DisplayPort device. More...
 
u32 XDp_RxHandleDownReq (XDp *InstancePtr)
 This function will handle incoming sideband messages. More...
 
XDp_RxIicMapEntryXDp_RxGetIicMapEntry (XDp *InstancePtr, u8 PortNum, u8 IicAddress)
 This function returns a pointer to the I2C map entry at the supplied I2C address for the specified port. More...
 
u32 XDp_RxSetIicMapEntry (XDp *InstancePtr, u8 PortNum, u8 IicAddress, u8 ReadNumBytes, u8 *ReadData)
 This function adds an entry into the I2C map for a given port. More...
 
void XDp_RxSetDpcdMap (XDp *InstancePtr, u8 PortNum, u32 StartAddr, u32 NumBytes, u8 *DpcdMap)
 This function specified the DPCD address space for a given port. More...
 
void XDp_RxMstExposePort (XDp *InstancePtr, u8 PortNum, u8 Expose)
 This function allows the user to select which ports will be exposed when replying to a LINK_ADDRESS sideband message. More...
 
void XDp_RxMstSetPort (XDp *InstancePtr, u8 PortNum, XDp_SbMsgLinkAddressReplyPortDetail *PortDetails)
 This function sets the port information that is contained in the driver instance structure for the specified port number, to be copied from the supplied port details structure. More...
 
void XDp_RxMstSetInputPort (XDp *InstancePtr, u8 PortNum, XDp_SbMsgLinkAddressReplyPortDetail *PortOverride)
 This function, for an input port, sets the port information that is contained in the driver instance structure for the specified port number. More...
 
void XDp_RxMstSetPbn (XDp *InstancePtr, u8 PortNum, u16 PbnVal)
 This function will set the available payload bandwidth number (PBN) of the specified port that is available for allocation, and the full PBN that the port is capable of using. More...
 
u32 XDp_SelfTest (XDp *InstancePtr)
 This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode. More...
 
void XDp_TxCfgMsaRecalculate (XDp *InstancePtr, u8 Stream)
 This function calculates the following Main Stream Attributes (MSA): More...
 
void XDp_TxCfgMsaUseStandardVideoMode (XDp *InstancePtr, u8 Stream, XVidC_VideoMode VideoMode)
 This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table. More...
 
void XDp_TxCfgMsaUseEdidPreferredTiming (XDp *InstancePtr, u8 Stream, u8 *Edid)
 This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor. More...
 
void XDp_TxCfgMsaUseCustom (XDp *InstancePtr, u8 Stream, XDp_TxMainStreamAttributes *MsaConfigCustom, u8 Recalculate)
 This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig. More...
 
u32 XDp_TxCfgSetColorEncode (XDp *InstancePtr, u8 Stream, XVidC_ColorFormat Format, XVidC_ColorStd ColorCoeffs, XDp_DynamicRange Range)
 This function will set the color encoding scheme for a given stream. More...
 
void XDp_TxCfgMsaSetBpc (XDp *InstancePtr, u8 Stream, u8 BitsPerColor)
 This function sets the bits per color value of the video stream. More...
 
void XDp_TxCfgMsaEnSynchClkMode (XDp *InstancePtr, u8 Stream, u8 Enable)
 This function enables or disables synchronous clock mode for a video stream. More...
 
void XDp_TxSetVideoMode (XDp *InstancePtr, u8 Stream)
 This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure. More...
 
void XDp_TxClearMsaValues (XDp *InstancePtr, u8 Stream)
 This function clears the main stream attributes registers of the DisplayPort TX core. More...
 
void XDp_TxSetMsaValues (XDp *InstancePtr, u8 Stream)
 This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure. More...
 
void XDp_TxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth)
 This function configures the number of pixels output through the user data interface for DisplayPort TX core. More...
 
void XDp_RxSetUserPixelWidth (XDp *InstancePtr, u8 UserPixelWidth)
 This function configures the number of pixels output through the user data interface. More...
 
XVidC_ColorDepth XDp_RxGetBpc (XDp *InstancePtr, u8 Stream)
 This function extracts the bits per color from MISC0 of the stream. More...
 
XVidC_ColorFormat XDp_RxGetColorComponent (XDp *InstancePtr, u8 Stream)
 This function extracts the color component format from MISC0 of the stream. More...
 
void XDp_RxSetLineReset (XDp *InstancePtr, u8 Stream)
 Disable/enables the end of line reset to the internal video pipe in case of reduced blanking as required. More...
 
void XDp_RxAllocatePayloadStream (XDp *InstancePtr)
 This function will set the virtual channel payload table both in software and in the DisplayPort RX core's hardware registers based on the MST allocation values from ALLOCATE_PAYLOAD and CLEAR_PAYLOAD sideband message requests. More...
 

Variables

u8 GuidTable [16][XDP_GUID_NBYTES]
 This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function. More...
 
u32 TxResetValues [2][2]
 This table contains the default values for the DisplayPort TX core's general usage registers. More...
 
u32 TxResetValuesMsa [20][2]
 This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers. More...
 
u32 RxResetValues [2][2]
 This table contains the default values for the DisplayPort RX core's general usage registers. More...
 
XDp_Config XDp_ConfigTable [XPAR_XDP_NUM_INSTANCES]
 A table of configuration structures containing the configuration information for each DisplayPort TX core in the system. More...
 

DPTX core registers: Link configuration field.

Address mapping for the DisplayPort core in TX mode.

#define XDP_TX_LINK_BW_SET   0x000
 Set main link bandwidth setting. More...
 
#define XDP_TX_LANE_COUNT_SET   0x004
 Set lane count setting. More...
 
#define XDP_TX_ENHANCED_FRAME_EN   0x008
 Enable enhanced framing symbol sequence. More...
 
#define XDP_TX_TRAINING_PATTERN_SET   0x00C
 Set the link training pattern. More...
 
#define XDP_TX_LINK_QUAL_PATTERN_SET   0x010
 Transmit the link quality pattern. More...
 
#define XDP_TX_SCRAMBLING_DISABLE   0x014
 Disable scrambler and transmit all symbols. More...
 
#define XDP_TX_DOWNSPREAD_CTRL   0x018
 Enable a 0.5% spreading of the clock. More...
 
#define XDP_TX_SOFT_RESET   0x01C
 Software reset. More...
 

DPTX core registers: Core enables.

#define XDP_TX_ENABLE   0x080
 Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. More...
 
#define XDP_TX_ENABLE_MAIN_STREAM   0x084
 Enable transmission of main link video info. More...
 
#define XDP_TX_ENABLE_SEC_STREAM   0x088
 Enable the transmission of secondary link info. More...
 
#define XDP_TX_FORCE_SCRAMBLER_RESET   0x0C0
 Force a scrambler reset. More...
 
#define XDP_TX_MST_CONFIG   0x0D0
 Enable MST. More...
 
#define XDP_TX_LINE_RESET_DISABLE   0x0F0
 TX line reset disable. More...
 

DPTX core registers: Core ID.

#define XDP_TX_VERSION   0x0F8
 Version and revision of the DisplayPort core. More...
 
#define XDP_TX_CORE_ID   0x0FC
 DisplayPort protocol version and revision. More...
 

DPTX core registers: AUX channel interface.

#define XDP_TX_AUX_CMD   0x100
 Initiates AUX commands. More...
 
#define XDP_TX_AUX_WRITE_FIFO   0x104
 Write data for the current AUX command. More...
 
#define XDP_TX_AUX_ADDRESS   0x108
 Specifies the address of current AUX command. More...
 
#define XDP_TX_AUX_CLK_DIVIDER   0x10C
 Clock divider value for generating the internal 1MHz clock. More...
 
#define XDP_TX_USER_FIFO_OVERFLOW   0x110
 Indicates an overflow in user FIFO. More...
 
#define XDP_TX_INTERRUPT_SIG_STATE   0x130
 The raw signal values for interrupt events. More...
 
#define XDP_TX_AUX_REPLY_DATA   0x134
 Reply data received during the AUX reply. More...
 
#define XDP_TX_AUX_REPLY_CODE   0x138
 Reply code received from the most recent AUX command. More...
 
#define XDP_TX_AUX_REPLY_COUNT   0x13C
 Number of reply transactions received over AUX. More...
 
#define XDP_TX_INTERRUPT_STATUS   0x140
 Status for interrupt events. More...
 
#define XDP_TX_INTERRUPT_MASK   0x144
 Masks the specified interrupt sources. More...
 
#define XDP_TX_REPLY_DATA_COUNT   0x148
 Total number of data bytes actually received during a transaction. More...
 
#define XDP_TX_REPLY_STATUS   0x14C
 Reply status of most recent AUX transaction. More...
 
#define XDP_TX_HPD_DURATION   0x150
 Duration of the HPD pulse in microseconds. More...
 

DPTX core registers: Main stream attributes for SST / MST STREAM1.

#define XDP_TX_STREAM1_MSA_START   0x180
 Start of the MSA registers for stream 1. More...
 
#define XDP_TX_MAIN_STREAM_HTOTAL   0x180
 Total number of clocks in the horizontal framing period. More...
 
#define XDP_TX_MAIN_STREAM_VTOTAL   0x184
 Total number of lines in the video frame. More...
 
#define XDP_TX_MAIN_STREAM_POLARITY   0x188
 Polarity for the video sync signals. More...
 
#define XDP_TX_MAIN_STREAM_HSWIDTH   0x18C
 Width of the horizontal sync pulse. More...
 
#define XDP_TX_MAIN_STREAM_VSWIDTH   0x190
 Width of the vertical sync pulse. More...
 
#define XDP_TX_MAIN_STREAM_HRES   0x194
 Number of active pixels per line (the horizontal resolution). More...
 
#define XDP_TX_MAIN_STREAM_VRES   0x198
 Number of active lines (the vertical resolution). More...
 
#define XDP_TX_MAIN_STREAM_HSTART   0x19C
 Number of clocks between the leading edge of the horizontal sync and the start of active data. More...
 
#define XDP_TX_MAIN_STREAM_VSTART   0x1A0
 Number of lines between the leading edge of the vertical sync and the first line of active data. More...
 
#define XDP_TX_MAIN_STREAM_MISC0   0x1A4
 Miscellaneous stream attributes. More...
 
#define XDP_TX_MAIN_STREAM_MISC1   0x1A8
 Miscellaneous stream attributes. More...
 
#define XDP_TX_M_VID   0x1AC
 M value for the video stream as computed by the source core in asynchronous clock mode. More...
 
#define XDP_TX_TU_SIZE   0x1B0
 Size of a transfer unit in the framing logic. More...
 
#define XDP_TX_N_VID   0x1B4
 N value for the video stream as computed by the source core in asynchronous clock mode. More...
 
#define XDP_TX_USER_PIXEL_WIDTH   0x1B8
 Selects the width of the user data input port. More...
 
#define XDP_TX_USER_DATA_COUNT_PER_LANE   0x1BC
 Used to translate the number of pixels per line to the native internal 16-bit datapath. More...
 
#define XDP_TX_MAIN_STREAM_INTERLACED   0x1C0
 Video is interlaced. More...
 
#define XDP_TX_MIN_BYTES_PER_TU   0x1C4
 The minimum number of bytes per transfer unit. More...
 
#define XDP_TX_FRAC_BYTES_PER_TU   0x1C8
 The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value. More...
 
#define XDP_TX_INIT_WAIT   0x1CC
 Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. More...
 
#define XDP_TX_STREAM1   0x1D0
 Average stream symbol timeslots per MTP config. More...
 
#define XDP_TX_STREAM2   0x1D4
 Average stream symbol timeslots per MTP config. More...
 
#define XDP_TX_STREAM3   0x1D8
 Average stream symbol timeslots per MTP config. More...
 
#define XDP_TX_STREAM4   0x1DC
 Average stream symbol timeslots per MTP config. More...
 

DPTX core registers: PHY configuration status.

#define XDP_TX_PHY_CONFIG   0x200
 Transceiver PHY reset and configuration. More...
 
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0   0x220
 Controls the differential voltage swing. More...
 
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1   0x224
 Controls the differential voltage swing. More...
 
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2   0x228
 Controls the differential voltage swing. More...
 
#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3   0x22C
 Controls the differential voltage swing. More...
 
#define XDP_TX_PHY_TRANSMIT_PRBS7   0x230
 Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. More...
 
#define XDP_TX_PHY_CLOCK_SELECT   0x234
 Instructs the PHY PLL to generate the proper clock frequency for the required link rate. More...
 
#define XDP_TX_PHY_POWER_DOWN   0x238
 Controls PHY power down. More...
 
#define XDP_TX_PHY_PRECURSOR_LANE_0   0x23C
 Controls the pre-cursor level. More...
 
#define XDP_TX_PHY_PRECURSOR_LANE_1   0x240
 Controls the pre-cursor level. More...
 
#define XDP_TX_PHY_PRECURSOR_LANE_2   0x244
 Controls the pre-cursor level. More...
 
#define XDP_TX_PHY_PRECURSOR_LANE_3   0x248
 Controls the pre-cursor level. More...
 
#define XDP_TX_PHY_POSTCURSOR_LANE_0   0x24C
 Controls the post-cursor level. More...
 
#define XDP_TX_PHY_POSTCURSOR_LANE_1   0x250
 Controls the post-cursor level. More...
 
#define XDP_TX_PHY_POSTCURSOR_LANE_2   0x254
 Controls the post-cursor level. More...
 
#define XDP_TX_PHY_POSTCURSOR_LANE_3   0x258
 Controls the post-cursor level. More...
 
#define XDP_TX_PHY_STATUS   0x280
 Current PHY status. More...
 
#define XDP_TX_GT_DRP_COMMAND   0x2A0
 Provides access to the GT DRP ports. More...
 
#define XDP_TX_GT_DRP_READ_DATA   0x2A4
 Provides access to GT DRP read data. More...
 
#define XDP_TX_GT_DRP_CHANNEL_STATUS   0x2A8
 Provides access to GT DRP channel status. More...
 

DPTX core registers: DisplayPort audio.

#define XDP_TX_AUDIO_CONTROL   0x300
 Enables audio stream packets in main link and buffer control. More...
 
#define XDP_TX_AUDIO_CHANNELS   0x304
 Used to input active channel count. More...
 
#define XDP_TX_AUDIO_INFO_DATA(NUM)   (0x308 + 4 * (NUM - 1))
 Word formatted as per CEA 861-C info frame. More...
 
#define XDP_TX_AUDIO_MAUD   0x328
 M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. More...
 
#define XDP_TX_AUDIO_NAUD   0x32C
 N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. More...
 
#define XDP_TX_AUDIO_EXT_DATA(NUM)   (0x330 + 4 * (NUM - 1))
 Word formatted as per extension packet. More...
 

DPTX core registers: DisplayPort video.

#define XDP_TX_VIDEO_PACKING_CLOCK_CONTROL   0x90
 

DPTX core registers: HDCP.

#define XDP_TX_HDCP_ENABLE   0x400
 Enables HDCP core. More...
 

DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.

#define XDP_TX_STREAM2_MSA_START   0x500
 Start of the MSA registers for stream 2. More...
 
#define XDP_TX_STREAM2_MSA_START_OFFSET
 The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. More...
 
#define XDP_TX_STREAM3_MSA_START   0x550
 Start of the MSA registers for stream 3. More...
 
#define XDP_TX_STREAM3_MSA_START_OFFSET
 The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. More...
 
#define XDP_TX_STREAM4_MSA_START   0x5A0
 Start of the MSA registers for stream 4. More...
 
#define XDP_TX_STREAM4_MSA_START_OFFSET
 The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. More...
 

DPTX core masks, shifts, and register values.

#define XDP_TX_LINK_BW_SET_162GBPS   0x06
 1.62 Gbps link rate. More...
 
#define XDP_TX_LINK_BW_SET_270GBPS   0x0A
 2.70 Gbps link rate. More...
 
#define XDP_TX_LINK_BW_SET_540GBPS   0x14
 5.40 Gbps link rate. More...
 
#define XDP_TX_LANE_COUNT_SET_1   0x01
 Lane count of 1. More...
 
#define XDP_TX_LANE_COUNT_SET_2   0x02
 Lane count of 2. More...
 
#define XDP_TX_LANE_COUNT_SET_4   0x04
 Lane count of 4. More...
 
#define XDP_TX_TRAINING_PATTERN_SET_OFF   0x0
 Training off. More...
 
#define XDP_TX_TRAINING_PATTERN_SET_TP1   0x1
 Training pattern 1 used for clock recovery. More...
 
#define XDP_TX_TRAINING_PATTERN_SET_TP2   0x2
 Training pattern 2 used for channel equalization. More...
 
#define XDP_TX_TRAINING_PATTERN_SET_TP3   0x3
 Training pattern 3 used for channel equalization for cores with DP v1.2. More...
 
#define XDP_TX_LINK_QUAL_PATTERN_SET_OFF   0x0
 Link quality test pattern not transmitted. More...
 
#define XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1
 D10.2 unscrambled test pattern transmitted. More...
 
#define XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES   0x2
 Symbol error rate measurement pattern transmitted. More...
 
#define XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7   0x3
 Pseudo random bit sequence 7 transmitted. More...
 
#define XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001
 Reset video logic. More...
 
#define XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002
 Reset video logic. More...
 
#define XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004
 Reset video logic. More...
 
#define XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008
 Reset video logic. More...
 
#define XDP_TX_SOFT_RESET_AUX_MASK   0x00000080
 Reset AUX logic. More...
 
#define XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F
 Reset video logic for all streams. More...
 
#define XDP_TX_MST_CONFIG_MST_EN_MASK   0x00000001
 Enable MST. More...
 
#define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002
 The VC payload has been updated in the sink. More...
 
#define XDP_TX_LINE_RESET_DISABLE_MASK(Stream)   (1 << ((Stream) - XDP_TX_STREAM_ID1))
 Used to disable the end of the line reset to the internal video pipe. More...
 
#define XDP_TX_VERSION_INTER_REV_MASK   0x0000000F
 Internal revision. More...
 
#define XDP_TX_VERSION_CORE_PATCH_MASK   0x00000030
 Core patch details. More...
 
#define XDP_TX_VERSION_CORE_PATCH_SHIFT   8
 Shift bits for core patch details. More...
 
#define XDP_TX_VERSION_CORE_VER_REV_MASK   0x000000C0
 Core version revision. More...
 
#define XDP_TX_VERSION_CORE_VER_REV_SHIFT   12
 Shift bits for core version revision. More...
 
#define XDP_TX_VERSION_CORE_VER_MNR_MASK   0x00000F00
 Core minor version. More...
 
#define XDP_TX_VERSION_CORE_VER_MNR_SHIFT   16
 Shift bits for core minor version. More...
 
#define XDP_TX_VERSION_CORE_VER_MJR_MASK   0x0000F000
 Core major version. More...
 
#define XDP_TX_VERSION_CORE_VER_MJR_SHIFT   24
 Shift bits for core major version. More...
 
#define XDP_TX_CORE_ID_TYPE_MASK   0x0000000F
 Core type. More...
 
#define XDP_TX_CORE_ID_TYPE_TX   0x0
 Core is a transmitter. More...
 
#define XDP_TX_CORE_ID_TYPE_RX   0x1
 Core is a receiver. More...
 
#define XDP_TX_CORE_ID_DP_REV_MASK   0x000000F0
 DisplayPort protocol revision. More...
 
#define XDP_TX_CORE_ID_DP_REV_SHIFT   8
 Shift bits for DisplayPort protocol revision. More...
 
#define XDP_TX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
 DisplayPort protocol minor version. More...
 
#define XDP_TX_CORE_ID_DP_MNR_VER_SHIFT   16
 Shift bits for DisplayPort protocol major version. More...
 
#define XDP_TX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
 DisplayPort protocol major version. More...
 
#define XDP_TX_CORE_ID_DP_MJR_VER_SHIFT   24
 Shift bits for DisplayPort protocol major version. More...
 
#define XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F
 Number of bytes to transfer with the current AUX command. More...
 
#define XDP_TX_AUX_CMD_MASK   0x00000F00
 AUX command. More...
 
#define XDP_TX_AUX_CMD_SHIFT   8
 Shift bits for command. More...
 
#define XDP_TX_AUX_CMD_I2C_WRITE   0x0
 I2C-over-AUX write command. More...
 
#define XDP_TX_AUX_CMD_I2C_READ   0x1
 I2C-over-AUX read command. More...
 
#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS   0x2
 I2C-over-AUX write status command. More...
 
#define XDP_TX_AUX_CMD_I2C_WRITE_MOT   0x4
 I2C-over-AUX write MOT (middle-of-transaction) command. More...
 
#define XDP_TX_AUX_CMD_I2C_READ_MOT   0x5
 I2C-over-AUX read MOT (middle-of-transaction) command. More...
 
#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6
 I2C-over-AUX write status MOT (middle-of- transaction) command. More...
 
#define XDP_TX_AUX_CMD_WRITE   0x8
 AUX write command. More...
 
#define XDP_TX_AUX_CMD_READ   0x9
 AUX read command. More...
 
#define XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000
 Address only transfer enable (STOP will be sent after command). More...
 
#define XDP_TX_AUX_CLK_DIVIDER_VAL_MASK   0x00FF
 Clock divider value. More...
 
#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0xFF00
 AUX (noise) signal width filter. More...
 
#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
 Shift bits for AUX signal width filter. More...
 
#define XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001
 Raw state of the HPD pin on the DP connector. More...
 
#define XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002
 A request is currently being sent. More...
 
#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004
 A reply is currently being received. More...
 
#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008
 A reply timeout has occurred. More...
 
#define XDP_TX_AUX_REPLY_CODE_ACK   0x0
 AUX command ACKed. More...
 
#define XDP_TX_AUX_REPLY_CODE_I2C_ACK   0x0
 I2C-over-AUX command not ACKed. More...
 
#define XDP_TX_AUX_REPLY_CODE_NACK   0x1
 AUX command not ACKed. More...
 
#define XDP_TX_AUX_REPLY_CODE_DEFER   0x2
 AUX command deferred. More...
 
#define XDP_TX_AUX_REPLY_CODE_I2C_NACK   0x4
 I2C-over-AUX command not ACKed. More...
 
#define XDP_TX_AUX_REPLY_CODE_I2C_DEFER   0x8
 I2C-over-AUX command deferred. More...
 
#define XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001
 Detected an IRQ framed with the proper timing on the HPD signal. More...
 
#define XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002
 Detected the presence of the HPD signal. More...
 
#define XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004
 An AUX reply transaction has been detected. More...
 
#define XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008
 A reply timeout has occurred. More...
 
#define XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010
 A pulse on the HPD line was detected. More...
 
#define XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020
 Extended packet has been transmitted and the core is ready to accept a new packet. More...
 
#define XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001
 Mask HPD IRQ interrupt. More...
 
#define XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002
 Mask HPD event interrupt. More...
 
#define XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004
 Mask reply received interrupt. More...
 
#define XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008
 Mask reply received interrupt. More...
 
#define XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010
 Mask HPD pulse detected interrupt. More...
 
#define XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020
 Mask extended packet transmit interrupt. More...
 
#define XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001
 AUX transaction is complete and a valid reply transaction received. More...
 
#define XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002
 AUX reply is currently being received. More...
 
#define XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004
 AUX request is currently being transmitted. More...
 
#define XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008
 Detected an error in the AUX reply of the most recent transaction. More...
 
#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0
 Internal AUX reply state machine status bits. More...
 
#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4
 Shift bits for the internal AUX reply state machine status. More...
 
#define XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001
 Polarity of the horizontal sync pulse. More...
 
#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002
 Polarity of the vertical sync pulse. More...
 
#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1
 Shift bits for polarity of the vertical sync pulse. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001
 Synchronous clock. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006
 Component format. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1
 Shift bits for component format. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0
 Stream's component format is RGB. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x5
 Stream's component format is YcbCr 4:2:2. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x6
 Stream's component format is YcbCr 4:4:4. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008
 Dynamic range. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3
 Shift bits for dynamic range. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_VESA   0
 VESA range. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_CEA   1
 CEA range. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010
 YCbCr colorimetry. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4
 Shift bits for YCbCr colorimetry. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT601   0
 ITU BT601 YCbCr coefficients. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT709   1
 ITU BT709 YCbCr coefficients. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0
 Bit depth per color component (BDC). More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT   5
 Shift bits for BDC. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0
 6 bits per component. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1
 8 bits per component. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2
 10 bits per component. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3
 12 bits per component. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4
 16 bits per component. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_OVERRIDE_CLOCKING_MODE_MASK   0x00000100
 Override Audio clk Mode. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_MODE_MASK   0x00000200
 Audio clock modes, Setting this bit to 1 enables sync mode. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_INSERT_TIMESTAMP_MASK   0x00000400
 Inserts info/timestamp every 512 BS symbols. More...
 
#define XDP_TX_MAIN_STREAMX_MISC0_AUD_UNMASK_LOWER_MAUD_BITS_MASK   0x00000800
 Unmasks lower 2-bits of Maud value. More...
 
#define XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001
 Interlaced vertical total even. More...
 
#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006
 Stereo video attribute. More...
 
#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1
 Shift bits for stereo video attribute. More...
 
#define XDP_TX_MAIN_STREAMX_MISC1_Y_ONLY_EN_MASK   0x00000080 /* Y-only enable. */
 
#define XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0000000
 Release reset. More...
 
#define XDP_TX_PHY_CONFIG_PHY_RESET_MASK   0x0000001
 Hold the PHY in reset. More...
 
#define XDP_TX_PHY_CONFIG_GTTX_RESET_MASK   0x0000002
 Hold GTTXRESET in reset. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0000100
 Hold TX_PHY_PMA reset. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0000200
 Hold TX_PHY_PCS reset. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0000800
 Set TX_PHY_POLARITY. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0001000
 Set TX_PHY_PRBSFORCEERR. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x000E000
 Set TX_PHY_LOOPBACK. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT   13
 Shift bits for TX_PHY_LOOPBACK. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK   0x0010000
 Set to enable individual lane polarity. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK   0x0020000
 Set TX_PHY_POLARITY for lane 0. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK   0x0040000
 Set TX_PHY_POLARITY for lane 1. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK   0x0080000
 Set TX_PHY_POLARITY for lane 2. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK   0x0100000
 Set TX_PHY_POLARITY for lane 3. More...
 
#define XDP_TX_PHY_CONFIG_TX_PHY_8B10BEN_MASK   0x0200000
 8B10B encoding enable. More...
 
#define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0000003
 Reset GT and PHY. More...
 
#define XDP_TX_PHY_CLOCK_SELECT_162GBPS   0x1
 1.62 Gbps link. More...
 
#define XDP_TX_PHY_CLOCK_SELECT_270GBPS   0x3
 2.70 Gbps link. More...
 
#define XDP_TX_PHY_CLOCK_SELECT_540GBPS   0x5
 5.40 Gbps link. More...
 
#define XDP_TX_VS_LEVEL_0   0x2
 Voltage swing level 0. More...
 
#define XDP_TX_VS_LEVEL_1   0x5
 Voltage swing level 1. More...
 
#define XDP_TX_VS_LEVEL_2   0x8
 Voltage swing level 2. More...
 
#define XDP_TX_VS_LEVEL_3   0xF
 Voltage swing level 3. More...
 
#define XDP_TX_VS_LEVEL_OFFSET   0x4
 Voltage swing compensation offset used when there's no redriver in display path. More...
 
#define XDP_TX_PE_LEVEL_0   0x00
 Pre-emphasis level 0. More...
 
#define XDP_TX_PE_LEVEL_1   0x0E
 Pre-emphasis level 1. More...
 
#define XDP_TX_PE_LEVEL_2   0x14
 Pre-emphasis level 2. More...
 
#define XDP_TX_PE_LEVEL_3   0x1B
 Pre-emphasis level 3. More...
 
#define XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK   0x00000001
 Reset done for lane 0. More...
 
#define XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK   0x00000002
 Reset done for lane 1. More...
 
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
 Reset done for lanes 2 and 3. More...
 
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT   2
 Shift bits for reset done for lanes 2 and 3. More...
 
#define XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
 PLL locked for lanes 0 and 1. More...
 
#define XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
 PLL locked for lanes 2 and 3. More...
 
#define XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040
 FPGA fabric clock PLL locked. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000
 TX buffer status lane 0. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16
 Shift bits for TX buffer status lane 0. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000
 TX error on lane 0. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18
 Shift bits for TX error on lane 0. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000
 TX buffer status lane 1. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20
 Shift bits for TX buffer status lane 1. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000
 TX error on lane 1. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22
 Shift bits for TX error on lane 1. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000
 TX buffer status lane 2. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24
 Shift bits for TX buffer status lane 2. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000
 TX error on lane 2. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26
 Shift bits for TX error on lane 2. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000
 TX buffer status lane 3. More...
 
#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28
 Shift bits for TX buffer status lane 3. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000
 TX error on lane 3. More...
 
#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30
 Shift bits for TX error on lane 3. More...
 
#define XDP_TX_PHY_STATUS_LANE_0_READY_MASK
 Lane 0 is ready. More...
 
#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK
 Lanes 0-1 are ready. More...
 
#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK
 Lanes 0-3 are ready. More...
 
#define XDP_TX_PHY_STATUS_LANES_READY_MASK(n)
 Macro for lanes ready mask with number of lanes as the argument. More...
 
#define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F
 DRP address. More...
 
#define XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080
 DRP read/write command (Read=0, Write=1). More...
 
#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00
 DRP write data. More...
 
#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16
 Shift bits for DRP write data. More...
 
#define XDP_TX_HDCP_ENABLE_BYPASS_DISABLE_MASK   0x0001
 Disables bypass of the HDCP core. More...
 

DPRX core registers: Receiver core configuration.

Address mapping for the DisplayPort core in RX mode.

#define XDP_RX_LINK_ENABLE   0x000
 Enable the receiver core. More...
 
#define XDP_RX_AUX_CLK_DIVIDER   0x004
 Clock divider value for generating the internal 1MHz clock. More...
 
#define XDP_RX_AUX_DEFER_SHIFT   24
 Aux defer. More...
 
#define XDP_RX_LINE_RESET_DISABLE   0x008
 RX line reset disable. More...
 
#define XDP_RX_DTG_ENABLE   0x00C
 Enables the display timing generator (DTG). More...
 
#define XDP_RX_USER_PIXEL_WIDTH   0x010
 Selects the width of the user data input port. More...
 
#define XDP_RX_INTERRUPT_MASK   0x014
 Masks the specified interrupt sources for stream 1. More...
 
#define XDP_RX_MISC_CTRL   0x018
 Miscellaneous control of RX behavior. More...
 
#define XDP_RX_SOFT_RESET   0x01C
 Software reset. More...
 

DPRX core registers: AUX channel status.

#define XDP_RX_AUX_REQ_IN_PROGRESS   0x020
 Indicates the receipt of an AUX channel request. More...
 
#define XDP_RX_REQ_ERROR_COUNT   0x024
 Provides a running total of errors detected on inbound AUX channel requests. More...
 
#define XDP_RX_REQ_COUNT   0x028
 Provides a running total of the number of AUX requests received. More...
 
#define XDP_RX_HPD_INTERRUPT   0x02C
 Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal. More...
 
#define XDP_RX_REQ_CLK_WIDTH   0x030
 Holds the half period of the recovered AUX clock. More...
 
#define XDP_RX_REQ_CMD   0x034
 Provides the most recent AUX command received. More...
 
#define XDP_RX_REQ_ADDRESS   0x038
 Contains the address field of the most recent AUX request. More...
 
#define XDP_RX_REQ_LENGTH   0x03C
 Contains length of the most recent AUX request. More...
 

DPRX core registers: Interrupt registers.

#define XDP_RX_INTERRUPT_CAUSE   0x040
 Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel. More...
 
#define XDP_RX_INTERRUPT_MASK_1   0x044
 Masks the specified interrupt sources for streams 2, 3, 4. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1   0x048
 Indicates the cause of a pending host interrupts for streams 2, 3, 4. More...
 

DPRX core registers: DPCD fields.

#define XDP_RX_LOCAL_EDID_VIDEO   0x084
 Indicates the presence of EDID information for the video stream. More...
 
#define XDP_RX_LOCAL_EDID_AUDIO   0x088
 Indicates the presence of EDID information for the audio stream. More...
 
#define XDP_RX_REMOTE_CMD   0x08C
 Used for passing remote information to the DisplayPort TX. More...
 
#define XDP_RX_DEVICE_SERVICE_IRQ   0x090
 Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state. More...
 
#define XDP_RX_VIDEO_UNSUPPORTED   0x094
 DPCD register bit to inform the DisplayPort TX that video data is not supported. More...
 
#define XDP_RX_AUDIO_UNSUPPORTED   0x098
 DPCD register bit to inform the DisplayPort TX that audio data is not supported. More...
 
#define XDP_RX_OVER_LINK_BW_SET   0x09C
 Used to override the main link bandwidth setting in the DPCD. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET   0x0A0
 Used to override the lane count setting in the DPCD. More...
 
#define XDP_RX_OVER_TP_SET   0x0A4
 Used to override the link training pattern in the DPCD. More...
 
#define XDP_RX_OVER_TRAINING_LANE0_SET   0x0A8
 Used to override the TRAINING_LANE0_SET register in the DPCD. More...
 
#define XDP_RX_OVER_TRAINING_LANE1_SET   0x0AC
 Used to override the TRAINING_LANE1_SET register in the DPCD. More...
 
#define XDP_RX_OVER_TRAINING_LANE2_SET   0x0B0
 Used to override the TRAINING_LANE2_SET register in the DPCD. More...
 
#define XDP_RX_OVER_TRAINING_LANE3_SET   0x0B4
 Used to override the TRAINING_LANE3_SET register in the DPCD. More...
 
#define XDP_RX_OVER_CTRL_DPCD   0x0B8
 Used to enable AXI/APB write access to the DPCD capability structure. More...
 
#define XDP_RX_OVER_DOWNSPREAD_CTRL   0x0BC
 Used to override downspread control in the DPCD. More...
 
#define XDP_RX_OVER_LINK_QUAL_LANE0_SET   0x0C0
 Used to override the LINK_QUAL_LANE0_SET register in the DPCD. More...
 
#define XDP_RX_OVER_LINK_QUAL_LANE1_SET   0x0C4
 Used to override the LINK_QUAL_LANE1_SET register in the DPCD. More...
 
#define XDP_RX_OVER_LINK_QUAL_LANE2_SET   0x0C8
 Used to override the LINK_QUAL_LANE2_SET register in the DPCD. More...
 
#define XDP_RX_OVER_LINK_QUAL_LANE3_SET   0x0CC
 Used to override the LINK_QUAL_LANE3_SET register in the DPCD. More...
 
#define XDP_RX_MST_CAP   0x0D0
 Used to enable or disable MST capability. More...
 
#define XDP_RX_SINK_COUNT   0x0D4
 The sink device count. More...
 
#define XDP_RX_GUID0   0x0E0
 Lower 4 bytes of the DPCD's GUID field. More...
 
#define XDP_RX_GUID1   0x0E4
 Bytes 4 to 7 of the DPCD's GUID field. More...
 
#define XDP_RX_GUID2   0x0E8
 Bytes 8 to 11 of the DPCD's GUID field. More...
 
#define XDP_RX_GUID3   0x0EC
 Upper 4 bytes of the DPCD's GUID field. More...
 
#define XDP_RX_OVER_GUID   0x0F0
 Used to override the GUID field in the DPCD with what is stored in XDP_RX_GUID[0-3]. More...
 

DPRX core registers: Core ID.

#define XDP_RX_VERSION   0x0F8
 Version and revision of the DisplayPort core. More...
 
#define XDP_RX_CORE_ID   0x0FC
 DisplayPort protocol version and revision. More...
 

DPRX core registers: User video status.

#define XDP_RX_USER_FIFO_OVERFLOW   0x110
 Indicates an overflow in user FIFO. More...
 
#define XDP_RX_USER_VSYNC_STATE   0x114
 Provides a mechanism for the host processor to monitor the state of the video data path. More...
 

DPRX core registers: PHY configuration and status.

#define XDP_RX_PHY_CONFIG   0x200
 Transceiver PHY reset and configuration. More...
 
#define XDP_RX_PHY_STATUS   0x208
 Current PHY status. More...
 
#define XDP_RX_PHY_POWER_DOWN   0x210
 Control PHY power down. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING   0x214
 Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training. More...
 
#define XDP_RX_CDR_CONTROL_CONFIG   0x21C
 Control the configuration for clock and data recovery. More...
 
#define XDP_RX_BS_IDLE_TIME   0x220
 Blanking start symbol idle time - this value is loaded as a timeout counter for detecting cable disconnect or unplug events. More...
 
#define XDP_RX_GT_DRP_COMMAND   0x2A0
 Provides access to the GT DRP ports. More...
 
#define XDP_RX_GT_DRP_READ_DATA   0x2A4
 Provides access to GT DRP read data. More...
 
#define XDP_RX_GT_DRP_CH_STATUS   0x2A8
 Provides access to GT DRP channel status. More...
 

DPRX core registers: Audio.

#define XDP_RX_AUDIO_CONTROL   0x300
 Enables audio stream packets in main link. More...
 
#define XDP_RX_AUDIO_INFO_DATA(NUM)   (0x304 + 4 * (NUM - 1))
 Word formatted as per CEA 861-C info frame. More...
 
#define XDP_RX_AUDIO_MAUD   0x324
 M value of audio stream as decoded from audio time stamp packet. More...
 
#define XDP_RX_AUDIO_NAUD   0x328
 N value of audio stream as decoded from audio time stamp packet. More...
 
#define XDP_RX_AUDIO_STATUS   0x32C
 Status of audio stream. More...
 
#define XDP_RX_AUDIO_EXT_DATA(NUM)   (0x330 + 4 * (NUM - 1))
 Word formatted as per extension packet. More...
 

DPRX core registers: DPCD configuration space.

#define XDP_RX_DPCD_LINK_BW_SET   0x400
 Current link bandwidth setting as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_LANE_COUNT_SET   0x404
 Current lane count setting as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_ENHANCED_FRAME_EN   0x408
 Current setting for enhanced framing symbol mode as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_TRAINING_PATTERN_SET   0x40C
 Current training pattern setting as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET   0x410
 Current value of the link quality pattern field as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN   0x414
 Value of the output clock enable field as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_SCRAMBLING_DISABLE   0x418
 Value of the scrambling disable field as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT   0x41C
 Current value of the symbol error count select field as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_TRAINING_LANE_0_SET   0x420
 The RX DPCD value used by the TX during link training to configure the RX PHY lane 0. More...
 
#define XDP_RX_DPCD_TRAINING_LANE_1_SET   0x424
 The RX DPCD value used by the TX during link training to configure the RX PHY lane 1. More...
 
#define XDP_RX_DPCD_TRAINING_LANE_2_SET   0x428
 The RX DPCD value used by the TX during link training to configure the RX PHY lane 2. More...
 
#define XDP_RX_DPCD_TRAINING_LANE_3_SET   0x42C
 The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3. More...
 
#define XDP_RX_DPCD_DOWNSPREAD_CONTROL   0x430
 The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled. More...
 
#define XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET   0x434
 8B/10B encoding setting as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_SET_POWER_STATE   0x438
 Power state requested by the TX as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_LANE01_STATUS   0x43C
 Link training status for lanes 0 and 1 as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_LANE23_STATUS   0x440
 Link training status for lanes 2 and 3 as exposed in the RX DPCD. More...
 
#define XDP_RX_DPCD_SOURCE_OUI_VALUE
 
#define XDP_RX_DPCD_SYM_ERR_CNT01
 
#define XDP_RX_DPCD_SYM_ERR_CNT23
 

DPRX core registers: Main stream attributes for SST / MST STREAM1.

#define XDP_RX_STREAM1_MSA_START   0x500
 Start of the MSA registers for stream 1. More...
 
#define XDP_RX_MSA_HRES   0x500
 Number of active pixels per line (the horizontal resolution). More...
 
#define XDP_RX_MSA_HSPOL   0x504
 The horizontal sync polarity. More...
 
#define XDP_RX_MSA_HSWIDTH   0x508
 Width of the horizontal sync pulse. More...
 
#define XDP_RX_MSA_HSTART   0x50C
 Number of clocks between the leading edge of the horizontal sync and the start of active data. More...
 
#define XDP_RX_MSA_HTOTAL   0x510
 Total number of clocks in the horizontal framing period. More...
 
#define XDP_RX_MSA_VHEIGHT   0x514
 Number of active lines (the vertical resolution). More...
 
#define XDP_RX_MSA_VSPOL   0x518
 The vertical sync polarity. More...
 
#define XDP_RX_MSA_VSWIDTH   0x51C
 Width of the vertical sync pulse. More...
 
#define XDP_RX_MSA_VSTART   0x520
 Number of lines between the leading edge of the vertical sync and the first line of active data. More...
 
#define XDP_RX_MSA_VTOTAL   0x524
 Total number of lines in the video frame. More...
 
#define XDP_RX_MSA_MISC0   0x528
 Miscellaneous stream attributes. More...
 
#define XDP_RX_MSA_MISC1   0x52C
 Miscellaneous stream attributes. More...
 
#define XDP_RX_MSA_MVID   0x530
 Used to recover the video clock from the link clock. More...
 
#define XDP_RX_MSA_NVID   0x534
 Used to recover the video clock from the link clock. More...
 
#define XDP_RX_MSA_VBID   0x538
 The most recently received VB-ID value. More...
 

DPRX core registers: Main stream attributes for MST STREAM2, 3, and 4.

#define XDP_RX_STREAM2_MSA_START   0x540
 Start of the MSA registers for stream 2. More...
 
#define XDP_RX_STREAM2_MSA_START_OFFSET
 The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1. More...
 
#define XDP_RX_STREAM3_MSA_START   0x580
 Start of the MSA registers for stream 3. More...
 
#define XDP_RX_STREAM3_MSA_START_OFFSET
 The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1. More...
 
#define XDP_RX_STREAM4_MSA_START   0x5C0
 Start of the MSA registers for stream 4. More...
 
#define XDP_RX_STREAM4_MSA_START_OFFSET
 The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1. More...
 

DPRX core registers: DPCD registers for HDCP.

#define XDP_RX_DPCD_HDCP_TABLE   0x900
 HDCP register table (0x100 bytes). More...
 

DPRX core registers: MST field for sideband message buffers and the

virtual channel payload table.

#define XDP_RX_DOWN_REQ   0xA00
 Down request buffer address space. More...
 
#define XDP_RX_DOWN_REP   0xB00
 Down reply buffer address space. More...
 
#define XDP_RX_VC_PAYLOAD_TABLE   0x800
 Virtual channel payload table (0xFF bytes). More...
 
#define XDP_RX_VC_PAYLOAD_TABLE_ID_SLOT(SlotNum)   (XDP_RX_VC_PAYLOAD_TABLE + SlotNum)
 

DPRX core registers: Vendor specific DPCD.

#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD   0xE00
 User access to the source specific field as exposed in the RX DPCD (0xFF bytes). More...
 
#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD_REG(RegNum)   (XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD + (4 * RegNum))
 
#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD   0xF00
 User access to the sink specific field as exposed in the RX DPCD (0xFF bytes). More...
 
#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD_REG(RegNum)   (XDP_RX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum))
 

DPRX core masks, shifts, and register values.

#define XDP_RX_AUX_CLK_DIVIDER_VAL_MASK   0x00FF
 Clock divider value. More...
 
#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0xFF00
 AUX (noise) signal width filter. More...
 
#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8
 Shift bits for AUX signal width filter. More...
 
#define XDP_RX_LINE_RESET_DISABLE_MASK(Stream)   (1 << ((Stream) - XDP_TX_STREAM_ID1))
 Used to disable the end of the line reset to the internal video pipe. More...
 
#define XDP_RX_USER_PIXEL_WIDTH_1   0x1
 Single pixel wide interface. More...
 
#define XDP_RX_USER_PIXEL_WIDTH_2   0x2
 Dual pixel output mode. More...
 
#define XDP_RX_USER_PIXEL_WIDTH_4   0x4
 Quad pixel output mode. More...
 
#define XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK   0x00000001
 Mask the interrupt assertion for a resolution change, as detected from the MSA fields. More...
 
#define XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK   0x00000002
 Mask the interrupt assertion for a power state change. More...
 
#define XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK   0x00000004
 Mask the interrupt assertion for the no-video condition being detected after active video received. More...
 
#define XDP_RX_INTERRUPT_MASK_VBLANK_MASK   0x00000008
 Mask the interrupt assertion for the start of the blanking interval. More...
 
#define XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK   0x00000010
 Mask the interrupt assertion for training loss on active lanes. More...
 
#define XDP_RX_INTERRUPT_MASK_VIDEO_MASK   0x00000040
 Mask the interrupt assertion for a valid video frame being detected on the main link. More...
 
#define XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK   0x00000100
 Mask the interrupt assertion for an audio info packet being received. More...
 
#define XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK   0x00000200
 Mask the interrupt assertion for an audio extension packet being received. More...
 
#define XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK   0x00000400
 Mask the interrupt assertion for a virtual channel payload being allocated. More...
 
#define XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK   0x00000800
 Mask the interrupt assertion for a virtual channel payload being allocated. More...
 
#define XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK   0x00001000
 Mask the interrupt assertion for a downstream reply being ready. More...
 
#define XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK   0x00002000
 Mask the interrupt assertion for a downstream request being ready. More...
 
#define XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK   0x00004000
 Mask the interrupt assertion for link training completion. More...
 
#define XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK   0x00008000
 Mask the interrupt assertion for a change in bandwidth. More...
 
#define XDP_RX_INTERRUPT_MASK_TP1_MASK   0x00010000
 Mask the interrupt assertion for start of training pattern 1. More...
 
#define XDP_RX_INTERRUPT_MASK_TP2_MASK   0x00020000
 Mask the interrupt assertion for start of training pattern 2. More...
 
#define XDP_RX_INTERRUPT_MASK_TP3_MASK   0x00040000
 Mask the interrupt assertion for start of training pattern 3. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_DEBUG_WRITE_MASK   0x00080000
 Mask the interrupt for a write to any HDCP debug register. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_AKSV_WRITE_MASK   0x00100000
 Mask the interrupt for a write to the HDCP AKSV MSB register. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_AN_WRITE_MASK   0x00200000
 Mask the interrupt for a write to the HDCP An MSB register. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_AINFO_WRITE_MASK   0x00400000
 Mask the interrupt for a write to the HDCP AInfo register. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_RO_READ_MASK   0x00800000
 Mask the interrupt for a read of the HDCP Ro register. More...
 
#define XDP_RX_INTERRUPT_MASK_HDCP_BINFO_READ_MASK   0x01000000
 Mask the interrupt for a read of the HDCP BInfo register. More...
 
#define XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK   0x08000000
 Mask the interrupt assertion caused for an audio packet overflow. More...
 
#define XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK   0x10000000
 Mask the interrupt assertion for the RX's DPCD payload allocation registers that have been updated as part of (de-)allocation or partial deletion. More...
 
#define XDP_RX_INTERRUPT_MASK_ACT_RX_MASK   0x20000000
 Mask the interrupt assertion for the ACT sequence being received. More...
 
#define XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK   0x40000000
 Mask the interrupt assertion for the start of a CRC test. More...
 
#define XDP_RX_INTERRUPT_MASK_UNPLUG_MASK   0x80000000
 Mask the unplug event interrupt. More...
 
#define XDP_RX_INTERRUPT_MASK_ALL_MASK   0xF9FFFFFF
 Mask all interrupts. More...
 
#define XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK   0x1
 When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally. More...
 
#define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK   0x2
 When set, the long I2C write data transfers are responded to using DEFER instead of partial ACKs. More...
 
#define XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK   0x4
 When set, I2C DEFERs will be sent as AUX DEFERs to the source device. More...
 
#define XDP_RX_SOFT_RESET_VIDEO_MASK   0x01
 Reset the video logic. More...
 
#define XDP_RX_SOFT_RESET_AUX_MASK   0x80
 Reset the AUX logic. More...
 
#define XDP_RX_HPD_INTERRUPT_ASSERT_MASK   0x00000001
 Instructs the RX core to assert an interrupt to the TX using the HPD signal. More...
 
#define XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK   0xFFFF0000
 The length of the HPD pulse to generate (in microseconds). More...
 
#define XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT   16
 Shift bits for the HPD pulse length. More...
 
#define XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK   XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK
 Interrupt caused by a resolution change, as detected from the MSA fields. More...
 
#define XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK   XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK
 Interrupt caused by a power state change. More...
 
#define XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK   XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK
 Interrupt caused by the no-video condition being detected after active video received. More...
 
#define XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK   XDP_RX_INTERRUPT_MASK_VBLANK_MASK
 Interrupt caused by the start of the blanking interval. More...
 
#define XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK   XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK
 Interrupt caused by training loss on active lanes. More...
 
#define XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK   XDP_RX_INTERRUPT_MASK_VIDEO_MASK
 Interrupt caused by a valid video frame being detected on the main link. More...
 
#define XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK   XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK
 Interrupt caused by an audio info packet being received. More...
 
#define XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK   XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK
 Interrupt caused by an audio extension packet being received. More...
 
#define XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK   XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK
 Interrupt caused by a virtual channel payload being allocated. More...
 
#define XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK   XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK
 Interrupt caused by a virtual channel payload being allocated. More...
 
#define XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK   XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK
 Interrupt caused by a downstream reply being ready. More...
 
#define XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK   XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK
 Interrupt caused by a downstream request being ready. More...
 
#define XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK   XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK
 Interrupt caused by link training completion. More...
 
#define XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK   XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK
 Interrupt caused by a change in bandwidth. More...
 
#define XDP_RX_INTERRUPT_CAUSE_TP1_MASK   XDP_RX_INTERRUPT_MASK_TP1_MASK
 Interrupt caused by the start of training pattern 1. More...
 
#define XDP_RX_INTERRUPT_CAUSE_TP2_MASK   XDP_RX_INTERRUPT_MASK_TP2_MASK
 Interrupt caused by the start of training pattern 2. More...
 
#define XDP_RX_INTERRUPT_CAUSE_TP3_MASK   XDP_RX_INTERRUPT_MASK_TP3_MASK
 Interrupt caused by the start of training pattern 3. More...
 
#define XDP_RX_INTERRUPT_CAUSE_AUDIO_OVER_MASK   XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK
 Interrupt caused by an audio packet overflow. More...
 
#define XDP_RX_INTERRUPT_CAUSE_PAYLOAD_ALLOC_MASK   XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK
 Interrupt caused by the RX's DPCD payload allocation registers has been updated as part of (de-)allocation or partial deletion. More...
 
#define XDP_RX_INTERRUPT_CAUSE_ACT_RX_MASK   XDP_RX_INTERRUPT_MASK_ACT_RX_MASK
 Interrupt caused by the ACT sequence being received. More...
 
#define XDP_RX_INTERRUPT_CAUSE_CRC_TEST_MASK   XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK
 Interrupt caused by the start of a CRC test. More...
 
#define XDP_RX_INTERRUPT_CAUSE_UNPLUG_MASK   XDP_RX_INTERRUPT_MASK_UNPLUG_MASK
 Interrupt caused by the an unplug event. More...
 
#define XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK(Stream)   (0x00001 << ((Stream - 2) * 6))
 Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK(Stream)   (0x00002 << ((Stream - 2) * 6))
 Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK(Stream)   (0x00004 << ((Stream - 2) * 6))
 Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK(Stream)   (0x00008 << ((Stream - 2) * 6))
 Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK(Stream)   (0x00010 << ((Stream - 2) * 6))
 Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or. More...
 
#define XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK(Stream)   (0x00020 << ((Stream - 2) * 6))
 Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream)
 Interrupt caused by an audio extension packet being received for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream)
 Interrupt caused by an audio info packet being received for stream 2, 3, or. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream)
 Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream)
 Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream)
 Interrupt caused by the start of the blanking interval for stream 2, 3, or. More...
 
#define XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream)   XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream)
 Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4. More...
 
#define XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK   0x00FF
 Specifies the number of clock cycles the horizontal sync pulse is asserted. More...
 
#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK   0xFF00
 Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch). More...
 
#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT   8
 Shift bits for the front porch. More...
 
#define XDP_RX_MST_ALLOC_VCP_ID_MASK   0x00003F
 The virtual channel payload ID that was issued as part of the most recent ALLOCATE_PAYLOAD down request. More...
 
#define XDP_RX_MST_ALLOC_START_TS_MASK   0x003F00
 The starting time slot that was issued as part of the most recent ALLOCATE_PAYLOAD down request. More...
 
#define XDP_RX_MST_ALLOC_START_TS_SHIFT   8
 Shift bits for the starting time slot. More...
 
#define XDP_RX_MST_ALLOC_COUNT_TS_MASK   0x3F0000
 The time slot count that was issued as part of part of the most recent ALLOCATE_PAYLOAD down request. More...
 
#define XDP_RX_MST_ALLOC_COUNT_TS_SHIFT   16
 Shift bits for the time slot count. More...
 
#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK   0x01
 Indicates that a new command is present in the REMOTE_CMD register. More...
 
#define XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK   0x02
 Reflects the SINK_SPECIFIC_IRQ state. More...
 
#define XDP_RX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK   0x04
 Generates a CP IRQ event. More...
 
#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK   0x10
 Indicates a new DOWN_REPLY buffer message is ready. More...
 
#define XDP_RX_OVER_LINK_BW_SET_162GBPS   0x06
 1.62 Gbps link rate. More...
 
#define XDP_RX_OVER_LINK_BW_SET_270GBPS   0x0A
 2.70 Gbps link rate. More...
 
#define XDP_RX_OVER_LINK_BW_SET_540GBPS   0x14
 5.40 Gbps link rate. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_MASK   0x1F
 The lane count override value. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_1   0x1
 Lane count of 1. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_2   0x2
 Lane count of 2. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_4   0x4
 Lane count of 4. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK   0x40
 Capability override for training pattern 3. More...
 
#define XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK   0x80
 Capability override for enhanced framing. More...
 
#define XDP_RX_OVER_TP_SET_TP_SELECT_MASK   0x0003
 Training pattern select override. More...
 
#define XDP_RX_OVER_TP_SET_LQP_SET_MASK   0x000C
 Link quality pattern set override. More...
 
#define XDP_RX_OVER_TP_SET_LQP_SET_SHIFT   2
 Shift bits for link quality pattern set override. More...
 
#define XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK   0x0010
 Recovered clock output enable override. More...
 
#define XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK   0x0020
 Scrambling disable override. More...
 
#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK   0x00C0
 Symbol error count override. More...
 
#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT   6
 Shift bits for symbol error count override. More...
 
#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK   0xFF00
 Training AUX read interval override. More...
 
#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT   8
 Shift bits for training AUX read interval override. More...
 
#define XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK   0x03
 Voltage swing set override. More...
 
#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
 Maximum voltage swing override. More...
 
#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK   0x18
 Pre-emphasis set override. More...
 
#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT   3
 Shift bits for pre-emphasis set override. More...
 
#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
 Maximum pre-emphasis override. More...
 
#define XDP_RX_MST_CAP_ENABLE_MASK   0x001
 When set to 1, enables MST mode in the RX, or disables it when 0. More...
 
#define XDP_RX_MST_CAP_SOFT_VCP_MASK   0x002
 When set to 1, enables software control over the virtual channel payload table. More...
 
#define XDP_RX_MST_CAP_OVER_ACT_MASK   0x004
 When set to 1, overrides the ACT trigger. More...
 
#define XDP_RX_MST_CAP_VCP_UPDATE_MASK   0x010
 When set to 1, indicates to the upstream device that the virtual channel payload table has been updated. More...
 
#define XDP_RX_MST_CAP_VCP_CLEAR_MASK   0x100
 When set to 1, clears the virtual channel payload table. More...
 
#define XDP_RX_VERSION_INTER_REV_MASK   0x0000000F
 Internal revision. More...
 
#define XDP_RX_VERSION_CORE_PATCH_MASK   0x00000030
 Core patch details. More...
 
#define XDP_RX_VERSION_CORE_PATCH_SHIFT   8
 Shift bits for core patch details. More...
 
#define XDP_RX_VERSION_CORE_VER_REV_MASK   0x000000C0
 Core version revision. More...
 
#define XDP_RX_VERSION_CORE_VER_REV_SHIFT   12
 Shift bits for core version revision. More...
 
#define XDP_RX_VERSION_CORE_VER_MNR_MASK   0x00000F00
 Core minor version. More...
 
#define XDP_RX_VERSION_CORE_VER_MNR_SHIFT   16
 Shift bits for core minor version. More...
 
#define XDP_RX_VERSION_CORE_VER_MJR_MASK   0x0000F000
 Core major version. More...
 
#define XDP_RX_VERSION_CORE_VER_MJR_SHIFT   24
 Shift bits for core major version. More...
 
#define XDP_RX_CORE_ID_TYPE_MASK   0x0000000F
 Core type. More...
 
#define XDP_RX_CORE_ID_TYPE_TX   0x0
 Core is a transmitter. More...
 
#define XDP_RX_CORE_ID_TYPE_RX   0x1
 Core is a receiver. More...
 
#define XDP_RX_CORE_ID_DP_REV_MASK   0x000000F0
 DisplayPort protocol revision. More...
 
#define XDP_RX_CORE_ID_DP_REV_SHIFT   8
 Shift bits for DisplayPort protocol revision. More...
 
#define XDP_RX_CORE_ID_DP_MNR_VER_MASK   0x00000F00
 DisplayPort protocol minor version. More...
 
#define XDP_RX_CORE_ID_DP_MNR_VER_SHIFT   16
 Shift bits for DisplayPort protocol major version. More...
 
#define XDP_RX_CORE_ID_DP_MJR_VER_MASK   0x0000F000
 DisplayPort protocol major version. More...
 
#define XDP_RX_CORE_ID_DP_MJR_VER_SHIFT   24
 Shift bits for DisplayPort protocol major version. More...
 
#define XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK(Stream)   (Stream)
 Indicates that the internal FIFO has detected on overflow condition for the specified stream. More...
 
#define XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK(Stream)   (Stream << 4)
 Indicates that the video unpack FIFO has overflown for the specified stream. More...
 
#define XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK(Stream)   (Stream << 8)
 Indicates that the video timing FIFO has overflown for the specified stream. More...
 
#define XDP_RX_USER_VSYNC_STATE_STREAMX_MASK(Stream)   (Stream)
 The state of the vertical sync pulse for the specified stream. More...
 
#define XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x00000000
 Release reset. More...
 
#define XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK   0x00000001
 Hold the GTPLL in reset. More...
 
#define XDP_RX_PHY_CONFIG_GTRX_RESET_MASK   0x00000002
 Hold GTRXRESET in reset. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK   0x00000100
 Hold RX_PHY_PMA reset. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK   0x00000200
 Hold RX_PHY_PCS reset. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK   0x00000400
 Hold RX_PHY_BUF reset. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK   0x00000800
 Hold RX_PHY_DFE_LPM reset. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK   0x00001000
 Set RX_PHY_POLARITY. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK   0x0000E000
 Set RX_PHY_LOOPBACK. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK   0x00010000
 Set RX_PHY_EYESCANRESET. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK   0x00020000
 Set RX_PHY_ EYESCANTRIGGER. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK   0x00040000
 Set RX_PHY_PRBSCNTRESET. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK   0x00080000
 Set RX_PHY_RXLPMHFHOLD. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK   0x00100000
 Set RX_PHY_RXLPMLFHOLD. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK   0x00200000
 Set RX_PHY_ RXLPMHFOVERDEN. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK   0x00400000
 Set RX_PHY_CDRHOLD. More...
 
#define XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK   0x00800000
 Issue reset at every training iteration. More...
 
#define XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK   0x01000000
 Issue reset at every link rate change. More...
 
#define XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK   0x02000000
 Issue reset at start of training pattern 1. More...
 
#define XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK   0x04000000
 Enable the individual lane polarity. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK   0x08000000
 Configure RX_PHY_POLARITY for lane 0. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK   0x10000000
 Configure RX_PHY_POLARITY for lane 1. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK   0x20000000
 Configure RX_PHY_POLARITY for lane 2. More...
 
#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK   0x40000000
 Configure RX_PHY_POLARITY for lane 3. More...
 
#define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK   0x00000003
 Reset GT and PHY. More...
 
#define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003
 Reset done for lanes 0 and 1. More...
 
#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C
 Reset done for lanes 2 and 3. More...
 
#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT   2
 Shift bits for reset done for lanes 2 and 3. More...
 
#define XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010
 PLL locked for lanes 0 and 1. More...
 
#define XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020
 PLL locked for lanes 2 and 3. More...
 
#define XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040
 FPGA fabric clock PLL locked. More...
 
#define XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK   0x00000080
 Receiver clock locked. More...
 
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK   0x00000100
 PRBS error on lane 0. More...
 
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK   0x00000200
 PRBS error on lane 1. More...
 
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK   0x00000400
 PRBS error on lane 2. More...
 
#define XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK   0x00000800
 PRBS error on lane 3. More...
 
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK   0x00001000
 RX voltage low on lane 0. More...
 
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK   0x00002000
 RX voltage low on lane. More...
 
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK   0x00004000
 RX voltage low on lane. More...
 
#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK   0x00008000
 RX voltage low on lane. More...
 
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK   0x00010000
 Lane alignment status for lane 0. More...
 
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK   0x00020000
 Lane alignment status for lane 1. More...
 
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK   0x00040000
 Lane alignment status for lane 2. More...
 
#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK   0x00080000
 Lane alignment status for lane 3. More...
 
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK   0x00100000
 Symbol lock status for lane 0. More...
 
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK   0x00200000
 Symbol lock status for lane 1. More...
 
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK   0x00400000
 Symbol lock status for lane 2. More...
 
#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK   0x00800000
 Symbol lock status for lane 3. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK   0x03000000
 RX buffer status lane 0. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT   24
 Shift bits for RX buffer status lane 0. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK   0x0C000000
 RX buffer status lane 1. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT   26
 Shift bits for RX buffer status lane 1. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK   0x30000000
 RX buffer status lane 2. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT   28
 Shift bits for RX buffer status lane 2. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK   0xC0000000
 RX buffer status lane 3. More...
 
#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT   30
 Shift bits for RX buffer status lane 3. More...
 
#define XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK   0x00000013
 Lanes 0 and 1 are ready. More...
 
#define XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F
 All lanes are ready. More...
 
#define XDP_RX_PHY_POWER_DOWN_LANE_0_MASK   0x1
 Power down the PHY for lane 0. More...
 
#define XDP_RX_PHY_POWER_DOWN_LANE_1_MASK   0x2
 Power down the PHY for lane. More...
 
#define XDP_RX_PHY_POWER_DOWN_LANE_2_MASK   0x4
 Power down the PHY for lane. More...
 
#define XDP_RX_PHY_POWER_DOWN_LANE_3_MASK   0x8
 Power down the PHY for lane. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_MIN_MASK   0x000003
 The minimum voltage swing level. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_MASK   0x00000C
 Clock recovery options. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_SHIFT   2
 Shift bits for clock recovery options. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC   0x0
 Increment voltage swing adjust request every training iteration. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC_4CNT   0x1
 Increment voltage swing adjust request every 4 or VS_SWEEP_CNT iterations. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_HOLD   0x2
 Hold adjust request to SET_VS. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_NA   0x3
 Not applicable. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_MASK   0x000070
 Voltage swing sweep count. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_SHIFT   4
 Shift bits for voltage swing sweep count. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_MASK   0x000300
 Set voltage swing level. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_SHIFT   8
 Shift bits for voltage swing setting. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_MASK   0x000C00
 Channel equalization options. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_SHIFT   10
 Shift bits for channel equalization options. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_INC   0x0
 Increment pre-emphasis adjust request every training iteration until maximum level, SET_PE, is reached. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_HOLD   0x1
 Hold adjust request to SET_PE. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_TABLE   0x2
 Pick pre-emphasis values from PE_TABLE. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_VS_NA   0x3
 Not applicable. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_MASK   0x003000
 Set pre-emphasis level. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_SHIFT   12
 Shift bits for pre-emphasis setting. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_MASK(Iteration)   (0x3 << (14 + ((Iteration - 1) * 2)))
 Table specifying what pre-emphasis level to request for each training iteration. More...
 
#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_SHIFT(Iteration)   (14 + ((Iteration - 1) * 2))
 Shift bits for pre-emphasis table. More...
 
#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_TO_MASK   0x000FFFFF
 Controls the CDR tDLOCK timeout value. More...
 
#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_DP159   0x1388
 CDR tDLOCK calibration value using DP159. More...
 
#define XDP_RX_CDR_CONTROL_CONFIG_DFE_CTRL_MASK   0x80000000
 Use DFE control. More...
 
#define XDP_RX_CDR_CONTROL_CONFIG_DISABLE_TIMEOUT   0X40000000
 Timeout for MST mode. More...
 

DisplayPort Configuration Data: Receiver capability field.

Address mapping for the DisplayPort Configuration Data (DPCD) of the downstream device.

#define XDP_DPCD_REV   0x00000
 
#define XDP_DPCD_MAX_LINK_RATE   0x00001
 
#define XDP_DPCD_MAX_LANE_COUNT   0x00002
 
#define XDP_DPCD_MAX_DOWNSPREAD   0x00003
 
#define XDP_DPCD_NORP_PWR_V_CAP   0x00004
 
#define XDP_DPCD_DOWNSP_PRESENT   0x00005
 
#define XDP_DPCD_ML_CH_CODING_CAP   0x00006
 
#define XDP_DPCD_DOWNSP_COUNT_MSA_OUI   0x00007
 
#define XDP_DPCD_RX_PORT0_CAP_0   0x00008
 
#define XDP_DPCD_RX_PORT0_CAP_1   0x00009
 
#define XDP_DPCD_RX_PORT1_CAP_0   0x0000A
 
#define XDP_DPCD_RX_PORT1_CAP_1   0x0000B
 
#define XDP_DPCD_I2C_SPEED_CTL_CAP   0x0000C
 
#define XDP_DPCD_EDP_CFG_CAP   0x0000D
 
#define XDP_DPCD_TRAIN_AUX_RD_INTERVAL   0x0000E
 
#define XDP_DPCD_ADAPTER_CAP   0x0000F
 
#define XDP_DPCD_FAUX_CAP   0x00020
 
#define XDP_DPCD_MSTM_CAP   0x00021
 
#define XDP_DPCD_NUM_AUDIO_EPS   0x00022
 
#define XDP_DPCD_AV_GRANULARITY   0x00023
 
#define XDP_DPCD_AUD_DEC_LAT_7_0   0x00024
 
#define XDP_DPCD_AUD_DEC_LAT_15_8   0x00025
 
#define XDP_DPCD_AUD_PP_LAT_7_0   0x00026
 
#define XDP_DPCD_AUD_PP_LAT_15_8   0x00027
 
#define XDP_DPCD_VID_INTER_LAT   0x00028
 
#define XDP_DPCD_VID_PROG_LAT   0x00029
 
#define XDP_DPCD_REP_LAT   0x0002A
 
#define XDP_DPCD_AUD_DEL_INS_7_0   0x0002B
 
#define XDP_DPCD_AUD_DEL_INS_15_8   0x0002C
 
#define XDP_DPCD_AUD_DEL_INS_23_16   0x0002D
 
#define XDP_DPCD_GUID   0x00030
 
#define XDP_DPCD_RX_GTC_VALUE_7_0   0x00054
 
#define XDP_DPCD_RX_GTC_VALUE_15_8   0x00055
 
#define XDP_DPCD_RX_GTC_VALUE_23_16   0x00056
 
#define XDP_DPCD_RX_GTC_VALUE_31_24   0x00057
 
#define XDP_DPCD_RX_GTC_MSTR_REQ   0x00058
 
#define XDP_DPCD_RX_GTC_FREQ_LOCK_DONE   0x00059
 
#define XDP_DPCD_DOWNSP_0_CAP   0x00080
 
#define XDP_DPCD_DOWNSP_1_CAP   0x00081
 
#define XDP_DPCD_DOWNSP_2_CAP   0x00082
 
#define XDP_DPCD_DOWNSP_3_CAP   0x00083
 
#define XDP_DPCD_DOWNSP_0_DET_CAP   0x00080
 
#define XDP_DPCD_DOWNSP_1_DET_CAP   0x00084
 
#define XDP_DPCD_DOWNSP_2_DET_CAP   0x00088
 
#define XDP_DPCD_DOWNSP_3_DET_CAP   0x0008C
 

DisplayPort Configuration Data: Link configuration field.

#define XDP_DPCD_LINK_BW_SET   0x00100
 
#define XDP_DPCD_LANE_COUNT_SET   0x00101
 
#define XDP_DPCD_TP_SET   0x00102
 
#define XDP_DPCD_TRAINING_LANE0_SET   0x00103
 
#define XDP_DPCD_TRAINING_LANE1_SET   0x00104
 
#define XDP_DPCD_TRAINING_LANE2_SET   0x00105
 
#define XDP_DPCD_TRAINING_LANE3_SET   0x00106
 
#define XDP_DPCD_DOWNSPREAD_CTRL   0x00107
 
#define XDP_DPCD_ML_CH_CODING_SET   0x00108
 
#define XDP_DPCD_I2C_SPEED_CTL_SET   0x00109
 
#define XDP_DPCD_EDP_CFG_SET   0x0010A
 
#define XDP_DPCD_LINK_QUAL_LANE0_SET   0x0010B
 
#define XDP_DPCD_LINK_QUAL_LANE1_SET   0x0010C
 
#define XDP_DPCD_LINK_QUAL_LANE2_SET   0x0010D
 
#define XDP_DPCD_LINK_QUAL_LANE3_SET   0x0010E
 
#define XDP_DPCD_TRAINING_LANE0_1_SET2   0x0010F
 
#define XDP_DPCD_TRAINING_LANE2_3_SET2   0x00110
 
#define XDP_DPCD_MSTM_CTRL   0x00111
 
#define XDP_DPCD_AUDIO_DELAY_7_0   0x00112
 
#define XDP_DPCD_AUDIO_DELAY_15_8   0x00113
 
#define XDP_DPCD_AUDIO_DELAY_23_6   0x00114
 
#define XDP_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED   0x00118
 
#define XDP_DPCD_FAUX_MODE_CTRL   0x00120
 
#define XDP_DPCD_FAUX_FORWARD_CH_DRIVE_SET   0x00121
 
#define XDP_DPCD_BACK_CH_STATUS   0x00122
 
#define XDP_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT   0x00123
 
#define XDP_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME   0x00125
 
#define XDP_DPCD_TX_GTC_VALUE_7_0   0x00154
 
#define XDP_DPCD_TX_GTC_VALUE_15_8   0x00155
 
#define XDP_DPCD_TX_GTC_VALUE_23_16   0x00156
 
#define XDP_DPCD_TX_GTC_VALUE_31_24   0x00157
 
#define XDP_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN   0x00158
 
#define XDP_DPCD_TX_GTC_FREQ_LOCK_DONE   0x00159
 
#define XDP_DPCD_ADAPTER_CTRL   0x001A0
 
#define XDP_DPCD_BRANCH_DEVICE_CTRL   0x001A1
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_SET   0x001C0
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT   0x001C1
 
#define XDP_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT   0x001C2
 

DisplayPort Configuration Data: Link/sink status field.

#define XDP_DPCD_SINK_COUNT   0x00200
 
#define XDP_DPCD_DEVICE_SERVICE_IRQ   0x00201
 
#define XDP_DPCD_STATUS_LANE_0_1   0x00202
 
#define XDP_DPCD_STATUS_LANE_2_3   0x00203
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED   0x00204
 
#define XDP_DPCD_SINK_STATUS   0x00205
 
#define XDP_DPCD_ADJ_REQ_LANE_0_1   0x00206
 
#define XDP_DPCD_ADJ_REQ_LANE_2_3   0x00207
 
#define XDP_DPCD_TRAINING_SCORE_LANE_0   0x00208
 
#define XDP_DPCD_TRAINING_SCORE_LANE_1   0x00209
 
#define XDP_DPCD_TRAINING_SCORE_LANE_2   0x0020A
 
#define XDP_DPCD_TRAINING_SCORE_LANE_3   0x0020B
 
#define XDP_DPCD_ADJ_REQ_PC2   0x0020C
 
#define XDP_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT   0x0020D
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0   0x00210
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1   0x00212
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2   0x00214
 
#define XDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3   0x00216
 

DisplayPort Configuration Data: Automated testing sub-field.

#define XDP_DPCD_FAUX_FORWARD_CH_STATUS   0x00280
 
#define XDP_DPCD_FAUX_BACK_CH_DRIVE_SET   0x00281
 
#define XDP_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL   0x00282
 
#define XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS   0x002C0
 
#define XDP_DPCD_VC_PAYLOAD_ID_SLOT(SlotNum)   (XDP_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
 

DisplayPort Configuration Data: Sink control field.

#define XDP_DPCD_SET_POWER_DP_PWR_VOLTAGE   0x00600
 

DisplayPort Configuration Data: Sideband message buffers.

#define XDP_DPCD_DOWN_REQ   0x01000
 
#define XDP_DPCD_UP_REP   0x01200
 
#define XDP_DPCD_DOWN_REP   0x01400
 
#define XDP_DPCD_UP_REQ   0x01600
 

DisplayPort Configuration Data: Event status indicator field.

#define XDP_DPCD_SINK_COUNT_ESI   0x02002
 
#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x02003
 
#define XDP_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x02004
 
#define XDP_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0   0x02005
 
#define XDP_DPCD_SINK_LANE0_1_STATUS   0x0200C
 
#define XDP_DPCD_SINK_LANE2_3_STATUS   0x0200D
 
#define XDP_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI   0x0200E
 
#define XDP_DPCD_SINK_STATUS_ESI   0x0200F
 

DisplayPort Configuration Data: Field addresses and sizes.

#define XDP_DPCD_RECEIVER_CAP_FIELD_START   XDP_DPCD_REV
 
#define XDP_DPCD_RECEIVER_CAP_FIELD_SIZE   0x100
 
#define XDP_DPCD_LINK_CFG_FIELD_START   XDP_DPCD_LINK_BW_SET
 
#define XDP_DPCD_LINK_CFG_FIELD_SIZE   0x100
 
#define XDP_DPCD_LINK_SINK_STATUS_FIELD_START   XDP_DPCD_SINK_COUNT
 
#define XDP_DPCD_LINK_SINK_STATUS_FIELD_SIZE   0x17
 

DisplayPort Configuration Data: Receiver capability field masks,

shifts, and register values.

#define XDP_DPCD_REV_MNR_MASK   0x0F
 
#define XDP_DPCD_REV_MJR_MASK   0xF0
 
#define XDP_DPCD_REV_MJR_SHIFT   4
 
#define XDP_DPCD_MAX_LINK_RATE_162GBPS   0x06
 
#define XDP_DPCD_MAX_LINK_RATE_270GBPS   0x0A
 
#define XDP_DPCD_MAX_LINK_RATE_540GBPS   0x14
 
#define XDP_DPCD_MAX_LANE_COUNT_MASK   0x1F
 
#define XDP_DPCD_MAX_LANE_COUNT_1   0x01
 
#define XDP_DPCD_MAX_LANE_COUNT_2   0x02
 
#define XDP_DPCD_MAX_LANE_COUNT_4   0x04
 
#define XDP_DPCD_TPS3_SUPPORT_MASK   0x40
 
#define XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK   0x80
 
#define XDP_DPCD_MAX_DOWNSPREAD_MASK   0x01
 
#define XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK   0x40
 
#define XDP_DPCD_DOWNSP_PRESENT_MASK   0x01
 
#define XDP_DPCD_DOWNSP_TYPE_MASK   0x06
 
#define XDP_DPCD_DOWNSP_TYPE_SHIFT   1
 
#define XDP_DPCD_DOWNSP_TYPE_DP   0x0
 
#define XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII   0x1
 
#define XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP   0x2
 
#define XDP_DPCD_DOWNSP_TYPE_OTHERS   0x3
 
#define XDP_DPCD_DOWNSP_FORMAT_CONV_MASK   0x08
 
#define XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK   0x10
 
#define XDP_DPCD_ML_CH_CODING_MASK   0x01
 
#define XDP_DPCD_DOWNSP_COUNT_MASK   0x0F
 
#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK   0x40
 
#define XDP_DPCD_OUI_SUPPORT_MASK   0x80
 
#define XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK   0x02
 
#define XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK   0x04
 
#define XDP_DPCD_I2C_SPEED_CTL_NONE   0x00
 
#define XDP_DPCD_I2C_SPEED_CTL_1KBIPS   0x01
 
#define XDP_DPCD_I2C_SPEED_CTL_5KBIPS   0x02
 
#define XDP_DPCD_I2C_SPEED_CTL_10KBIPS   0x04
 
#define XDP_DPCD_I2C_SPEED_CTL_100KBIPS   0x08
 
#define XDP_DPCD_I2C_SPEED_CTL_400KBIPS   0x10
 
#define XDP_DPCD_I2C_SPEED_CTL_1MBIPS   0x20
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_100_400US   0x00
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_4MS   0x01
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_8MS   0x02
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_12MS   0x03
 
#define XDP_DPCD_TRAIN_AUX_RD_INT_16MS   0x04
 
#define XDP_DPCD_FAUX_CAP_MASK   0x01
 
#define XDP_DPCD_MST_CAP_MASK   0x01
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_MASK   0x07
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DP   0x0
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_AVGA   0x1
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DVI   0x2
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_HDMI   0x3
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_OTHERS   0x4
 
#define XDP_DPCD_DOWNSP_X_CAP_TYPE_DPPP   0x5
 
#define XDP_DPCD_DOWNSP_X_CAP_HPD_MASK   0x80
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK   0xF0
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT   4
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60   0x1
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50   0x2
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60   0x3
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50   0x4
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60   0x5
 
#define XDP_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50   0x7
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK   0x03
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_8   0x0
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_10   0x1
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_12   0x2
 
#define XDP_DPCD_DOWNSP_X_DCAP_MAX_BPC_16   0x3
 
#define XDP_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK   0x01
 
#define XDP_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK   0x02
 
#define XDP_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK   0x04
 

DisplayPort Configuration Data: Link configuration field masks,

shifts, and register values.

#define XDP_DPCD_LINK_BW_SET_162GBPS   0x06
 
#define XDP_DPCD_LINK_BW_SET_270GBPS   0x0A
 
#define XDP_DPCD_LINK_BW_SET_540GBPS   0x14
 
#define XDP_DPCD_LANE_COUNT_SET_MASK   0x1F
 
#define XDP_DPCD_LANE_COUNT_SET_1   0x01
 
#define XDP_DPCD_LANE_COUNT_SET_2   0x02
 
#define XDP_DPCD_LANE_COUNT_SET_4   0x04
 
#define XDP_DPCD_ENHANCED_FRAME_EN_MASK   0x80
 
#define XDP_DPCD_TP_SEL_MASK   0x03
 
#define XDP_DPCD_TP_SEL_OFF   0x0
 
#define XDP_DPCD_TP_SEL_TP1   0x1
 
#define XDP_DPCD_TP_SEL_TP2   0x2
 
#define XDP_DPCD_TP_SEL_TP3   0x3
 
#define XDP_DPCD_TP_SET_LQP_MASK   0x06
 
#define XDP_DPCD_TP_SET_LQP_SHIFT   2
 
#define XDP_DPCD_TP_SET_LQP_OFF   0x0
 
#define XDP_DPCD_TP_SET_LQP_D102_TEST   0x1
 
#define XDP_DPCD_TP_SET_LQP_SER_MES   0x2
 
#define XDP_DPCD_TP_SET_LQP_PRBS7   0x3
 
#define XDP_DPCD_TP_SET_REC_CLK_OUT_EN_MASK   0x10
 
#define XDP_DPCD_TP_SET_SCRAMB_DIS_MASK   0x20
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_MASK   0xC0
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_SHIFT   6
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE   0x0
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_DE   0x1
 
#define XDP_DPCD_TP_SET_SE_COUNT_SEL_ISE   0x2
 
#define XDP_DPCD_TRAINING_LANEX_SET_VS_MASK   0x03
 
#define XDP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK   0x04
 
#define XDP_DPCD_TRAINING_LANEX_SET_PE_MASK   0x18
 
#define XDP_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
 
#define XDP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK   0x20
 
#define XDP_DPCD_SPREAD_AMP_MASK   0x10
 
#define XDP_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK   0x80
 
#define XDP_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK   0x03
 
#define XDP_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK   0x04
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK   0x30
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT   4
 
#define XDP_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK   0x40
 
#define XDP_DPCD_MST_EN_MASK   0x01
 
#define XDP_DPCD_UP_REQ_EN_MASK   0x02
 
#define XDP_DPCD_UP_IS_SRC_MASK   0x03
 

DisplayPort Configuration Data: Link/sink status field masks, shifts,

and register values.

#define XDP_DPCD_SINK_COUNT_LOW_MASK   0x3F
 
#define XDP_DPCD_SINK_CP_READY_MASK   0x40
 
#define XDP_DPCD_SINK_COUNT_HIGH_MASK   0x80
 
#define XDP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT   1
 
#define XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK   0x01
 
#define XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK   0x02
 
#define XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK   0x04
 
#define XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK   0x10
 
#define XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK   0x20
 
#define XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK   0x40
 
#define XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK   0x01
 
#define XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK   0x02
 
#define XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK   0x04
 
#define XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK   0x10
 
#define XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK   0x20
 
#define XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK   0x40
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK   0x01
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK   0x40
 
#define XDP_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK   0x80
 
#define XDP_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK   0x01
 
#define XDP_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK   0x02
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK   0x03
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK   0x0C
 
#define XDP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT   2
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK   0x30
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT   4
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK   0xC0
 
#define XDP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT   6
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_0_MASK   0x03
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_MASK   0x0C
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT   2
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_MASK   0x30
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT   4
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_MASK   0xC0
 
#define XDP_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT   6
 

Extended Display Identification Data: Field addresses and sizes.

Address mapping for the Extended Display Identification Data (EDID) of the downstream device.

#define XDP_SEGPTR_ADDR   0x30
 
#define XDP_EDID_ADDR   0x50
 
#define XDP_EDID_BLOCK_SIZE   128
 
#define XDP_EDID_DTD_DD(Num)   (0x36 + (18 * Num))
 
#define XDP_EDID_PTM   XDP_EDID_DTD_DD(0)
 
#define XDP_EDID_EXT_BLOCK_COUNT   0x7E
 

Extended Display Identification Data: Register offsets for the

Tiled Display Topology (TDT) section data block.

#define XDP_EDID_DTD_PIXEL_CLK_KHZ_LSB   0x00
 
#define XDP_EDID_DTD_PIXEL_CLK_KHZ_MSB   0x01
 
#define XDP_EDID_DTD_HRES_LSB   0x02
 
#define XDP_EDID_DTD_HBLANK_LSB   0x03
 
#define XDP_EDID_DTD_HRES_HBLANK_U4   0x04
 
#define XDP_EDID_DTD_VRES_LSB   0x05
 
#define XDP_EDID_DTD_VBLANK_LSB   0x06
 
#define XDP_EDID_DTD_VRES_VBLANK_U4   0x07
 
#define XDP_EDID_DTD_HFPORCH_LSB   0x08
 
#define XDP_EDID_DTD_HSPW_LSB   0x09
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4   0x0A
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2   0x0B
 
#define XDP_EDID_DTD_HIMGSIZE_MM_LSB   0x0C
 
#define XDP_EDID_DTD_VIMGSIZE_MM_LSB   0x0D
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4   0x0E
 
#define XDP_EDID_DTD_HBORDER   0x0F
 
#define XDP_EDID_DTD_VBORDER   0x10
 
#define XDP_EDID_DTD_SIGNAL   0x11
 
#define XDP_EDID_EXT_BLOCK_TAG   0x00
 
#define XDP_TX_DISPID_VER_REV   0x00
 
#define XDP_TX_DISPID_SIZE   0x01
 
#define XDP_TX_DISPID_TYPE   0x02
 
#define XDP_TX_DISPID_EXT_COUNT   0x03
 
#define XDP_TX_DISPID_PAYLOAD_START   0x04
 
#define XDP_TX_DISPID_DB_SEC_TAG   0x00
 
#define XDP_TX_DISPID_DB_SEC_REV   0x01
 
#define XDP_TX_DISPID_DB_SEC_SIZE   0x02
 
#define XDP_TX_DISPID_TDT_TOP0   0x04
 
#define XDP_TX_DISPID_TDT_TOP1   0x05
 
#define XDP_TX_DISPID_TDT_TOP2   0x06
 
#define XDP_TX_DISPID_TDT_HSIZE0   0x07
 
#define XDP_TX_DISPID_TDT_HSIZE1   0x08
 
#define XDP_TX_DISPID_TDT_VSIZE0   0x09
 
#define XDP_TX_DISPID_TDT_VSIZE1   0x0A
 
#define XDP_TX_DISPID_TDT_VENID0   0x10
 
#define XDP_TX_DISPID_TDT_VENID1   0x11
 
#define XDP_TX_DISPID_TDT_VENID2   0x12
 
#define XDP_TX_DISPID_TDT_PCODE0   0x13
 
#define XDP_TX_DISPID_TDT_PCODE1   0x14
 
#define XDP_TX_DISPID_TDT_SN0   0x15
 
#define XDP_TX_DISPID_TDT_SN1   0x16
 
#define XDP_TX_DISPID_TDT_SN2   0x17
 
#define XDP_TX_DISPID_TDT_SN3   0x18
 

Extended Display Identification Data: Masks, shifts, and register

values for the Tiled Display Topology (TDT) section data block.

#define XDP_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK   0x0F
 
#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_MASK   0xF0
 
#define XDP_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT   4
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK   0x0F
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK   0xF0
 
#define XDP_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT   4
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK   0xC0
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK   0x30
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK   0x0C
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK   0x03
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT   6
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT   4
 
#define XDP_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT   2
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK   0x0F
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK   0xF0
 
#define XDP_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT   4
 
#define XDP_EDID_DTD_SIGNAL_HPOLARITY_MASK   0x02
 
#define XDP_EDID_DTD_SIGNAL_VPOLARITY_MASK   0x04
 
#define XDP_EDID_DTD_SIGNAL_HPOLARITY_SHIFT   1
 
#define XDP_EDID_DTD_SIGNAL_VPOLARITY_SHIFT   2
 
#define XDP_EDID_EXT_BLOCK_TAG_DISPID   0x70
 
#define XDP_TX_DISPID_TDT_TAG   0x12
 
#define XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT   4
 
#define XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK   (0xF << 4)
 
#define XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK   0xF
 
#define XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT   4
 
#define XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK   (0xF << 4)
 
#define XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK   0xF
 
#define XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT   6
 
#define XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK   (0x3 << 6)
 
#define XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT   4
 
#define XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK   (0x3 << 4)
 
#define XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT   2
 
#define XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK   (0x3 << 2)
 
#define XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK   0x3
 

Stream identification.

Multi-stream transport (MST) definitions.

#define XDP_TX_STREAM_ID1   1
 
#define XDP_TX_STREAM_ID2   2
 
#define XDP_TX_STREAM_ID3   3
 
#define XDP_TX_STREAM_ID4   4
 

Sideband message codes when the driver is in MST mode.

#define XDP_SBMSG_LINK_ADDRESS   0x01
 
#define XDP_SBMSG_CONNECTION_STATUS_NOTIFY   0x02
 
#define XDP_SBMSG_ENUM_PATH_RESOURCES   0x10
 
#define XDP_SBMSG_ALLOCATE_PAYLOAD   0x11
 
#define XDP_SBMSG_QUERY_PAYLOAD   0x12
 
#define XDP_SBMSG_RESOURCE_STATUS_NOTIFY   0x13
 
#define XDP_SBMSG_CLEAR_PAYLOAD_ID_TABLE   0x14
 
#define XDP_SBMSG_REMOTE_DPCD_READ   0x20
 
#define XDP_SBMSG_REMOTE_DPCD_WRITE   0x21
 
#define XDP_SBMSG_REMOTE_I2C_READ   0x22
 
#define XDP_SBMSG_REMOTE_I2C_WRITE   0x23
 
#define XDP_SBMSG_POWER_UP_PHY   0x24
 
#define XDP_SBMSG_POWER_DOWN_PHY   0x25
 
#define XDP_SBMSG_SINK_EVENT_NOTIFY   0x30
 
#define XDP_SBMSG_QUERY_STREAM_ENCRYPT_STATUS   0x38
 
#define XDP_SBMSG_NAK_REASON_WRITE_FAILURE   0x01
 
#define XDP_SBMSG_NAK_REASON_INVALID_RAD   0x02
 
#define XDP_SBMSG_NAK_REASON_CRC_FAILURE   0x03
 
#define XDP_SBMSG_NAK_REASON_BAD_PARAM   0x04
 
#define XDP_SBMSG_NAK_REASON_DEFER   0x05
 
#define XDP_SBMSG_NAK_REASON_LINK_FAILURE   0x06
 
#define XDP_SBMSG_NAK_REASON_NO_RESOURCES   0x07
 
#define XDP_SBMSG_NAK_REASON_DPCD_FAIL   0x08
 
#define XDP_SBMSG_NAK_REASON_I2C_NAK   0x09
 
#define XDP_SBMSG_NAK_REASON_ALLOCATE_FAIL   0x0A
 

Register access macro definitions.

#define XDp_In32   Xil_In32
 
#define XDp_Out32   Xil_Out32
 

Macro Definition Documentation

◆ XDp_GetCoreType

#define XDp_GetCoreType (   InstancePtr)

#include <xdp.h>

Value:
((InstancePtr)->Config.IsRx \
? XDP_RX : XDP_TX)

This is function determines whether the DisplayPort core, represented by the XDp structure pointed to, is a transmitter (TX) or a receiver (RX).

Parameters
InstancePtris a pointer to the XDp instance.
Returns
XDP_RX if the core is of type RX. XDP_TX if the core is of type TX.
Note
C-style signature: XDp_CoreType XDp_GetCoreType(XDp *InstancePtr)

Referenced by XDp_CfgInitialize(), XDp_Initialize(), XDp_InterruptHandler(), XDp_RxAudioDis(), XDp_RxAudioEn(), XDp_RxAudioReset(), XDp_RxCheckLinkStatus(), XDp_RxDtgDis(), XDp_RxDtgEn(), XDp_RxGenerateHpdInterrupt(), XDp_RxGetBpc(), XDp_RxGetColorComponent(), XDp_RxGetIicMapEntry(), XDp_RxHandleDownReq(), XDp_RxInterruptDisable(), XDp_RxInterruptEnable(), XDp_RxMstExposePort(), XDp_RxMstSetInputPort(), XDp_RxMstSetPbn(), XDp_RxMstSetPort(), XDp_RxSetDpcdMap(), XDp_RxSetDrvIntrNoVideoHandler(), XDp_RxSetDrvIntrPowerStateHandler(), XDp_RxSetDrvIntrVideoHandler(), XDp_RxSetIicMapEntry(), XDp_RxSetIntrActRxHandler(), XDp_RxSetIntrAudioOverHandler(), XDp_RxSetIntrBwChangeHandler(), XDp_RxSetIntrCrcTestHandler(), XDp_RxSetIntrDownReplyHandler(), XDp_RxSetIntrDownReqHandler(), XDp_RxSetIntrExtPktHandler(), XDp_RxSetIntrHdcpAinfoWriteHandler(), XDp_RxSetIntrHdcpAksvWriteHandler(), XDp_RxSetIntrHdcpAnWriteHandler(), XDp_RxSetIntrHdcpBinfoReadHandler(), XDp_RxSetIntrHdcpDebugWriteHandler(), XDp_RxSetIntrHdcpRoReadHandler(), XDp_RxSetIntrInfoPktHandler(), XDp_RxSetIntrNoVideoHandler(), XDp_RxSetIntrPayloadAllocHandler(), XDp_RxSetIntrPowerStateHandler(), XDp_RxSetIntrTp1Handler(), XDp_RxSetIntrTp2Handler(), XDp_RxSetIntrTp3Handler(), XDp_RxSetIntrTrainingDoneHandler(), XDp_RxSetIntrTrainingLostHandler(), XDp_RxSetIntrUnplugHandler(), XDp_RxSetIntrVBlankHandler(), XDp_RxSetIntrVideoHandler(), XDp_RxSetIntrVmChangeHandler(), XDp_RxSetLaneCount(), XDp_RxSetLineReset(), XDp_RxSetLinkRate(), XDp_RxSetUserPixelWidth(), XDp_SelfTest(), XDp_TxAllocatePayloadStreams(), XDp_TxAllocatePayloadVcIdTable(), XDp_TxAuxRead(), XDp_TxAuxWrite(), XDp_TxCfgMainLinkMax(), XDp_TxCfgMsaEnSynchClkMode(), XDp_TxCfgMsaRecalculate(), XDp_TxCfgMsaSetBpc(), XDp_TxCfgMsaUseCustom(), XDp_TxCfgMsaUseEdidPreferredTiming(), XDp_TxCfgMsaUseStandardVideoMode(), XDp_TxCfgSetColorEncode(), XDp_TxCfgTxPeLevel(), XDp_TxCfgTxVsLevel(), XDp_TxCfgTxVsOffset(), XDp_TxCheckLinkStatus(), XDp_TxClearMsaValues(), XDp_TxClearPayloadVcIdTable(), XDp_TxDisableMainLink(), XDp_TxEnableMainLink(), XDp_TxEnableTrainAdaptive(), XDp_TxEstablishLink(), XDp_TxFindAccessibleDpDevices(), XDp_TxGetEdid(), XDp_TxGetEdidBlock(), XDp_TxGetGuid(), XDp_TxGetRemoteEdid(), XDp_TxGetRemoteEdidBlock(), XDp_TxGetRemoteEdidDispIdExt(), XDp_TxGetRemoteTiledDisplayDb(), XDp_TxGetRxCapabilities(), XDp_TxIicRead(), XDp_TxIicWrite(), XDp_TxIsConnected(), XDp_TxMstCapable(), XDp_TxMstCfgModeDisable(), XDp_TxMstCfgModeEnable(), XDp_TxMstCfgStreamDisable(), XDp_TxMstCfgStreamEnable(), XDp_TxMstDisable(), XDp_TxMstEnable(), XDp_TxMstStreamIsEnabled(), XDp_TxRemoteDpcdRead(), XDp_TxRemoteDpcdWrite(), XDp_TxRemoteIicRead(), XDp_TxRemoteIicWrite(), XDp_TxResetPhy(), XDp_TxSendSbMsgAllocatePayload(), XDp_TxSendSbMsgClearPayloadIdTable(), XDp_TxSendSbMsgEnumPathResources(), XDp_TxSendSbMsgLinkAddress(), XDp_TxSendSbMsgRemoteDpcdRead(), XDp_TxSendSbMsgRemoteDpcdWrite(), XDp_TxSendSbMsgRemoteIicRead(), XDp_TxSendSbMsgRemoteIicWrite(), XDp_TxSetDownspread(), XDp_TxSetDrvHpdEventHandler(), XDp_TxSetDrvHpdPulseHandler(), XDp_TxSetEnhancedFrameMode(), XDp_TxSetHasRedriverInPath(), XDp_TxSetHpdEventHandler(), XDp_TxSetHpdPulseHandler(), XDp_TxSetLaneCount(), XDp_TxSetLaneCountChangeCallback(), XDp_TxSetLinkRate(), XDp_TxSetLinkRateChangeCallback(), XDp_TxSetMsaHandler(), XDp_TxSetMsaValues(), XDp_TxSetPeVsAdjustCallback(), XDp_TxSetPhyPolarityAll(), XDp_TxSetPhyPolarityLane(), XDp_TxSetScrambler(), XDp_TxSetStreamSelectFromSinkList(), XDp_TxSetStreamSinkRad(), XDp_TxSetUserPixelWidth(), XDp_TxTopologySortSinksByTiling(), XDp_TxTopologySwapSinks(), and XDp_TxWriteGuid().

◆ XDP_GUID_NBYTES

#define XDP_GUID_NBYTES   16

#include <xdp_hw.h>

The number of bytes for the global unique ID.

Referenced by XDp_TxGetGuid(), and XDp_TxWriteGuid().

◆ XDP_MAX_NPORTS

#define XDP_MAX_NPORTS   16

#include <xdp_hw.h>

The maximum number of ports connected to a DisplayPort device.

◆ XDp_ReadReg

#define XDp_ReadReg (   BaseAddress,
  RegOffset 
)    XDp_In32((BaseAddress) + (RegOffset))

#include <xdp_hw.h>

This is a low-level function that reads from the specified register.

Parameters
BaseAddressis the base address of the device.
RegOffsetis the register offset to be read from.
Returns
The 32-bit value of the specified register.
Note
C-style signature: u32 XDp_ReadReg(UINTPTR BaseAddress, u32 RegOffset)

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_AUDIO_CONTROL

#define XDP_RX_AUDIO_CONTROL   0x300

#include <xdp_hw.h>

Enables audio stream packets in main link.

◆ XDP_RX_AUDIO_EXT_DATA

#define XDP_RX_AUDIO_EXT_DATA (   NUM)    (0x330 + 4 * (NUM - 1))

#include <xdp_hw.h>

Word formatted as per extension packet.

◆ XDP_RX_AUDIO_INFO_DATA

#define XDP_RX_AUDIO_INFO_DATA (   NUM)    (0x304 + 4 * (NUM - 1))

#include <xdp_hw.h>

Word formatted as per CEA 861-C info frame.

◆ XDP_RX_AUDIO_MAUD

#define XDP_RX_AUDIO_MAUD   0x324

#include <xdp_hw.h>

M value of audio stream as decoded from audio time stamp packet.

◆ XDP_RX_AUDIO_NAUD

#define XDP_RX_AUDIO_NAUD   0x328

#include <xdp_hw.h>

N value of audio stream as decoded from audio time stamp packet.

◆ XDP_RX_AUDIO_STATUS

#define XDP_RX_AUDIO_STATUS   0x32C

#include <xdp_hw.h>

Status of audio stream.

◆ XDP_RX_AUDIO_UNSUPPORTED

#define XDP_RX_AUDIO_UNSUPPORTED   0x098

#include <xdp_hw.h>

DPCD register bit to inform the DisplayPort TX that audio data is not supported.

◆ XDP_RX_AUX_CLK_DIVIDER

#define XDP_RX_AUX_CLK_DIVIDER   0x004

#include <xdp_hw.h>

Clock divider value for generating the internal 1MHz clock.

◆ XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK

#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0xFF00

#include <xdp_hw.h>

AUX (noise) signal width filter.

◆ XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT

#define XDP_RX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8

#include <xdp_hw.h>

Shift bits for AUX signal width filter.

◆ XDP_RX_AUX_CLK_DIVIDER_VAL_MASK

#define XDP_RX_AUX_CLK_DIVIDER_VAL_MASK   0x00FF

#include <xdp_hw.h>

Clock divider value.

◆ XDP_RX_AUX_DEFER_SHIFT

#define XDP_RX_AUX_DEFER_SHIFT   24

#include <xdp_hw.h>

Aux defer.

◆ XDP_RX_AUX_REQ_IN_PROGRESS

#define XDP_RX_AUX_REQ_IN_PROGRESS   0x020

#include <xdp_hw.h>

Indicates the receipt of an AUX channel request.

◆ XDP_RX_BS_IDLE_TIME

#define XDP_RX_BS_IDLE_TIME   0x220

#include <xdp_hw.h>

Blanking start symbol idle time - this value is loaded as a timeout counter for detecting cable disconnect or unplug events.

◆ XDP_RX_CDR_CONTROL_CONFIG

#define XDP_RX_CDR_CONTROL_CONFIG   0x21C

#include <xdp_hw.h>

Control the configuration for clock and data recovery.

◆ XDP_RX_CDR_CONTROL_CONFIG_DFE_CTRL_MASK

#define XDP_RX_CDR_CONTROL_CONFIG_DFE_CTRL_MASK   0x80000000

#include <xdp_hw.h>

Use DFE control.

◆ XDP_RX_CDR_CONTROL_CONFIG_DISABLE_TIMEOUT

#define XDP_RX_CDR_CONTROL_CONFIG_DISABLE_TIMEOUT   0X40000000

#include <xdp_hw.h>

Timeout for MST mode.

◆ XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_DP159

#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_DP159   0x1388

#include <xdp_hw.h>

CDR tDLOCK calibration value using DP159.

◆ XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_TO_MASK

#define XDP_RX_CDR_CONTROL_CONFIG_TDLOCK_TO_MASK   0x000FFFFF

#include <xdp_hw.h>

Controls the CDR tDLOCK timeout value.

◆ XDP_RX_CORE_ID

#define XDP_RX_CORE_ID   0x0FC

#include <xdp_hw.h>

DisplayPort protocol version and revision.

◆ XDP_RX_CORE_ID_DP_MJR_VER_MASK

#define XDP_RX_CORE_ID_DP_MJR_VER_MASK   0x0000F000

#include <xdp_hw.h>

DisplayPort protocol major version.

◆ XDP_RX_CORE_ID_DP_MJR_VER_SHIFT

#define XDP_RX_CORE_ID_DP_MJR_VER_SHIFT   24

#include <xdp_hw.h>

Shift bits for DisplayPort protocol major version.

◆ XDP_RX_CORE_ID_DP_MNR_VER_MASK

#define XDP_RX_CORE_ID_DP_MNR_VER_MASK   0x00000F00

#include <xdp_hw.h>

DisplayPort protocol minor version.

◆ XDP_RX_CORE_ID_DP_MNR_VER_SHIFT

#define XDP_RX_CORE_ID_DP_MNR_VER_SHIFT   16

#include <xdp_hw.h>

Shift bits for DisplayPort protocol major version.

◆ XDP_RX_CORE_ID_DP_REV_MASK

#define XDP_RX_CORE_ID_DP_REV_MASK   0x000000F0

#include <xdp_hw.h>

DisplayPort protocol revision.

◆ XDP_RX_CORE_ID_DP_REV_SHIFT

#define XDP_RX_CORE_ID_DP_REV_SHIFT   8

#include <xdp_hw.h>

Shift bits for DisplayPort protocol revision.

◆ XDP_RX_CORE_ID_TYPE_MASK

#define XDP_RX_CORE_ID_TYPE_MASK   0x0000000F

#include <xdp_hw.h>

Core type.

◆ XDP_RX_CORE_ID_TYPE_RX

#define XDP_RX_CORE_ID_TYPE_RX   0x1

#include <xdp_hw.h>

Core is a receiver.

◆ XDP_RX_CORE_ID_TYPE_TX

#define XDP_RX_CORE_ID_TYPE_TX   0x0

#include <xdp_hw.h>

Core is a transmitter.

◆ XDP_RX_DEVICE_SERVICE_IRQ

#define XDP_RX_DEVICE_SERVICE_IRQ   0x090

#include <xdp_hw.h>

Indicates the DPCD DEVICE_SERVICE_IRQ_ VECTOR state.

◆ XDP_RX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK

#define XDP_RX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK   0x04

#include <xdp_hw.h>

Generates a CP IRQ event.

◆ XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK

#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK   0x10

#include <xdp_hw.h>

Indicates a new DOWN_REPLY buffer message is ready.

◆ XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK

#define XDP_RX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK   0x01

#include <xdp_hw.h>

Indicates that a new command is present in the REMOTE_CMD register.

◆ XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK

#define XDP_RX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK   0x02

#include <xdp_hw.h>

Reflects the SINK_SPECIFIC_IRQ state.

◆ XDP_RX_DOWN_REP

#define XDP_RX_DOWN_REP   0xB00

#include <xdp_hw.h>

Down reply buffer address space.

◆ XDP_RX_DOWN_REQ

#define XDP_RX_DOWN_REQ   0xA00

#include <xdp_hw.h>

Down request buffer address space.

◆ XDP_RX_DPCD_DOWNSPREAD_CONTROL

#define XDP_RX_DPCD_DOWNSPREAD_CONTROL   0x430

#include <xdp_hw.h>

The RX DPCD value that is used by the TX to inform the RX that downspreading has been enabled.

◆ XDP_RX_DPCD_ENHANCED_FRAME_EN

#define XDP_RX_DPCD_ENHANCED_FRAME_EN   0x408

#include <xdp_hw.h>

Current setting for enhanced framing symbol mode as exposed in the RX DPCD.

◆ XDP_RX_DPCD_HDCP_TABLE

#define XDP_RX_DPCD_HDCP_TABLE   0x900

#include <xdp_hw.h>

HDCP register table (0x100 bytes).

◆ XDP_RX_DPCD_LANE01_STATUS

#define XDP_RX_DPCD_LANE01_STATUS   0x43C

#include <xdp_hw.h>

Link training status for lanes 0 and 1 as exposed in the RX DPCD.

◆ XDP_RX_DPCD_LANE23_STATUS

#define XDP_RX_DPCD_LANE23_STATUS   0x440

#include <xdp_hw.h>

Link training status for lanes 2 and 3 as exposed in the RX DPCD.

◆ XDP_RX_DPCD_LANE_COUNT_SET

#define XDP_RX_DPCD_LANE_COUNT_SET   0x404

#include <xdp_hw.h>

Current lane count setting as exposed in the RX DPCD.

◆ XDP_RX_DPCD_LINK_BW_SET

#define XDP_RX_DPCD_LINK_BW_SET   0x400

#include <xdp_hw.h>

Current link bandwidth setting as exposed in the RX DPCD.

◆ XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET

#define XDP_RX_DPCD_LINK_QUALITY_PATTERN_SET   0x410

#include <xdp_hw.h>

Current value of the link quality pattern field as exposed in the RX DPCD.

◆ XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET

#define XDP_RX_DPCD_MAIN_LINK_CHANNEL_CODING_SET   0x434

#include <xdp_hw.h>

8B/10B encoding setting as exposed in the RX DPCD.

◆ XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN

#define XDP_RX_DPCD_RECOVERED_CLOCK_OUT_EN   0x414

#include <xdp_hw.h>

Value of the output clock enable field as exposed in the RX DPCD.

◆ XDP_RX_DPCD_SCRAMBLING_DISABLE

#define XDP_RX_DPCD_SCRAMBLING_DISABLE   0x418

#include <xdp_hw.h>

Value of the scrambling disable field as exposed in the RX DPCD.

◆ XDP_RX_DPCD_SET_POWER_STATE

#define XDP_RX_DPCD_SET_POWER_STATE   0x438

#include <xdp_hw.h>

Power state requested by the TX as exposed in the RX DPCD.

◆ XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT

#define XDP_RX_DPCD_SYMBOL_ERROR_COUNT_SELECT   0x41C

#include <xdp_hw.h>

Current value of the symbol error count select field as exposed in the RX DPCD.

◆ XDP_RX_DPCD_TRAINING_LANE_0_SET

#define XDP_RX_DPCD_TRAINING_LANE_0_SET   0x420

#include <xdp_hw.h>

The RX DPCD value used by the TX during link training to configure the RX PHY lane 0.

◆ XDP_RX_DPCD_TRAINING_LANE_1_SET

#define XDP_RX_DPCD_TRAINING_LANE_1_SET   0x424

#include <xdp_hw.h>

The RX DPCD value used by the TX during link training to configure the RX PHY lane 1.

◆ XDP_RX_DPCD_TRAINING_LANE_2_SET

#define XDP_RX_DPCD_TRAINING_LANE_2_SET   0x428

#include <xdp_hw.h>

The RX DPCD value used by the TX during link training to configure the RX PHY lane 2.

◆ XDP_RX_DPCD_TRAINING_LANE_3_SET

#define XDP_RX_DPCD_TRAINING_LANE_3_SET   0x42C

#include <xdp_hw.h>

The RX DPCD value Used by the TX during link training to configure the RX PHY lane 3.

◆ XDP_RX_DPCD_TRAINING_PATTERN_SET

#define XDP_RX_DPCD_TRAINING_PATTERN_SET   0x40C

#include <xdp_hw.h>

Current training pattern setting as exposed in the RX DPCD.

◆ XDP_RX_DTG_ENABLE

#define XDP_RX_DTG_ENABLE   0x00C

#include <xdp_hw.h>

Enables the display timing generator (DTG).

◆ XDP_RX_FAST_I2C_DIVIDER

#define XDP_RX_FAST_I2C_DIVIDER   0x060

#include <xdp_hw.h>

Fast I2C mode clock divider value.

◆ XDP_RX_GT_DRP_CH_STATUS

#define XDP_RX_GT_DRP_CH_STATUS   0x2A8

#include <xdp_hw.h>

Provides access to GT DRP channel status.

◆ XDP_RX_GT_DRP_COMMAND

#define XDP_RX_GT_DRP_COMMAND   0x2A0

#include <xdp_hw.h>

Provides access to the GT DRP ports.

◆ XDP_RX_GT_DRP_READ_DATA

#define XDP_RX_GT_DRP_READ_DATA   0x2A4

#include <xdp_hw.h>

Provides access to GT DRP read data.

◆ XDP_RX_GUID0

#define XDP_RX_GUID0   0x0E0

#include <xdp_hw.h>

Lower 4 bytes of the DPCD's GUID field.

◆ XDP_RX_GUID1

#define XDP_RX_GUID1   0x0E4

#include <xdp_hw.h>

Bytes 4 to 7 of the DPCD's GUID field.

◆ XDP_RX_GUID2

#define XDP_RX_GUID2   0x0E8

#include <xdp_hw.h>

Bytes 8 to 11 of the DPCD's GUID field.

◆ XDP_RX_GUID3

#define XDP_RX_GUID3   0x0EC

#include <xdp_hw.h>

Upper 4 bytes of the DPCD's GUID field.

◆ XDP_RX_HPD_INTERRUPT

#define XDP_RX_HPD_INTERRUPT   0x02C

#include <xdp_hw.h>

Instructs the DisplayPort RX core to assert an interrupt to the TX using the HPD signal.

◆ XDP_RX_HPD_INTERRUPT_ASSERT_MASK

#define XDP_RX_HPD_INTERRUPT_ASSERT_MASK   0x00000001

#include <xdp_hw.h>

Instructs the RX core to assert an interrupt to the TX using the HPD signal.

◆ XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK

#define XDP_RX_HPD_INTERRUPT_LENGTH_US_MASK   0xFFFF0000

#include <xdp_hw.h>

The length of the HPD pulse to generate (in microseconds).

◆ XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT

#define XDP_RX_HPD_INTERRUPT_LENGTH_US_SHIFT   16

#include <xdp_hw.h>

Shift bits for the HPD pulse length.

◆ XDP_RX_HSYNC_WIDTH

#define XDP_RX_HSYNC_WIDTH   0x050

#include <xdp_hw.h>

Controls the timing of the active-high horizontal sync pulse generated by the display timing generator (DTG).

◆ XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK

#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_MASK   0xFF00

#include <xdp_hw.h>

Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse (the front porch).

◆ XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT

#define XDP_RX_HSYNC_WIDTH_FRONT_PORCH_SHIFT   8

#include <xdp_hw.h>

Shift bits for the front porch.

◆ XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK

#define XDP_RX_HSYNC_WIDTH_PULSE_WIDTH_MASK   0x00FF

#include <xdp_hw.h>

Specifies the number of clock cycles the horizontal sync pulse is asserted.

◆ XDP_RX_INTERRUPT_CAUSE

#define XDP_RX_INTERRUPT_CAUSE   0x040

#include <xdp_hw.h>

Indicates the cause of pending host interrupts for stream 1, training, payload allocation, and for the AUX channel.

◆ XDP_RX_INTERRUPT_CAUSE_1

#define XDP_RX_INTERRUPT_CAUSE_1   0x048

#include <xdp_hw.h>

Indicates the cause of a pending host interrupts for streams 2, 3, 4.

◆ XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by an audio extension packet being received for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by an audio info packet being received for stream 2, 3, or.

◆ XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by the no-video condition being detected after active video received for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by the start of the blanking interval for stream 2, 3, or.

◆ XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by a valid video frame being detected on the main link for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK

#define XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK (   Stream)    XDP_RX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream)

#include <xdp_hw.h>

Interrupt caused by a resolution change, as detected from the MSA fields for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_CAUSE_ACT_RX_MASK

#define XDP_RX_INTERRUPT_CAUSE_ACT_RX_MASK   XDP_RX_INTERRUPT_MASK_ACT_RX_MASK

#include <xdp_hw.h>

Interrupt caused by the ACT sequence being received.

◆ XDP_RX_INTERRUPT_CAUSE_AUDIO_OVER_MASK

#define XDP_RX_INTERRUPT_CAUSE_AUDIO_OVER_MASK   XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK

#include <xdp_hw.h>

Interrupt caused by an audio packet overflow.

◆ XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK

#define XDP_RX_INTERRUPT_CAUSE_BW_CHANGE_MASK   XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK

#include <xdp_hw.h>

Interrupt caused by a change in bandwidth.

◆ XDP_RX_INTERRUPT_CAUSE_CRC_TEST_MASK

#define XDP_RX_INTERRUPT_CAUSE_CRC_TEST_MASK   XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK

#include <xdp_hw.h>

Interrupt caused by the start of a CRC test.

◆ XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK

#define XDP_RX_INTERRUPT_CAUSE_DOWN_REPLY_MASK   XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK

#include <xdp_hw.h>

Interrupt caused by a downstream reply being ready.

◆ XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK

#define XDP_RX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK   XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK

#include <xdp_hw.h>

Interrupt caused by a downstream request being ready.

◆ XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK

#define XDP_RX_INTERRUPT_CAUSE_EXT_PKT_MASK   XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK

#include <xdp_hw.h>

Interrupt caused by an audio extension packet being received.

◆ XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK

#define XDP_RX_INTERRUPT_CAUSE_INFO_PKT_MASK   XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK

#include <xdp_hw.h>

Interrupt caused by an audio info packet being received.

◆ XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK

#define XDP_RX_INTERRUPT_CAUSE_NO_VIDEO_MASK   XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK

#include <xdp_hw.h>

Interrupt caused by the no-video condition being detected after active video received.

◆ XDP_RX_INTERRUPT_CAUSE_PAYLOAD_ALLOC_MASK

#define XDP_RX_INTERRUPT_CAUSE_PAYLOAD_ALLOC_MASK   XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK

#include <xdp_hw.h>

Interrupt caused by the RX's DPCD payload allocation registers has been updated as part of (de-)allocation or partial deletion.

◆ XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK

#define XDP_RX_INTERRUPT_CAUSE_POWER_STATE_MASK   XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK

#include <xdp_hw.h>

Interrupt caused by a power state change.

◆ XDP_RX_INTERRUPT_CAUSE_TP1_MASK

#define XDP_RX_INTERRUPT_CAUSE_TP1_MASK   XDP_RX_INTERRUPT_MASK_TP1_MASK

#include <xdp_hw.h>

Interrupt caused by the start of training pattern 1.

◆ XDP_RX_INTERRUPT_CAUSE_TP2_MASK

#define XDP_RX_INTERRUPT_CAUSE_TP2_MASK   XDP_RX_INTERRUPT_MASK_TP2_MASK

#include <xdp_hw.h>

Interrupt caused by the start of training pattern 2.

◆ XDP_RX_INTERRUPT_CAUSE_TP3_MASK

#define XDP_RX_INTERRUPT_CAUSE_TP3_MASK   XDP_RX_INTERRUPT_MASK_TP3_MASK

#include <xdp_hw.h>

Interrupt caused by the start of training pattern 3.

◆ XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK

#define XDP_RX_INTERRUPT_CAUSE_TRAINING_DONE_MASK   XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK

#include <xdp_hw.h>

Interrupt caused by link training completion.

◆ XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK

#define XDP_RX_INTERRUPT_CAUSE_TRAINING_LOST_MASK   XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK

#include <xdp_hw.h>

Interrupt caused by training loss on active lanes.

◆ XDP_RX_INTERRUPT_CAUSE_UNPLUG_MASK

#define XDP_RX_INTERRUPT_CAUSE_UNPLUG_MASK   XDP_RX_INTERRUPT_MASK_UNPLUG_MASK

#include <xdp_hw.h>

Interrupt caused by the an unplug event.

◆ XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK

#define XDP_RX_INTERRUPT_CAUSE_VBLANK_MASK   XDP_RX_INTERRUPT_MASK_VBLANK_MASK

#include <xdp_hw.h>

Interrupt caused by the start of the blanking interval.

◆ XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK

#define XDP_RX_INTERRUPT_CAUSE_VCP_ALLOC_MASK   XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK

#include <xdp_hw.h>

Interrupt caused by a virtual channel payload being allocated.

◆ XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK

#define XDP_RX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK   XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK

#include <xdp_hw.h>

Interrupt caused by a virtual channel payload being allocated.

◆ XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK

#define XDP_RX_INTERRUPT_CAUSE_VIDEO_MASK   XDP_RX_INTERRUPT_MASK_VIDEO_MASK

#include <xdp_hw.h>

Interrupt caused by a valid video frame being detected on the main link.

Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character.

◆ XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK

#define XDP_RX_INTERRUPT_CAUSE_VM_CHANGE_MASK   XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK

#include <xdp_hw.h>

Interrupt caused by a resolution change, as detected from the MSA fields.

◆ XDP_RX_INTERRUPT_MASK

#define XDP_RX_INTERRUPT_MASK   0x014

#include <xdp_hw.h>

Masks the specified interrupt sources for stream 1.

◆ XDP_RX_INTERRUPT_MASK_1

#define XDP_RX_INTERRUPT_MASK_1   0x044

#include <xdp_hw.h>

Masks the specified interrupt sources for streams 2, 3, 4.

◆ XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK (   Stream)    (0x00001 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for an audio extension packet being received for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK (   Stream)    (0x00002 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for an audio info packet being received for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK (   Stream)    (0x00008 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for the no-video condition being detected after active video received for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK (   Stream)    (0x00010 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for the start of the blanking interval for stream 2, 3, or.

◆ XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK (   Stream)    (0x00020 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for a valid video frame being detected on the main link for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK

#define XDP_RX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK (   Stream)    (0x00004 << ((Stream - 2) * 6))

#include <xdp_hw.h>

Mask the interrupt assertion for a resolution change, as detected from the MSA fields for stream 2, 3, or 4.

◆ XDP_RX_INTERRUPT_MASK_ACT_RX_MASK

#define XDP_RX_INTERRUPT_MASK_ACT_RX_MASK   0x20000000

#include <xdp_hw.h>

Mask the interrupt assertion for the ACT sequence being received.

◆ XDP_RX_INTERRUPT_MASK_ALL_MASK

#define XDP_RX_INTERRUPT_MASK_ALL_MASK   0xF9FFFFFF

#include <xdp_hw.h>

Mask all interrupts.

◆ XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK

#define XDP_RX_INTERRUPT_MASK_AUDIO_OVER_MASK   0x08000000

#include <xdp_hw.h>

Mask the interrupt assertion caused for an audio packet overflow.

◆ XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK

#define XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK   0x00008000

#include <xdp_hw.h>

Mask the interrupt assertion for a change in bandwidth.

◆ XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK

#define XDP_RX_INTERRUPT_MASK_CRC_TEST_MASK   0x40000000

#include <xdp_hw.h>

Mask the interrupt assertion for the start of a CRC test.

◆ XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK

#define XDP_RX_INTERRUPT_MASK_DOWN_REPLY_MASK   0x00001000

#include <xdp_hw.h>

Mask the interrupt assertion for a downstream reply being ready.

◆ XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK

#define XDP_RX_INTERRUPT_MASK_DOWN_REQUEST_MASK   0x00002000

#include <xdp_hw.h>

Mask the interrupt assertion for a downstream request being ready.

◆ XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK

#define XDP_RX_INTERRUPT_MASK_EXT_PKT_MASK   0x00000200

#include <xdp_hw.h>

Mask the interrupt assertion for an audio extension packet being received.

◆ XDP_RX_INTERRUPT_MASK_HDCP_AINFO_WRITE_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_AINFO_WRITE_MASK   0x00400000

#include <xdp_hw.h>

Mask the interrupt for a write to the HDCP AInfo register.

◆ XDP_RX_INTERRUPT_MASK_HDCP_AKSV_WRITE_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_AKSV_WRITE_MASK   0x00100000

#include <xdp_hw.h>

Mask the interrupt for a write to the HDCP AKSV MSB register.

◆ XDP_RX_INTERRUPT_MASK_HDCP_AN_WRITE_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_AN_WRITE_MASK   0x00200000

#include <xdp_hw.h>

Mask the interrupt for a write to the HDCP An MSB register.

◆ XDP_RX_INTERRUPT_MASK_HDCP_BINFO_READ_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_BINFO_READ_MASK   0x01000000

#include <xdp_hw.h>

Mask the interrupt for a read of the HDCP BInfo register.

◆ XDP_RX_INTERRUPT_MASK_HDCP_DEBUG_WRITE_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_DEBUG_WRITE_MASK   0x00080000

#include <xdp_hw.h>

Mask the interrupt for a write to any HDCP debug register.

◆ XDP_RX_INTERRUPT_MASK_HDCP_RO_READ_MASK

#define XDP_RX_INTERRUPT_MASK_HDCP_RO_READ_MASK   0x00800000

#include <xdp_hw.h>

Mask the interrupt for a read of the HDCP Ro register.

◆ XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK

#define XDP_RX_INTERRUPT_MASK_INFO_PKT_MASK   0x00000100

#include <xdp_hw.h>

Mask the interrupt assertion for an audio info packet being received.

◆ XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK

#define XDP_RX_INTERRUPT_MASK_NO_VIDEO_MASK   0x00000004

#include <xdp_hw.h>

Mask the interrupt assertion for the no-video condition being detected after active video received.

◆ XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK

#define XDP_RX_INTERRUPT_MASK_PAYLOAD_ALLOC_MASK   0x10000000

#include <xdp_hw.h>

Mask the interrupt assertion for the RX's DPCD payload allocation registers that have been updated as part of (de-)allocation or partial deletion.

◆ XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK

#define XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK   0x00000002

#include <xdp_hw.h>

Mask the interrupt assertion for a power state change.

◆ XDP_RX_INTERRUPT_MASK_TP1_MASK

#define XDP_RX_INTERRUPT_MASK_TP1_MASK   0x00010000

#include <xdp_hw.h>

Mask the interrupt assertion for start of training pattern 1.

◆ XDP_RX_INTERRUPT_MASK_TP2_MASK

#define XDP_RX_INTERRUPT_MASK_TP2_MASK   0x00020000

#include <xdp_hw.h>

Mask the interrupt assertion for start of training pattern 2.

◆ XDP_RX_INTERRUPT_MASK_TP3_MASK

#define XDP_RX_INTERRUPT_MASK_TP3_MASK   0x00040000

#include <xdp_hw.h>

Mask the interrupt assertion for start of training pattern 3.

◆ XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK

#define XDP_RX_INTERRUPT_MASK_TRAINING_DONE_MASK   0x00004000

#include <xdp_hw.h>

Mask the interrupt assertion for link training completion.

◆ XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK

#define XDP_RX_INTERRUPT_MASK_TRAINING_LOST_MASK   0x00000010

#include <xdp_hw.h>

Mask the interrupt assertion for training loss on active lanes.

◆ XDP_RX_INTERRUPT_MASK_UNPLUG_MASK

#define XDP_RX_INTERRUPT_MASK_UNPLUG_MASK   0x80000000

#include <xdp_hw.h>

Mask the unplug event interrupt.

◆ XDP_RX_INTERRUPT_MASK_VBLANK_MASK

#define XDP_RX_INTERRUPT_MASK_VBLANK_MASK   0x00000008

#include <xdp_hw.h>

Mask the interrupt assertion for the start of the blanking interval.

◆ XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK

#define XDP_RX_INTERRUPT_MASK_VCP_ALLOC_MASK   0x00000400

#include <xdp_hw.h>

Mask the interrupt assertion for a virtual channel payload being allocated.

◆ XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK

#define XDP_RX_INTERRUPT_MASK_VCP_DEALLOC_MASK   0x00000800

#include <xdp_hw.h>

Mask the interrupt assertion for a virtual channel payload being allocated.

◆ XDP_RX_INTERRUPT_MASK_VIDEO_MASK

#define XDP_RX_INTERRUPT_MASK_VIDEO_MASK   0x00000040

#include <xdp_hw.h>

Mask the interrupt assertion for a valid video frame being detected on the main link.

Video interrupt is set after a delay of 8 video frames following a valid scrambler reset character.

◆ XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK

#define XDP_RX_INTERRUPT_MASK_VM_CHANGE_MASK   0x00000001

#include <xdp_hw.h>

Mask the interrupt assertion for a resolution change, as detected from the MSA fields.

◆ XDP_RX_LINE_RESET_DISABLE

#define XDP_RX_LINE_RESET_DISABLE   0x008

#include <xdp_hw.h>

RX line reset disable.

◆ XDP_RX_LINE_RESET_DISABLE_MASK

#define XDP_RX_LINE_RESET_DISABLE_MASK (   Stream)    (1 << ((Stream) - XDP_TX_STREAM_ID1))

#include <xdp_hw.h>

Used to disable the end of the line reset to the internal video pipe.

◆ XDP_RX_LINK_ENABLE

#define XDP_RX_LINK_ENABLE   0x000

#include <xdp_hw.h>

Enable the receiver core.

◆ XDP_RX_LOCAL_EDID_AUDIO

#define XDP_RX_LOCAL_EDID_AUDIO   0x088

#include <xdp_hw.h>

Indicates the presence of EDID information for the audio stream.

◆ XDP_RX_LOCAL_EDID_VIDEO

#define XDP_RX_LOCAL_EDID_VIDEO   0x084

#include <xdp_hw.h>

Indicates the presence of EDID information for the video stream.

◆ XDP_RX_MIN_VOLTAGE_SWING

#define XDP_RX_MIN_VOLTAGE_SWING   0x214

#include <xdp_hw.h>

Specifies the minimum voltage swing required during training before a link can be reliably established and advanced configuration for link training.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_MASK   0x000C00

#include <xdp_hw.h>

Channel equalization options.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_HOLD

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_HOLD   0x1

#include <xdp_hw.h>

Hold adjust request to SET_PE.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_INC

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_INC   0x0

#include <xdp_hw.h>

Increment pre-emphasis adjust request every training iteration until maximum level, SET_PE, is reached.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_TABLE

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_PE_TABLE   0x2

#include <xdp_hw.h>

Pick pre-emphasis values from PE_TABLE.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_SHIFT   10

#include <xdp_hw.h>

Shift bits for channel equalization options.

◆ XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_VS_NA

#define XDP_RX_MIN_VOLTAGE_SWING_CE_OPT_VS_NA   0x3

#include <xdp_hw.h>

Not applicable.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_MASK   0x00000C

#include <xdp_hw.h>

Clock recovery options.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_SHIFT   2

#include <xdp_hw.h>

Shift bits for clock recovery options.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_HOLD

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_HOLD   0x2

#include <xdp_hw.h>

Hold adjust request to SET_VS.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC   0x0

#include <xdp_hw.h>

Increment voltage swing adjust request every training iteration.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC_4CNT

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_INC_4CNT   0x1

#include <xdp_hw.h>

Increment voltage swing adjust request every 4 or VS_SWEEP_CNT iterations.

◆ XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_NA

#define XDP_RX_MIN_VOLTAGE_SWING_CR_OPT_VS_NA   0x3

#include <xdp_hw.h>

Not applicable.

◆ XDP_RX_MIN_VOLTAGE_SWING_MIN_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_MIN_MASK   0x000003

#include <xdp_hw.h>

The minimum voltage swing level.

◆ XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_MASK (   Iteration)    (0x3 << (14 + ((Iteration - 1) * 2)))

#include <xdp_hw.h>

Table specifying what pre-emphasis level to request for each training iteration.

◆ XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_PE_TABLE_SHIFT (   Iteration)    (14 + ((Iteration - 1) * 2))

#include <xdp_hw.h>

Shift bits for pre-emphasis table.

◆ XDP_RX_MIN_VOLTAGE_SWING_SET_PE_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_MASK   0x003000

#include <xdp_hw.h>

Set pre-emphasis level.

◆ XDP_RX_MIN_VOLTAGE_SWING_SET_PE_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_SET_PE_SHIFT   12

#include <xdp_hw.h>

Shift bits for pre-emphasis setting.

◆ XDP_RX_MIN_VOLTAGE_SWING_SET_VS_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_MASK   0x000300

#include <xdp_hw.h>

Set voltage swing level.

◆ XDP_RX_MIN_VOLTAGE_SWING_SET_VS_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_SET_VS_SHIFT   8

#include <xdp_hw.h>

Shift bits for voltage swing setting.

◆ XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_MASK

#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_MASK   0x000070

#include <xdp_hw.h>

Voltage swing sweep count.

◆ XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_SHIFT

#define XDP_RX_MIN_VOLTAGE_SWING_VS_SWEEP_CNT_SHIFT   4

#include <xdp_hw.h>

Shift bits for voltage swing sweep count.

◆ XDP_RX_MISC_CTRL

#define XDP_RX_MISC_CTRL   0x018

#include <xdp_hw.h>

Miscellaneous control of RX behavior.

◆ XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK

#define XDP_RX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK   0x4

#include <xdp_hw.h>

When set, I2C DEFERs will be sent as AUX DEFERs to the source device.

◆ XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK

#define XDP_RX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK   0x2

#include <xdp_hw.h>

When set, the long I2C write data transfers are responded to using DEFER instead of partial ACKs.

◆ XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK

#define XDP_RX_MISC_CTRL_USE_FILT_MSA_MASK   0x1

#include <xdp_hw.h>

When set, two matching values must be detected for each field of the MSA values before the associated register is updated internally.

◆ XDP_RX_MSA_HRES

#define XDP_RX_MSA_HRES   0x500

#include <xdp_hw.h>

Number of active pixels per line (the horizontal resolution).

◆ XDP_RX_MSA_HSPOL

#define XDP_RX_MSA_HSPOL   0x504

#include <xdp_hw.h>

The horizontal sync polarity.

◆ XDP_RX_MSA_HSTART

#define XDP_RX_MSA_HSTART   0x50C

#include <xdp_hw.h>

Number of clocks between the leading edge of the horizontal sync and the start of active data.

◆ XDP_RX_MSA_HSWIDTH

#define XDP_RX_MSA_HSWIDTH   0x508

#include <xdp_hw.h>

Width of the horizontal sync pulse.

◆ XDP_RX_MSA_HTOTAL

#define XDP_RX_MSA_HTOTAL   0x510

#include <xdp_hw.h>

Total number of clocks in the horizontal framing period.

◆ XDP_RX_MSA_MISC0

#define XDP_RX_MSA_MISC0   0x528

#include <xdp_hw.h>

Miscellaneous stream attributes.

◆ XDP_RX_MSA_MISC1

#define XDP_RX_MSA_MISC1   0x52C

#include <xdp_hw.h>

Miscellaneous stream attributes.

◆ XDP_RX_MSA_MVID

#define XDP_RX_MSA_MVID   0x530

#include <xdp_hw.h>

Used to recover the video clock from the link clock.

◆ XDP_RX_MSA_NVID

#define XDP_RX_MSA_NVID   0x534

#include <xdp_hw.h>

Used to recover the video clock from the link clock.

◆ XDP_RX_MSA_VBID

#define XDP_RX_MSA_VBID   0x538

#include <xdp_hw.h>

The most recently received VB-ID value.

◆ XDP_RX_MSA_VHEIGHT

#define XDP_RX_MSA_VHEIGHT   0x514

#include <xdp_hw.h>

Number of active lines (the vertical resolution).

◆ XDP_RX_MSA_VSPOL

#define XDP_RX_MSA_VSPOL   0x518

#include <xdp_hw.h>

The vertical sync polarity.

◆ XDP_RX_MSA_VSTART

#define XDP_RX_MSA_VSTART   0x520

#include <xdp_hw.h>

Number of lines between the leading edge of the vertical sync and the first line of active data.

◆ XDP_RX_MSA_VSWIDTH

#define XDP_RX_MSA_VSWIDTH   0x51C

#include <xdp_hw.h>

Width of the vertical sync pulse.

◆ XDP_RX_MSA_VTOTAL

#define XDP_RX_MSA_VTOTAL   0x524

#include <xdp_hw.h>

Total number of lines in the video frame.

◆ XDP_RX_MST_ALLOC

#define XDP_RX_MST_ALLOC   0x06C

#include <xdp_hw.h>

Represents the content from the DPCD registers related to payload allocation.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_ALLOC_COUNT_TS_MASK

#define XDP_RX_MST_ALLOC_COUNT_TS_MASK   0x3F0000

#include <xdp_hw.h>

The time slot count that was issued as part of part of the most recent ALLOCATE_PAYLOAD down request.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_ALLOC_COUNT_TS_SHIFT

#define XDP_RX_MST_ALLOC_COUNT_TS_SHIFT   16

#include <xdp_hw.h>

Shift bits for the time slot count.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_ALLOC_START_TS_MASK

#define XDP_RX_MST_ALLOC_START_TS_MASK   0x003F00

#include <xdp_hw.h>

The starting time slot that was issued as part of the most recent ALLOCATE_PAYLOAD down request.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_ALLOC_START_TS_SHIFT

#define XDP_RX_MST_ALLOC_START_TS_SHIFT   8

#include <xdp_hw.h>

Shift bits for the starting time slot.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_ALLOC_VCP_ID_MASK

#define XDP_RX_MST_ALLOC_VCP_ID_MASK   0x00003F

#include <xdp_hw.h>

The virtual channel payload ID that was issued as part of the most recent ALLOCATE_PAYLOAD down request.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_CAP

#define XDP_RX_MST_CAP   0x0D0

#include <xdp_hw.h>

Used to enable or disable MST capability.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_MST_CAP_ENABLE_MASK

#define XDP_RX_MST_CAP_ENABLE_MASK   0x001

#include <xdp_hw.h>

When set to 1, enables MST mode in the RX, or disables it when 0.

◆ XDP_RX_MST_CAP_OVER_ACT_MASK

#define XDP_RX_MST_CAP_OVER_ACT_MASK   0x004

#include <xdp_hw.h>

When set to 1, overrides the ACT trigger.

This is used when software controls the virtual channel payload table.

◆ XDP_RX_MST_CAP_SOFT_VCP_MASK

#define XDP_RX_MST_CAP_SOFT_VCP_MASK   0x002

#include <xdp_hw.h>

When set to 1, enables software control over the virtual channel payload table.

◆ XDP_RX_MST_CAP_VCP_CLEAR_MASK

#define XDP_RX_MST_CAP_VCP_CLEAR_MASK   0x100

#include <xdp_hw.h>

When set to 1, clears the virtual channel payload table.

◆ XDP_RX_MST_CAP_VCP_UPDATE_MASK

#define XDP_RX_MST_CAP_VCP_UPDATE_MASK   0x010

#include <xdp_hw.h>

When set to 1, indicates to the upstream device that the virtual channel payload table has been updated.

This is used when software controls the virtual channel payload table.

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_NUM_I2C_ENTRIES_PER_PORT

#define XDP_RX_NUM_I2C_ENTRIES_PER_PORT   3

#include <xdp_hw.h>

The number of I2C user- defined entries in the I2C map of each port.

◆ XDP_RX_OVER_CTRL_DPCD

#define XDP_RX_OVER_CTRL_DPCD   0x0B8

#include <xdp_hw.h>

Used to enable AXI/APB write access to the DPCD capability structure.

◆ XDP_RX_OVER_DOWNSPREAD_CTRL

#define XDP_RX_OVER_DOWNSPREAD_CTRL   0x0BC

#include <xdp_hw.h>

Used to override downspread control in the DPCD.

◆ XDP_RX_OVER_GUID

#define XDP_RX_OVER_GUID   0x0F0

#include <xdp_hw.h>

Used to override the GUID field in the DPCD with what is stored in XDP_RX_GUID[0-3].

◆ XDP_RX_OVER_LANE_COUNT_SET

#define XDP_RX_OVER_LANE_COUNT_SET   0x0A0

#include <xdp_hw.h>

Used to override the lane count setting in the DPCD.

◆ XDP_RX_OVER_LANE_COUNT_SET_1

#define XDP_RX_OVER_LANE_COUNT_SET_1   0x1

#include <xdp_hw.h>

Lane count of 1.

◆ XDP_RX_OVER_LANE_COUNT_SET_2

#define XDP_RX_OVER_LANE_COUNT_SET_2   0x2

#include <xdp_hw.h>

Lane count of 2.

◆ XDP_RX_OVER_LANE_COUNT_SET_4

#define XDP_RX_OVER_LANE_COUNT_SET_4   0x4

#include <xdp_hw.h>

Lane count of 4.

◆ XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK

#define XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK   0x80

#include <xdp_hw.h>

Capability override for enhanced framing.

◆ XDP_RX_OVER_LANE_COUNT_SET_MASK

#define XDP_RX_OVER_LANE_COUNT_SET_MASK   0x1F

#include <xdp_hw.h>

The lane count override value.

◆ XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK

#define XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK   0x40

#include <xdp_hw.h>

Capability override for training pattern 3.

◆ XDP_RX_OVER_LINK_BW_SET

#define XDP_RX_OVER_LINK_BW_SET   0x09C

#include <xdp_hw.h>

Used to override the main link bandwidth setting in the DPCD.

◆ XDP_RX_OVER_LINK_BW_SET_162GBPS

#define XDP_RX_OVER_LINK_BW_SET_162GBPS   0x06

#include <xdp_hw.h>

1.62 Gbps link rate.

◆ XDP_RX_OVER_LINK_BW_SET_270GBPS

#define XDP_RX_OVER_LINK_BW_SET_270GBPS   0x0A

#include <xdp_hw.h>

2.70 Gbps link rate.

◆ XDP_RX_OVER_LINK_BW_SET_540GBPS

#define XDP_RX_OVER_LINK_BW_SET_540GBPS   0x14

#include <xdp_hw.h>

5.40 Gbps link rate.

◆ XDP_RX_OVER_LINK_QUAL_LANE0_SET

#define XDP_RX_OVER_LINK_QUAL_LANE0_SET   0x0C0

#include <xdp_hw.h>

Used to override the LINK_QUAL_LANE0_SET register in the DPCD.

◆ XDP_RX_OVER_LINK_QUAL_LANE1_SET

#define XDP_RX_OVER_LINK_QUAL_LANE1_SET   0x0C4

#include <xdp_hw.h>

Used to override the LINK_QUAL_LANE1_SET register in the DPCD.

◆ XDP_RX_OVER_LINK_QUAL_LANE2_SET

#define XDP_RX_OVER_LINK_QUAL_LANE2_SET   0x0C8

#include <xdp_hw.h>

Used to override the LINK_QUAL_LANE2_SET register in the DPCD.

◆ XDP_RX_OVER_LINK_QUAL_LANE3_SET

#define XDP_RX_OVER_LINK_QUAL_LANE3_SET   0x0CC

#include <xdp_hw.h>

Used to override the LINK_QUAL_LANE3_SET register in the DPCD.

◆ XDP_RX_OVER_TP_SET

#define XDP_RX_OVER_TP_SET   0x0A4

#include <xdp_hw.h>

Used to override the link training pattern in the DPCD.

◆ XDP_RX_OVER_TP_SET_LQP_SET_MASK

#define XDP_RX_OVER_TP_SET_LQP_SET_MASK   0x000C

#include <xdp_hw.h>

Link quality pattern set override.

◆ XDP_RX_OVER_TP_SET_LQP_SET_SHIFT

#define XDP_RX_OVER_TP_SET_LQP_SET_SHIFT   2

#include <xdp_hw.h>

Shift bits for link quality pattern set override.

◆ XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK

#define XDP_RX_OVER_TP_SET_REC_CLK_OUT_EN_MASK   0x0010

#include <xdp_hw.h>

Recovered clock output enable override.

◆ XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK

#define XDP_RX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK   0x0020

#include <xdp_hw.h>

Scrambling disable override.

◆ XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK

#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK   0x00C0

#include <xdp_hw.h>

Symbol error count override.

◆ XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT

#define XDP_RX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT   6

#include <xdp_hw.h>

Shift bits for symbol error count override.

◆ XDP_RX_OVER_TP_SET_TP_SELECT_MASK

#define XDP_RX_OVER_TP_SET_TP_SELECT_MASK   0x0003

#include <xdp_hw.h>

Training pattern select override.

◆ XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK

#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK   0xFF00

#include <xdp_hw.h>

Training AUX read interval override.

◆ XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT

#define XDP_RX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT   8

#include <xdp_hw.h>

Shift bits for training AUX read interval override.

◆ XDP_RX_OVER_TRAINING_LANE0_SET

#define XDP_RX_OVER_TRAINING_LANE0_SET   0x0A8

#include <xdp_hw.h>

Used to override the TRAINING_LANE0_SET register in the DPCD.

◆ XDP_RX_OVER_TRAINING_LANE1_SET

#define XDP_RX_OVER_TRAINING_LANE1_SET   0x0AC

#include <xdp_hw.h>

Used to override the TRAINING_LANE1_SET register in the DPCD.

◆ XDP_RX_OVER_TRAINING_LANE2_SET

#define XDP_RX_OVER_TRAINING_LANE2_SET   0x0B0

#include <xdp_hw.h>

Used to override the TRAINING_LANE2_SET register in the DPCD.

◆ XDP_RX_OVER_TRAINING_LANE3_SET

#define XDP_RX_OVER_TRAINING_LANE3_SET   0x0B4

#include <xdp_hw.h>

Used to override the TRAINING_LANE3_SET register in the DPCD.

◆ XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK

#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK   0x20

#include <xdp_hw.h>

Maximum pre-emphasis override.

◆ XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK

#define XDP_RX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK   0x04

#include <xdp_hw.h>

Maximum voltage swing override.

◆ XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK

#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_MASK   0x18

#include <xdp_hw.h>

Pre-emphasis set override.

◆ XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT

#define XDP_RX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT   3

#include <xdp_hw.h>

Shift bits for pre-emphasis set override.

◆ XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK

#define XDP_RX_OVER_TRAINING_LANEX_SET_VS_SET_MASK   0x03

#include <xdp_hw.h>

Voltage swing set override.

◆ XDP_RX_PHY_CONFIG

#define XDP_RX_PHY_CONFIG   0x200

#include <xdp_hw.h>

Transceiver PHY reset and configuration.

◆ XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK

#define XDP_RX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK   0x04000000

#include <xdp_hw.h>

Enable the individual lane polarity.

◆ XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK

#define XDP_RX_PHY_CONFIG_GT_ALL_RESET_MASK   0x00000003

#include <xdp_hw.h>

Reset GT and PHY.

◆ XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK

#define XDP_RX_PHY_CONFIG_GTPLL_RESET_MASK   0x00000001

#include <xdp_hw.h>

Hold the GTPLL in reset.

◆ XDP_RX_PHY_CONFIG_GTRX_RESET_MASK

#define XDP_RX_PHY_CONFIG_GTRX_RESET_MASK   0x00000002

#include <xdp_hw.h>

Hold GTRXRESET in reset.

◆ XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK

#define XDP_RX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x00000000

#include <xdp_hw.h>

Release reset.

◆ XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK

#define XDP_RX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK   0x01000000

#include <xdp_hw.h>

Issue reset at every link rate change.

◆ XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK

#define XDP_RX_PHY_CONFIG_RESET_AT_TP1_START_MASK   0x02000000

#include <xdp_hw.h>

Issue reset at start of training pattern 1.

◆ XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK

#define XDP_RX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK   0x00800000

#include <xdp_hw.h>

Issue reset at every training iteration.

◆ XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK   0x00000400

#include <xdp_hw.h>

Hold RX_PHY_BUF reset.

◆ XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK   0x00400000

#include <xdp_hw.h>

Set RX_PHY_CDRHOLD.

◆ XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK   0x00000800

#include <xdp_hw.h>

Hold RX_PHY_DFE_LPM reset.

◆ XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK   0x00010000

#include <xdp_hw.h>

Set RX_PHY_EYESCANRESET.

◆ XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK   0x00020000

#include <xdp_hw.h>

Set RX_PHY_ EYESCANTRIGGER.

◆ XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK   0x0000E000

#include <xdp_hw.h>

Set RX_PHY_LOOPBACK.

◆ XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK   0x00000200

#include <xdp_hw.h>

Hold RX_PHY_PCS reset.

◆ XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK   0x00000100

#include <xdp_hw.h>

Hold RX_PHY_PMA reset.

◆ XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK   0x08000000

#include <xdp_hw.h>

Configure RX_PHY_POLARITY for lane 0.

◆ XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK   0x10000000

#include <xdp_hw.h>

Configure RX_PHY_POLARITY for lane 1.

◆ XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK   0x20000000

#include <xdp_hw.h>

Configure RX_PHY_POLARITY for lane 2.

◆ XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK   0x40000000

#include <xdp_hw.h>

Configure RX_PHY_POLARITY for lane 3.

◆ XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_POLARITY_MASK   0x00001000

#include <xdp_hw.h>

Set RX_PHY_POLARITY.

◆ XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK   0x00040000

#include <xdp_hw.h>

Set RX_PHY_PRBSCNTRESET.

◆ XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK   0x00080000

#include <xdp_hw.h>

Set RX_PHY_RXLPMHFHOLD.

◆ XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK   0x00200000

#include <xdp_hw.h>

Set RX_PHY_ RXLPMHFOVERDEN.

◆ XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK

#define XDP_RX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK   0x00100000

#include <xdp_hw.h>

Set RX_PHY_RXLPMLFHOLD.

◆ XDP_RX_PHY_POWER_DOWN

#define XDP_RX_PHY_POWER_DOWN   0x210

#include <xdp_hw.h>

Control PHY power down.

◆ XDP_RX_PHY_POWER_DOWN_LANE_0_MASK

#define XDP_RX_PHY_POWER_DOWN_LANE_0_MASK   0x1

#include <xdp_hw.h>

Power down the PHY for lane 0.

◆ XDP_RX_PHY_POWER_DOWN_LANE_1_MASK

#define XDP_RX_PHY_POWER_DOWN_LANE_1_MASK   0x2

#include <xdp_hw.h>

Power down the PHY for lane.

◆ XDP_RX_PHY_POWER_DOWN_LANE_2_MASK

#define XDP_RX_PHY_POWER_DOWN_LANE_2_MASK   0x4

#include <xdp_hw.h>

Power down the PHY for lane.

◆ XDP_RX_PHY_POWER_DOWN_LANE_3_MASK

#define XDP_RX_PHY_POWER_DOWN_LANE_3_MASK   0x8

#include <xdp_hw.h>

Power down the PHY for lane.

◆ XDP_RX_PHY_STATUS

#define XDP_RX_PHY_STATUS   0x208

#include <xdp_hw.h>

Current PHY status.

◆ XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK

#define XDP_RX_PHY_STATUS_ALL_LANES_READY_MASK   0x0000003F

#include <xdp_hw.h>

All lanes are ready.

◆ XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK

#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK   0x00010000

#include <xdp_hw.h>

Lane alignment status for lane 0.

◆ XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK

#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK   0x00020000

#include <xdp_hw.h>

Lane alignment status for lane 1.

◆ XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK

#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK   0x00040000

#include <xdp_hw.h>

Lane alignment status for lane 2.

◆ XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK

#define XDP_RX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK   0x00080000

#include <xdp_hw.h>

Lane alignment status for lane 3.

◆ XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK

#define XDP_RX_PHY_STATUS_LANES_0_1_READY_MASK   0x00000013

#include <xdp_hw.h>

Lanes 0 and 1 are ready.

◆ XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK

#define XDP_RX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040

#include <xdp_hw.h>

FPGA fabric clock PLL locked.

◆ XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK

#define XDP_RX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010

#include <xdp_hw.h>

PLL locked for lanes 0 and 1.

◆ XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK

#define XDP_RX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020

#include <xdp_hw.h>

PLL locked for lanes 2 and 3.

◆ XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK

#define XDP_RX_PHY_STATUS_PRBSERR_LANE_0_MASK   0x00000100

#include <xdp_hw.h>

PRBS error on lane 0.

◆ XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK

#define XDP_RX_PHY_STATUS_PRBSERR_LANE_1_MASK   0x00000200

#include <xdp_hw.h>

PRBS error on lane 1.

◆ XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK

#define XDP_RX_PHY_STATUS_PRBSERR_LANE_2_MASK   0x00000400

#include <xdp_hw.h>

PRBS error on lane 2.

◆ XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK

#define XDP_RX_PHY_STATUS_PRBSERR_LANE_3_MASK   0x00000800

#include <xdp_hw.h>

PRBS error on lane 3.

◆ XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK

#define XDP_RX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK   0x00000003

#include <xdp_hw.h>

Reset done for lanes 0 and 1.

◆ XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK

#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C

#include <xdp_hw.h>

Reset done for lanes 2 and 3.

◆ XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT

#define XDP_RX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT   2

#include <xdp_hw.h>

Shift bits for reset done for lanes 2 and 3.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT   26

#include <xdp_hw.h>

Shift bits for RX buffer status lane 1.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK   0x03000000

#include <xdp_hw.h>

RX buffer status lane 0.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT   24

#include <xdp_hw.h>

Shift bits for RX buffer status lane 0.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK   0x0C000000

#include <xdp_hw.h>

RX buffer status lane 1.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK   0x30000000

#include <xdp_hw.h>

RX buffer status lane 2.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT   28

#include <xdp_hw.h>

Shift bits for RX buffer status lane 2.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK   0xC0000000

#include <xdp_hw.h>

RX buffer status lane 3.

◆ XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT

#define XDP_RX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT   30

#include <xdp_hw.h>

Shift bits for RX buffer status lane 3.

◆ XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK

#define XDP_RX_PHY_STATUS_RX_CLK_LOCK_MASK   0x00000080

#include <xdp_hw.h>

Receiver clock locked.

◆ XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK

#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_0_MASK   0x00001000

#include <xdp_hw.h>

RX voltage low on lane 0.

◆ XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK

#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_1_MASK   0x00002000

#include <xdp_hw.h>

RX voltage low on lane.

◆ XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK

#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_2_MASK   0x00004000

#include <xdp_hw.h>

RX voltage low on lane.

◆ XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK

#define XDP_RX_PHY_STATUS_RX_VLOW_LANE_3_MASK   0x00008000

#include <xdp_hw.h>

RX voltage low on lane.

◆ XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK

#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_0_MASK   0x00100000

#include <xdp_hw.h>

Symbol lock status for lane 0.

◆ XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK

#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_1_MASK   0x00200000

#include <xdp_hw.h>

Symbol lock status for lane 1.

◆ XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK

#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_2_MASK   0x00400000

#include <xdp_hw.h>

Symbol lock status for lane 2.

◆ XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK

#define XDP_RX_PHY_STATUS_SYM_LOCK_LANE_3_MASK   0x00800000

#include <xdp_hw.h>

Symbol lock status for lane 3.

◆ XDP_RX_REMOTE_CMD

#define XDP_RX_REMOTE_CMD   0x08C

#include <xdp_hw.h>

Used for passing remote information to the DisplayPort TX.

◆ XDP_RX_REQ_ADDRESS

#define XDP_RX_REQ_ADDRESS   0x038

#include <xdp_hw.h>

Contains the address field of the most recent AUX request.

◆ XDP_RX_REQ_CLK_WIDTH

#define XDP_RX_REQ_CLK_WIDTH   0x030

#include <xdp_hw.h>

Holds the half period of the recovered AUX clock.

◆ XDP_RX_REQ_CMD

#define XDP_RX_REQ_CMD   0x034

#include <xdp_hw.h>

Provides the most recent AUX command received.

◆ XDP_RX_REQ_COUNT

#define XDP_RX_REQ_COUNT   0x028

#include <xdp_hw.h>

Provides a running total of the number of AUX requests received.

◆ XDP_RX_REQ_ERROR_COUNT

#define XDP_RX_REQ_ERROR_COUNT   0x024

#include <xdp_hw.h>

Provides a running total of errors detected on inbound AUX channel requests.

◆ XDP_RX_REQ_LENGTH

#define XDP_RX_REQ_LENGTH   0x03C

#include <xdp_hw.h>

Contains length of the most recent AUX request.

◆ XDP_RX_SINK_COUNT

#define XDP_RX_SINK_COUNT   0x0D4

#include <xdp_hw.h>

The sink device count.

◆ XDP_RX_SINK_DEVICE_SPECIFIC_FIELD

#define XDP_RX_SINK_DEVICE_SPECIFIC_FIELD   0xF00

#include <xdp_hw.h>

User access to the sink specific field as exposed in the RX DPCD (0xFF bytes).

◆ XDP_RX_SOFT_RESET

#define XDP_RX_SOFT_RESET   0x01C

#include <xdp_hw.h>

Software reset.

◆ XDP_RX_SOFT_RESET_AUX_MASK

#define XDP_RX_SOFT_RESET_AUX_MASK   0x80

#include <xdp_hw.h>

Reset the AUX logic.

◆ XDP_RX_SOFT_RESET_VIDEO_MASK

#define XDP_RX_SOFT_RESET_VIDEO_MASK   0x01

#include <xdp_hw.h>

Reset the video logic.

◆ XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD

#define XDP_RX_SOURCE_DEVICE_SPECIFIC_FIELD   0xE00

#include <xdp_hw.h>

User access to the source specific field as exposed in the RX DPCD (0xFF bytes).

◆ XDP_RX_STREAM1_MSA_START

#define XDP_RX_STREAM1_MSA_START   0x500

#include <xdp_hw.h>

Start of the MSA registers for stream 1.

◆ XDP_RX_STREAM2_MSA_START

#define XDP_RX_STREAM2_MSA_START   0x540

#include <xdp_hw.h>

Start of the MSA registers for stream 2.

◆ XDP_RX_STREAM2_MSA_START_OFFSET

#define XDP_RX_STREAM2_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_RX_STREAM1_MSA_START)
#define XDP_RX_STREAM2_MSA_START
Start of the MSA registers for stream 2.
Definition: xdp_hw.h:1642

The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().

◆ XDP_RX_STREAM3_MSA_START

#define XDP_RX_STREAM3_MSA_START   0x580

#include <xdp_hw.h>

Start of the MSA registers for stream 3.

◆ XDP_RX_STREAM3_MSA_START_OFFSET

#define XDP_RX_STREAM3_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_RX_STREAM1_MSA_START)
#define XDP_RX_STREAM3_MSA_START
Start of the MSA registers for stream 3.
Definition: xdp_hw.h:1655

The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().

◆ XDP_RX_STREAM4_MSA_START

#define XDP_RX_STREAM4_MSA_START   0x5C0

#include <xdp_hw.h>

Start of the MSA registers for stream 4.

◆ XDP_RX_STREAM4_MSA_START_OFFSET

#define XDP_RX_STREAM4_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_RX_STREAM1_MSA_START)
#define XDP_RX_STREAM4_MSA_START
Start of the MSA registers for stream 4.
Definition: xdp_hw.h:1668

The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_RxGetBpc(), XDp_RxGetColorComponent(), and XDp_RxSetLineReset().

◆ XDP_RX_USER_FIFO_OVERFLOW

#define XDP_RX_USER_FIFO_OVERFLOW   0x110

#include <xdp_hw.h>

Indicates an overflow in user FIFO.

◆ XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK

#define XDP_RX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK (   Stream)    (Stream)

#include <xdp_hw.h>

Indicates that the internal FIFO has detected on overflow condition for the specified stream.

◆ XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK

#define XDP_RX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK (   Stream)    (Stream << 8)

#include <xdp_hw.h>

Indicates that the video timing FIFO has overflown for the specified stream.

◆ XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK

#define XDP_RX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK (   Stream)    (Stream << 4)

#include <xdp_hw.h>

Indicates that the video unpack FIFO has overflown for the specified stream.

◆ XDP_RX_USER_PIXEL_WIDTH

#define XDP_RX_USER_PIXEL_WIDTH   0x010

#include <xdp_hw.h>

Selects the width of the user data input port.

◆ XDP_RX_USER_PIXEL_WIDTH_1

#define XDP_RX_USER_PIXEL_WIDTH_1   0x1

#include <xdp_hw.h>

Single pixel wide interface.

◆ XDP_RX_USER_PIXEL_WIDTH_2

#define XDP_RX_USER_PIXEL_WIDTH_2   0x2

#include <xdp_hw.h>

Dual pixel output mode.

◆ XDP_RX_USER_PIXEL_WIDTH_4

#define XDP_RX_USER_PIXEL_WIDTH_4   0x4

#include <xdp_hw.h>

Quad pixel output mode.

◆ XDP_RX_USER_VSYNC_STATE

#define XDP_RX_USER_VSYNC_STATE   0x114

#include <xdp_hw.h>

Provides a mechanism for the host processor to monitor the state of the video data path.

◆ XDP_RX_USER_VSYNC_STATE_STREAMX_MASK

#define XDP_RX_USER_VSYNC_STATE_STREAMX_MASK (   Stream)    (Stream)

#include <xdp_hw.h>

The state of the vertical sync pulse for the specified stream.

◆ XDP_RX_VC_PAYLOAD_TABLE

#define XDP_RX_VC_PAYLOAD_TABLE   0x800

#include <xdp_hw.h>

Virtual channel payload table (0xFF bytes).

Referenced by XDp_RxAllocatePayloadStream().

◆ XDP_RX_VERSION

#define XDP_RX_VERSION   0x0F8

#include <xdp_hw.h>

Version and revision of the DisplayPort core.

◆ XDP_RX_VERSION_CORE_PATCH_MASK

#define XDP_RX_VERSION_CORE_PATCH_MASK   0x00000030

#include <xdp_hw.h>

Core patch details.

◆ XDP_RX_VERSION_CORE_PATCH_SHIFT

#define XDP_RX_VERSION_CORE_PATCH_SHIFT   8

#include <xdp_hw.h>

Shift bits for core patch details.

◆ XDP_RX_VERSION_CORE_VER_MJR_MASK

#define XDP_RX_VERSION_CORE_VER_MJR_MASK   0x0000F000

#include <xdp_hw.h>

Core major version.

◆ XDP_RX_VERSION_CORE_VER_MJR_SHIFT

#define XDP_RX_VERSION_CORE_VER_MJR_SHIFT   24

#include <xdp_hw.h>

Shift bits for core major version.

◆ XDP_RX_VERSION_CORE_VER_MNR_MASK

#define XDP_RX_VERSION_CORE_VER_MNR_MASK   0x00000F00

#include <xdp_hw.h>

Core minor version.

◆ XDP_RX_VERSION_CORE_VER_MNR_SHIFT

#define XDP_RX_VERSION_CORE_VER_MNR_SHIFT   16

#include <xdp_hw.h>

Shift bits for core minor version.

◆ XDP_RX_VERSION_CORE_VER_REV_MASK

#define XDP_RX_VERSION_CORE_VER_REV_MASK   0x000000C0

#include <xdp_hw.h>

Core version revision.

◆ XDP_RX_VERSION_CORE_VER_REV_SHIFT

#define XDP_RX_VERSION_CORE_VER_REV_SHIFT   12

#include <xdp_hw.h>

Shift bits for core version revision.

◆ XDP_RX_VERSION_INTER_REV_MASK

#define XDP_RX_VERSION_INTER_REV_MASK   0x0000000F

#include <xdp_hw.h>

Internal revision.

◆ XDP_RX_VIDEO_UNSUPPORTED

#define XDP_RX_VIDEO_UNSUPPORTED   0x094

#include <xdp_hw.h>

DPCD register bit to inform the DisplayPort TX that video data is not supported.

◆ XDP_RX_VSYNC_WIDTH

#define XDP_RX_VSYNC_WIDTH   0x058

#include <xdp_hw.h>

Controls the timing of the active-high vertical sync pulse generated by the display timing generator (DTG).

◆ XDP_TX_AUDIO_CHANNELS

#define XDP_TX_AUDIO_CHANNELS   0x304

#include <xdp_hw.h>

Used to input active channel count.

◆ XDP_TX_AUDIO_CONTROL

#define XDP_TX_AUDIO_CONTROL   0x300

#include <xdp_hw.h>

Enables audio stream packets in main link and buffer control.

◆ XDP_TX_AUDIO_EXT_DATA

#define XDP_TX_AUDIO_EXT_DATA (   NUM)    (0x330 + 4 * (NUM - 1))

#include <xdp_hw.h>

Word formatted as per extension packet.

◆ XDP_TX_AUDIO_INFO_DATA

#define XDP_TX_AUDIO_INFO_DATA (   NUM)    (0x308 + 4 * (NUM - 1))

#include <xdp_hw.h>

Word formatted as per CEA 861-C info frame.

◆ XDP_TX_AUDIO_MAUD

#define XDP_TX_AUDIO_MAUD   0x328

#include <xdp_hw.h>

M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.

◆ XDP_TX_AUDIO_NAUD

#define XDP_TX_AUDIO_NAUD   0x32C

#include <xdp_hw.h>

N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.

◆ XDP_TX_AUX_ADDRESS

#define XDP_TX_AUX_ADDRESS   0x108

#include <xdp_hw.h>

Specifies the address of current AUX command.

◆ XDP_TX_AUX_CLK_DIVIDER

#define XDP_TX_AUX_CLK_DIVIDER   0x10C

#include <xdp_hw.h>

Clock divider value for generating the internal 1MHz clock.

◆ XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK

#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK   0xFF00

#include <xdp_hw.h>

AUX (noise) signal width filter.

◆ XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT

#define XDP_TX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT   8

#include <xdp_hw.h>

Shift bits for AUX signal width filter.

◆ XDP_TX_AUX_CLK_DIVIDER_VAL_MASK

#define XDP_TX_AUX_CLK_DIVIDER_VAL_MASK   0x00FF

#include <xdp_hw.h>

Clock divider value.

◆ XDP_TX_AUX_CMD

#define XDP_TX_AUX_CMD   0x100

#include <xdp_hw.h>

Initiates AUX commands.

◆ XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN

#define XDP_TX_AUX_CMD_ADDR_ONLY_TRANSFER_EN   0x00001000

#include <xdp_hw.h>

Address only transfer enable (STOP will be sent after command).

◆ XDP_TX_AUX_CMD_I2C_READ

#define XDP_TX_AUX_CMD_I2C_READ   0x1

#include <xdp_hw.h>

I2C-over-AUX read command.

◆ XDP_TX_AUX_CMD_I2C_READ_MOT

#define XDP_TX_AUX_CMD_I2C_READ_MOT   0x5

#include <xdp_hw.h>

I2C-over-AUX read MOT (middle-of-transaction) command.

◆ XDP_TX_AUX_CMD_I2C_WRITE

#define XDP_TX_AUX_CMD_I2C_WRITE   0x0

#include <xdp_hw.h>

I2C-over-AUX write command.

◆ XDP_TX_AUX_CMD_I2C_WRITE_MOT

#define XDP_TX_AUX_CMD_I2C_WRITE_MOT   0x4

#include <xdp_hw.h>

I2C-over-AUX write MOT (middle-of-transaction) command.

◆ XDP_TX_AUX_CMD_I2C_WRITE_STATUS

#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS   0x2

#include <xdp_hw.h>

I2C-over-AUX write status command.

◆ XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT

#define XDP_TX_AUX_CMD_I2C_WRITE_STATUS_MOT   0x6

#include <xdp_hw.h>

I2C-over-AUX write status MOT (middle-of- transaction) command.

◆ XDP_TX_AUX_CMD_MASK

#define XDP_TX_AUX_CMD_MASK   0x00000F00

#include <xdp_hw.h>

AUX command.

◆ XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK

#define XDP_TX_AUX_CMD_NBYTES_TRANSFER_MASK   0x0000000F

#include <xdp_hw.h>

Number of bytes to transfer with the current AUX command.

◆ XDP_TX_AUX_CMD_READ

#define XDP_TX_AUX_CMD_READ   0x9

#include <xdp_hw.h>

AUX read command.

◆ XDP_TX_AUX_CMD_SHIFT

#define XDP_TX_AUX_CMD_SHIFT   8

#include <xdp_hw.h>

Shift bits for command.

◆ XDP_TX_AUX_CMD_WRITE

#define XDP_TX_AUX_CMD_WRITE   0x8

#include <xdp_hw.h>

AUX write command.

◆ XDP_TX_AUX_REPLY_CODE

#define XDP_TX_AUX_REPLY_CODE   0x138

#include <xdp_hw.h>

Reply code received from the most recent AUX command.

◆ XDP_TX_AUX_REPLY_CODE_ACK

#define XDP_TX_AUX_REPLY_CODE_ACK   0x0

#include <xdp_hw.h>

AUX command ACKed.

◆ XDP_TX_AUX_REPLY_CODE_DEFER

#define XDP_TX_AUX_REPLY_CODE_DEFER   0x2

#include <xdp_hw.h>

AUX command deferred.

◆ XDP_TX_AUX_REPLY_CODE_I2C_ACK

#define XDP_TX_AUX_REPLY_CODE_I2C_ACK   0x0

#include <xdp_hw.h>

I2C-over-AUX command not ACKed.

◆ XDP_TX_AUX_REPLY_CODE_I2C_DEFER

#define XDP_TX_AUX_REPLY_CODE_I2C_DEFER   0x8

#include <xdp_hw.h>

I2C-over-AUX command deferred.

◆ XDP_TX_AUX_REPLY_CODE_I2C_NACK

#define XDP_TX_AUX_REPLY_CODE_I2C_NACK   0x4

#include <xdp_hw.h>

I2C-over-AUX command not ACKed.

◆ XDP_TX_AUX_REPLY_CODE_NACK

#define XDP_TX_AUX_REPLY_CODE_NACK   0x1

#include <xdp_hw.h>

AUX command not ACKed.

◆ XDP_TX_AUX_REPLY_COUNT

#define XDP_TX_AUX_REPLY_COUNT   0x13C

#include <xdp_hw.h>

Number of reply transactions received over AUX.

◆ XDP_TX_AUX_REPLY_DATA

#define XDP_TX_AUX_REPLY_DATA   0x134

#include <xdp_hw.h>

Reply data received during the AUX reply.

◆ XDP_TX_AUX_WRITE_FIFO

#define XDP_TX_AUX_WRITE_FIFO   0x104

#include <xdp_hw.h>

Write data for the current AUX command.

◆ XDP_TX_CORE_ID

#define XDP_TX_CORE_ID   0x0FC

#include <xdp_hw.h>

DisplayPort protocol version and revision.

◆ XDP_TX_CORE_ID_DP_MJR_VER_MASK

#define XDP_TX_CORE_ID_DP_MJR_VER_MASK   0x0000F000

#include <xdp_hw.h>

DisplayPort protocol major version.

◆ XDP_TX_CORE_ID_DP_MJR_VER_SHIFT

#define XDP_TX_CORE_ID_DP_MJR_VER_SHIFT   24

#include <xdp_hw.h>

Shift bits for DisplayPort protocol major version.

◆ XDP_TX_CORE_ID_DP_MNR_VER_MASK

#define XDP_TX_CORE_ID_DP_MNR_VER_MASK   0x00000F00

#include <xdp_hw.h>

DisplayPort protocol minor version.

◆ XDP_TX_CORE_ID_DP_MNR_VER_SHIFT

#define XDP_TX_CORE_ID_DP_MNR_VER_SHIFT   16

#include <xdp_hw.h>

Shift bits for DisplayPort protocol major version.

◆ XDP_TX_CORE_ID_DP_REV_MASK

#define XDP_TX_CORE_ID_DP_REV_MASK   0x000000F0

#include <xdp_hw.h>

DisplayPort protocol revision.

◆ XDP_TX_CORE_ID_DP_REV_SHIFT

#define XDP_TX_CORE_ID_DP_REV_SHIFT   8

#include <xdp_hw.h>

Shift bits for DisplayPort protocol revision.

◆ XDP_TX_CORE_ID_TYPE_MASK

#define XDP_TX_CORE_ID_TYPE_MASK   0x0000000F

#include <xdp_hw.h>

Core type.

◆ XDP_TX_CORE_ID_TYPE_RX

#define XDP_TX_CORE_ID_TYPE_RX   0x1

#include <xdp_hw.h>

Core is a receiver.

◆ XDP_TX_CORE_ID_TYPE_TX

#define XDP_TX_CORE_ID_TYPE_TX   0x0

#include <xdp_hw.h>

Core is a transmitter.

◆ XDP_TX_DOWNSPREAD_CTRL

#define XDP_TX_DOWNSPREAD_CTRL   0x018

#include <xdp_hw.h>

Enable a 0.5% spreading of the clock.

◆ XDP_TX_ENABLE

#define XDP_TX_ENABLE   0x080

#include <xdp_hw.h>

Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled.

◆ XDP_TX_ENABLE_MAIN_STREAM

#define XDP_TX_ENABLE_MAIN_STREAM   0x084

#include <xdp_hw.h>

Enable transmission of main link video info.

◆ XDP_TX_ENABLE_SEC_STREAM

#define XDP_TX_ENABLE_SEC_STREAM   0x088

#include <xdp_hw.h>

Enable the transmission of secondary link info.

◆ XDP_TX_ENHANCED_FRAME_EN

#define XDP_TX_ENHANCED_FRAME_EN   0x008

#include <xdp_hw.h>

Enable enhanced framing symbol sequence.

◆ XDP_TX_FORCE_SCRAMBLER_RESET

#define XDP_TX_FORCE_SCRAMBLER_RESET   0x0C0

#include <xdp_hw.h>

Force a scrambler reset.

◆ XDP_TX_FRAC_BYTES_PER_TU

#define XDP_TX_FRAC_BYTES_PER_TU   0x1C8

#include <xdp_hw.h>

The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value.

◆ XDP_TX_GT_DRP_CHANNEL_STATUS

#define XDP_TX_GT_DRP_CHANNEL_STATUS   0x2A8

#include <xdp_hw.h>

Provides access to GT DRP channel status.

◆ XDP_TX_GT_DRP_COMMAND

#define XDP_TX_GT_DRP_COMMAND   0x2A0

#include <xdp_hw.h>

Provides access to the GT DRP ports.

◆ XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK

#define XDP_TX_GT_DRP_COMMAND_DRP_ADDR_MASK   0x000F

#include <xdp_hw.h>

DRP address.

◆ XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK

#define XDP_TX_GT_DRP_COMMAND_DRP_RW_CMD_MASK   0x0080

#include <xdp_hw.h>

DRP read/write command (Read=0, Write=1).

◆ XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK

#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_MASK   0xFF00

#include <xdp_hw.h>

DRP write data.

◆ XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT

#define XDP_TX_GT_DRP_COMMAND_DRP_W_DATA_SHIFT   16

#include <xdp_hw.h>

Shift bits for DRP write data.

◆ XDP_TX_GT_DRP_READ_DATA

#define XDP_TX_GT_DRP_READ_DATA   0x2A4

#include <xdp_hw.h>

Provides access to GT DRP read data.

◆ XDP_TX_HDCP_ENABLE

#define XDP_TX_HDCP_ENABLE   0x400

#include <xdp_hw.h>

Enables HDCP core.

◆ XDP_TX_HDCP_ENABLE_BYPASS_DISABLE_MASK

#define XDP_TX_HDCP_ENABLE_BYPASS_DISABLE_MASK   0x0001

#include <xdp_hw.h>

Disables bypass of the HDCP core.

◆ XDP_TX_HPD_DURATION

#define XDP_TX_HPD_DURATION   0x150

#include <xdp_hw.h>

Duration of the HPD pulse in microseconds.

◆ XDP_TX_INIT_WAIT

#define XDP_TX_INIT_WAIT   0x1CC

#include <xdp_hw.h>

Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.

◆ XDP_TX_INTERRUPT_MASK

#define XDP_TX_INTERRUPT_MASK   0x144

#include <xdp_hw.h>

Masks the specified interrupt sources.

◆ XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK

#define XDP_TX_INTERRUPT_MASK_EXT_PKT_TXD_MASK   0x00000020

#include <xdp_hw.h>

Mask extended packet transmit interrupt.

◆ XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK

#define XDP_TX_INTERRUPT_MASK_HPD_EVENT_MASK   0x00000002

#include <xdp_hw.h>

Mask HPD event interrupt.

◆ XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK

#define XDP_TX_INTERRUPT_MASK_HPD_IRQ_MASK   0x00000001

#include <xdp_hw.h>

Mask HPD IRQ interrupt.

◆ XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK

#define XDP_TX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK   0x00000010

#include <xdp_hw.h>

Mask HPD pulse detected interrupt.

◆ XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK

#define XDP_TX_INTERRUPT_MASK_REPLY_RECEIVED_MASK   0x00000004

#include <xdp_hw.h>

Mask reply received interrupt.

◆ XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK

#define XDP_TX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK   0x00000008

#include <xdp_hw.h>

Mask reply received interrupt.

◆ XDP_TX_INTERRUPT_SIG_STATE

#define XDP_TX_INTERRUPT_SIG_STATE   0x130

#include <xdp_hw.h>

The raw signal values for interrupt events.

◆ XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK

#define XDP_TX_INTERRUPT_SIG_STATE_HPD_STATE_MASK   0x00000001

#include <xdp_hw.h>

Raw state of the HPD pin on the DP connector.

◆ XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK

#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_STATE_MASK   0x00000004

#include <xdp_hw.h>

A reply is currently being received.

◆ XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK

#define XDP_TX_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK   0x00000008

#include <xdp_hw.h>

A reply timeout has occurred.

◆ XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK

#define XDP_TX_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK   0x00000002

#include <xdp_hw.h>

A request is currently being sent.

◆ XDP_TX_INTERRUPT_STATUS

#define XDP_TX_INTERRUPT_STATUS   0x140

#include <xdp_hw.h>

Status for interrupt events.

◆ XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK

#define XDP_TX_INTERRUPT_STATUS_EXT_PKT_TXD_MASK   0x00000020

#include <xdp_hw.h>

Extended packet has been transmitted and the core is ready to accept a new packet.

◆ XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK

#define XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK   0x00000002

#include <xdp_hw.h>

Detected the presence of the HPD signal.

◆ XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK

#define XDP_TX_INTERRUPT_STATUS_HPD_IRQ_MASK   0x00000001

#include <xdp_hw.h>

Detected an IRQ framed with the proper timing on the HPD signal.

◆ XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK

#define XDP_TX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK   0x00000010

#include <xdp_hw.h>

A pulse on the HPD line was detected.

◆ XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK

#define XDP_TX_INTERRUPT_STATUS_REPLY_RECEIVED_MASK   0x00000004

#include <xdp_hw.h>

An AUX reply transaction has been detected.

◆ XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK

#define XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK   0x00000008

#include <xdp_hw.h>

A reply timeout has occurred.

◆ XDP_TX_LANE_COUNT_SET

#define XDP_TX_LANE_COUNT_SET   0x004

#include <xdp_hw.h>

Set lane count setting.

◆ XDP_TX_LANE_COUNT_SET_1

#define XDP_TX_LANE_COUNT_SET_1   0x01

#include <xdp_hw.h>

Lane count of 1.

Referenced by XDp_IsLaneCountValid().

◆ XDP_TX_LANE_COUNT_SET_2

#define XDP_TX_LANE_COUNT_SET_2   0x02

#include <xdp_hw.h>

Lane count of 2.

Referenced by XDp_IsLaneCountValid().

◆ XDP_TX_LANE_COUNT_SET_4

#define XDP_TX_LANE_COUNT_SET_4   0x04

#include <xdp_hw.h>

Lane count of 4.

Referenced by XDp_IsLaneCountValid().

◆ XDP_TX_LINE_RESET_DISABLE

#define XDP_TX_LINE_RESET_DISABLE   0x0F0

#include <xdp_hw.h>

TX line reset disable.

◆ XDP_TX_LINE_RESET_DISABLE_MASK

#define XDP_TX_LINE_RESET_DISABLE_MASK (   Stream)    (1 << ((Stream) - XDP_TX_STREAM_ID1))

#include <xdp_hw.h>

Used to disable the end of the line reset to the internal video pipe.

◆ XDP_TX_LINK_BW_SET

#define XDP_TX_LINK_BW_SET   0x000

#include <xdp_hw.h>

Set main link bandwidth setting.

◆ XDP_TX_LINK_BW_SET_162GBPS

#define XDP_TX_LINK_BW_SET_162GBPS   0x06

#include <xdp_hw.h>

1.62 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_TX_LINK_BW_SET_270GBPS

#define XDP_TX_LINK_BW_SET_270GBPS   0x0A

#include <xdp_hw.h>

2.70 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_TX_LINK_BW_SET_540GBPS

#define XDP_TX_LINK_BW_SET_540GBPS   0x14

#include <xdp_hw.h>

5.40 Gbps link rate.

Referenced by XDp_IsLinkRateValid().

◆ XDP_TX_LINK_QUAL_PATTERN_SET

#define XDP_TX_LINK_QUAL_PATTERN_SET   0x010

#include <xdp_hw.h>

Transmit the link quality pattern.

◆ XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST

#define XDP_TX_LINK_QUAL_PATTERN_SET_D102_TEST   0x1

#include <xdp_hw.h>

D10.2 unscrambled test pattern transmitted.

◆ XDP_TX_LINK_QUAL_PATTERN_SET_OFF

#define XDP_TX_LINK_QUAL_PATTERN_SET_OFF   0x0

#include <xdp_hw.h>

Link quality test pattern not transmitted.

◆ XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7

#define XDP_TX_LINK_QUAL_PATTERN_SET_PRBS7   0x3

#include <xdp_hw.h>

Pseudo random bit sequence 7 transmitted.

◆ XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES

#define XDP_TX_LINK_QUAL_PATTERN_SET_SER_MES   0x2

#include <xdp_hw.h>

Symbol error rate measurement pattern transmitted.

◆ XDP_TX_M_VID

#define XDP_TX_M_VID   0x1AC

#include <xdp_hw.h>

M value for the video stream as computed by the source core in asynchronous clock mode.

Must be written in synchronous mode.

◆ XDP_TX_MAIN_STREAM_HRES

#define XDP_TX_MAIN_STREAM_HRES   0x194

#include <xdp_hw.h>

Number of active pixels per line (the horizontal resolution).

◆ XDP_TX_MAIN_STREAM_HSTART

#define XDP_TX_MAIN_STREAM_HSTART   0x19C

#include <xdp_hw.h>

Number of clocks between the leading edge of the horizontal sync and the start of active data.

◆ XDP_TX_MAIN_STREAM_HSWIDTH

#define XDP_TX_MAIN_STREAM_HSWIDTH   0x18C

#include <xdp_hw.h>

Width of the horizontal sync pulse.

◆ XDP_TX_MAIN_STREAM_HTOTAL

#define XDP_TX_MAIN_STREAM_HTOTAL   0x180

#include <xdp_hw.h>

Total number of clocks in the horizontal framing period.

◆ XDP_TX_MAIN_STREAM_INTERLACED

#define XDP_TX_MAIN_STREAM_INTERLACED   0x1C0

#include <xdp_hw.h>

Video is interlaced.

◆ XDP_TX_MAIN_STREAM_MISC0

#define XDP_TX_MAIN_STREAM_MISC0   0x1A4

#include <xdp_hw.h>

Miscellaneous stream attributes.

◆ XDP_TX_MAIN_STREAM_MISC1

#define XDP_TX_MAIN_STREAM_MISC1   0x1A8

#include <xdp_hw.h>

Miscellaneous stream attributes.

◆ XDP_TX_MAIN_STREAM_POLARITY

#define XDP_TX_MAIN_STREAM_POLARITY   0x188

#include <xdp_hw.h>

Polarity for the video sync signals.

◆ XDP_TX_MAIN_STREAM_VRES

#define XDP_TX_MAIN_STREAM_VRES   0x198

#include <xdp_hw.h>

Number of active lines (the vertical resolution).

◆ XDP_TX_MAIN_STREAM_VSTART

#define XDP_TX_MAIN_STREAM_VSTART   0x1A0

#include <xdp_hw.h>

Number of lines between the leading edge of the vertical sync and the first line of active data.

◆ XDP_TX_MAIN_STREAM_VSWIDTH

#define XDP_TX_MAIN_STREAM_VSWIDTH   0x190

#include <xdp_hw.h>

Width of the vertical sync pulse.

◆ XDP_TX_MAIN_STREAM_VTOTAL

#define XDP_TX_MAIN_STREAM_VTOTAL   0x184

#include <xdp_hw.h>

Total number of lines in the video frame.

◆ XDP_TX_MAIN_STREAMX_MISC0_AUD_INSERT_TIMESTAMP_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_AUD_INSERT_TIMESTAMP_MASK   0x00000400

#include <xdp_hw.h>

Inserts info/timestamp every 512 BS symbols.

◆ XDP_TX_MAIN_STREAMX_MISC0_AUD_MODE_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_AUD_MODE_MASK   0x00000200

#include <xdp_hw.h>

Audio clock modes, Setting this bit to 1 enables sync mode.

◆ XDP_TX_MAIN_STREAMX_MISC0_AUD_UNMASK_LOWER_MAUD_BITS_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_AUD_UNMASK_LOWER_MAUD_BITS_MASK   0x00000800

#include <xdp_hw.h>

Unmasks lower 2-bits of Maud value.

Masked by default

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_10BPC   0x2

#include <xdp_hw.h>

10 bits per component.

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_12BPC   0x3

#include <xdp_hw.h>

12 bits per component.

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_16BPC   0x4

#include <xdp_hw.h>

16 bits per component.

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_6BPC   0x0

#include <xdp_hw.h>

6 bits per component.

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_8BPC   0x1

#include <xdp_hw.h>

8 bits per component.

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_MASK   0x000000E0

#include <xdp_hw.h>

Bit depth per color component (BDC).

◆ XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT

#define XDP_TX_MAIN_STREAMX_MISC0_BDC_SHIFT   5

#include <xdp_hw.h>

Shift bits for BDC.

◆ XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK   0x00000006

#include <xdp_hw.h>

Component format.

◆ XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB

#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB   0x0

#include <xdp_hw.h>

Stream's component format is RGB.

◆ XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT

#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT   1

#include <xdp_hw.h>

Shift bits for component format.

◆ XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422

#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422   0x5

#include <xdp_hw.h>

Stream's component format is YcbCr 4:2:2.

◆ XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444

#define XDP_TX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444   0x6

#include <xdp_hw.h>

Stream's component format is YcbCr 4:4:4.

◆ XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_CEA

#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_CEA   1

#include <xdp_hw.h>

CEA range.

◆ XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK   0x00000008

#include <xdp_hw.h>

Dynamic range.

◆ XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT

#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT   3

#include <xdp_hw.h>

Shift bits for dynamic range.

◆ XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_VESA

#define XDP_TX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_VESA   0

#include <xdp_hw.h>

VESA range.

◆ XDP_TX_MAIN_STREAMX_MISC0_OVERRIDE_CLOCKING_MODE_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_OVERRIDE_CLOCKING_MODE_MASK   0x00000100

#include <xdp_hw.h>

Override Audio clk Mode.

◆ XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK   0x00000001

#include <xdp_hw.h>

Synchronous clock.

◆ XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT601

#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT601   0

#include <xdp_hw.h>

ITU BT601 YCbCr coefficients.

◆ XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT709

#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_BT709   1

#include <xdp_hw.h>

ITU BT709 YCbCr coefficients.

◆ XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK

#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK   0x00000010

#include <xdp_hw.h>

YCbCr colorimetry.

◆ XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT

#define XDP_TX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT   4

#include <xdp_hw.h>

Shift bits for YCbCr colorimetry.

◆ XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK

#define XDP_TX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK   0x00000001

#include <xdp_hw.h>

Interlaced vertical total even.

◆ XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK

#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK   0x00000006

#include <xdp_hw.h>

Stereo video attribute.

◆ XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT

#define XDP_TX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT   1

#include <xdp_hw.h>

Shift bits for stereo video attribute.

◆ XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK

#define XDP_TX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK   0x00000001

#include <xdp_hw.h>

Polarity of the horizontal sync pulse.

◆ XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK

#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK   0x00000002

#include <xdp_hw.h>

Polarity of the vertical sync pulse.

◆ XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT

#define XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT   1

#include <xdp_hw.h>

Shift bits for polarity of the vertical sync pulse.

◆ XDP_TX_MIN_BYTES_PER_TU

#define XDP_TX_MIN_BYTES_PER_TU   0x1C4

#include <xdp_hw.h>

The minimum number of bytes per transfer unit.

◆ XDP_TX_MST_CONFIG

#define XDP_TX_MST_CONFIG   0x0D0

#include <xdp_hw.h>

Enable MST.

◆ XDP_TX_MST_CONFIG_MST_EN_MASK

#define XDP_TX_MST_CONFIG_MST_EN_MASK   0x00000001

#include <xdp_hw.h>

Enable MST.

◆ XDP_TX_MST_CONFIG_VCP_UPDATED_MASK

#define XDP_TX_MST_CONFIG_VCP_UPDATED_MASK   0x00000002

#include <xdp_hw.h>

The VC payload has been updated in the sink.

◆ XDP_TX_N_VID

#define XDP_TX_N_VID   0x1B4

#include <xdp_hw.h>

N value for the video stream as computed by the source core in asynchronous clock mode.

Must be written in synchronous mode.

◆ XDP_TX_PE_LEVEL_0

#define XDP_TX_PE_LEVEL_0   0x00

#include <xdp_hw.h>

Pre-emphasis level 0.

◆ XDP_TX_PE_LEVEL_1

#define XDP_TX_PE_LEVEL_1   0x0E

#include <xdp_hw.h>

Pre-emphasis level 1.

◆ XDP_TX_PE_LEVEL_2

#define XDP_TX_PE_LEVEL_2   0x14

#include <xdp_hw.h>

Pre-emphasis level 2.

◆ XDP_TX_PE_LEVEL_3

#define XDP_TX_PE_LEVEL_3   0x1B

#include <xdp_hw.h>

Pre-emphasis level 3.

◆ XDP_TX_PHY_CLOCK_SELECT

#define XDP_TX_PHY_CLOCK_SELECT   0x234

#include <xdp_hw.h>

Instructs the PHY PLL to generate the proper clock frequency for the required link rate.

◆ XDP_TX_PHY_CLOCK_SELECT_162GBPS

#define XDP_TX_PHY_CLOCK_SELECT_162GBPS   0x1

#include <xdp_hw.h>

1.62 Gbps link.

◆ XDP_TX_PHY_CLOCK_SELECT_270GBPS

#define XDP_TX_PHY_CLOCK_SELECT_270GBPS   0x3

#include <xdp_hw.h>

2.70 Gbps link.

◆ XDP_TX_PHY_CLOCK_SELECT_540GBPS

#define XDP_TX_PHY_CLOCK_SELECT_540GBPS   0x5

#include <xdp_hw.h>

5.40 Gbps link.

◆ XDP_TX_PHY_CONFIG

#define XDP_TX_PHY_CONFIG   0x200

#include <xdp_hw.h>

Transceiver PHY reset and configuration.

◆ XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK

#define XDP_TX_PHY_CONFIG_GT_ALL_RESET_MASK   0x0000003

#include <xdp_hw.h>

Reset GT and PHY.

◆ XDP_TX_PHY_CONFIG_GTTX_RESET_MASK

#define XDP_TX_PHY_CONFIG_GTTX_RESET_MASK   0x0000002

#include <xdp_hw.h>

Hold GTTXRESET in reset.

◆ XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK

#define XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK   0x0000000

#include <xdp_hw.h>

Release reset.

◆ XDP_TX_PHY_CONFIG_PHY_RESET_MASK

#define XDP_TX_PHY_CONFIG_PHY_RESET_MASK   0x0000001

#include <xdp_hw.h>

Hold the PHY in reset.

◆ XDP_TX_PHY_CONFIG_TX_PHY_8B10BEN_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_8B10BEN_MASK   0x0200000

#include <xdp_hw.h>

8B10B encoding enable.

◆ XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK   0x000E000

#include <xdp_hw.h>

Set TX_PHY_LOOPBACK.

◆ XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT

#define XDP_TX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT   13

#include <xdp_hw.h>

Shift bits for TX_PHY_LOOPBACK.

◆ XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK   0x0000200

#include <xdp_hw.h>

Hold TX_PHY_PCS reset.

◆ XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK   0x0000100

#include <xdp_hw.h>

Hold TX_PHY_PMA reset.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK   0x0010000

#include <xdp_hw.h>

Set to enable individual lane polarity.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK   0x0020000

#include <xdp_hw.h>

Set TX_PHY_POLARITY for lane 0.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK   0x0040000

#include <xdp_hw.h>

Set TX_PHY_POLARITY for lane 1.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK   0x0080000

#include <xdp_hw.h>

Set TX_PHY_POLARITY for lane 2.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK   0x0100000

#include <xdp_hw.h>

Set TX_PHY_POLARITY for lane 3.

◆ XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_POLARITY_MASK   0x0000800

#include <xdp_hw.h>

Set TX_PHY_POLARITY.

◆ XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK

#define XDP_TX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK   0x0001000

#include <xdp_hw.h>

Set TX_PHY_PRBSFORCEERR.

◆ XDP_TX_PHY_POSTCURSOR_LANE_0

#define XDP_TX_PHY_POSTCURSOR_LANE_0   0x24C

#include <xdp_hw.h>

Controls the post-cursor level.

◆ XDP_TX_PHY_POSTCURSOR_LANE_1

#define XDP_TX_PHY_POSTCURSOR_LANE_1   0x250

#include <xdp_hw.h>

Controls the post-cursor level.

◆ XDP_TX_PHY_POSTCURSOR_LANE_2

#define XDP_TX_PHY_POSTCURSOR_LANE_2   0x254

#include <xdp_hw.h>

Controls the post-cursor level.

◆ XDP_TX_PHY_POSTCURSOR_LANE_3

#define XDP_TX_PHY_POSTCURSOR_LANE_3   0x258

#include <xdp_hw.h>

Controls the post-cursor level.

◆ XDP_TX_PHY_POWER_DOWN

#define XDP_TX_PHY_POWER_DOWN   0x238

#include <xdp_hw.h>

Controls PHY power down.

◆ XDP_TX_PHY_PRECURSOR_LANE_0

#define XDP_TX_PHY_PRECURSOR_LANE_0   0x23C

#include <xdp_hw.h>

Controls the pre-cursor level.

◆ XDP_TX_PHY_PRECURSOR_LANE_1

#define XDP_TX_PHY_PRECURSOR_LANE_1   0x240

#include <xdp_hw.h>

Controls the pre-cursor level.

◆ XDP_TX_PHY_PRECURSOR_LANE_2

#define XDP_TX_PHY_PRECURSOR_LANE_2   0x244

#include <xdp_hw.h>

Controls the pre-cursor level.

◆ XDP_TX_PHY_PRECURSOR_LANE_3

#define XDP_TX_PHY_PRECURSOR_LANE_3   0x248

#include <xdp_hw.h>

Controls the pre-cursor level.

◆ XDP_TX_PHY_STATUS

#define XDP_TX_PHY_STATUS   0x280

#include <xdp_hw.h>

Current PHY status.

◆ XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK

#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK

#include <xdp_hw.h>

Value:
XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK)
#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK
Reset done for lanes 2 and 3.
Definition: xdp_hw.h:971

Lanes 0-3 are ready.

◆ XDP_TX_PHY_STATUS_LANE_0_READY_MASK

#define XDP_TX_PHY_STATUS_LANE_0_READY_MASK

#include <xdp_hw.h>

Value:
XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK)
#define XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK
Reset done for lane 0.
Definition: xdp_hw.h:967

Lane 0 is ready.

◆ XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK

#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK

#include <xdp_hw.h>

Value:
XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK)
#define XDP_TX_PHY_STATUS_LANE_0_READY_MASK
Lane 0 is ready.
Definition: xdp_hw.h:1039

Lanes 0-1 are ready.

◆ XDP_TX_PHY_STATUS_LANES_READY_MASK

#define XDP_TX_PHY_STATUS_LANES_READY_MASK (   n)

#include <xdp_hw.h>

Value:
XDP_TX_PHY_STATUS_LANE_0_READY_MASK)
#define XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK
Lanes 0-3 are ready.
Definition: xdp_hw.h:1045
#define XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK
Lanes 0-1 are ready.
Definition: xdp_hw.h:1042

Macro for lanes ready mask with number of lanes as the argument.

◆ XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK

#define XDP_TX_PHY_STATUS_PLL_FABRIC_LOCK_MASK   0x00000040

#include <xdp_hw.h>

FPGA fabric clock PLL locked.

◆ XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK

#define XDP_TX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK   0x00000010

#include <xdp_hw.h>

PLL locked for lanes 0 and 1.

◆ XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK

#define XDP_TX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK   0x00000020

#include <xdp_hw.h>

PLL locked for lanes 2 and 3.

◆ XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK

#define XDP_TX_PHY_STATUS_RESET_LANE_0_DONE_MASK   0x00000001

#include <xdp_hw.h>

Reset done for lane 0.

◆ XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK

#define XDP_TX_PHY_STATUS_RESET_LANE_1_DONE_MASK   0x00000002

#include <xdp_hw.h>

Reset done for lane 1.

◆ XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK

#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK   0x0000000C

#include <xdp_hw.h>

Reset done for lanes 2 and 3.

◆ XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT

#define XDP_TX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT   2

#include <xdp_hw.h>

Shift bits for reset done for lanes 2 and 3.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK   0x00030000

#include <xdp_hw.h>

TX buffer status lane 0.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT   16

#include <xdp_hw.h>

Shift bits for TX buffer status lane 0.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK   0x00300000

#include <xdp_hw.h>

TX buffer status lane 1.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT   20

#include <xdp_hw.h>

Shift bits for TX buffer status lane 1.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK   0x03000000

#include <xdp_hw.h>

TX buffer status lane 2.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT   24

#include <xdp_hw.h>

Shift bits for TX buffer status lane 2.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK   0x30000000

#include <xdp_hw.h>

TX buffer status lane 3.

◆ XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT

#define XDP_TX_PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT   28

#include <xdp_hw.h>

Shift bits for TX buffer status lane 3.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_MASK   0x000C0000

#include <xdp_hw.h>

TX error on lane 0.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_0_SHIFT   18

#include <xdp_hw.h>

Shift bits for TX error on lane 0.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_MASK   0x00C00000

#include <xdp_hw.h>

TX error on lane 1.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_1_SHIFT   22

#include <xdp_hw.h>

Shift bits for TX error on lane 1.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_MASK   0x0C000000

#include <xdp_hw.h>

TX error on lane 2.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_2_SHIFT   26

#include <xdp_hw.h>

Shift bits for TX error on lane 2.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_MASK   0xC0000000

#include <xdp_hw.h>

TX error on lane 3.

◆ XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT

#define XDP_TX_PHY_STATUS_TX_ERROR_LANE_3_SHIFT   30

#include <xdp_hw.h>

Shift bits for TX error on lane 3.

◆ XDP_TX_PHY_TRANSMIT_PRBS7

#define XDP_TX_PHY_TRANSMIT_PRBS7   0x230

#include <xdp_hw.h>

Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.

◆ XDP_TX_PHY_VOLTAGE_DIFF_LANE_0

#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_0   0x220

#include <xdp_hw.h>

Controls the differential voltage swing.

◆ XDP_TX_PHY_VOLTAGE_DIFF_LANE_1

#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_1   0x224

#include <xdp_hw.h>

Controls the differential voltage swing.

◆ XDP_TX_PHY_VOLTAGE_DIFF_LANE_2

#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_2   0x228

#include <xdp_hw.h>

Controls the differential voltage swing.

◆ XDP_TX_PHY_VOLTAGE_DIFF_LANE_3

#define XDP_TX_PHY_VOLTAGE_DIFF_LANE_3   0x22C

#include <xdp_hw.h>

Controls the differential voltage swing.

◆ XDP_TX_REPLY_DATA_COUNT

#define XDP_TX_REPLY_DATA_COUNT   0x148

#include <xdp_hw.h>

Total number of data bytes actually received during a transaction.

◆ XDP_TX_REPLY_STATUS

#define XDP_TX_REPLY_STATUS   0x14C

#include <xdp_hw.h>

Reply status of most recent AUX transaction.

◆ XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK

#define XDP_TX_REPLY_STATUS_REPLY_ERROR_MASK   0x00000008

#include <xdp_hw.h>

Detected an error in the AUX reply of the most recent transaction.

◆ XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK

#define XDP_TX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK   0x00000002

#include <xdp_hw.h>

AUX reply is currently being received.

◆ XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK

#define XDP_TX_REPLY_STATUS_REPLY_RECEIVED_MASK   0x00000001

#include <xdp_hw.h>

AUX transaction is complete and a valid reply transaction received.

◆ XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK

#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_MASK   0x00000FF0

#include <xdp_hw.h>

Internal AUX reply state machine status bits.

◆ XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT

#define XDP_TX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT   4

#include <xdp_hw.h>

Shift bits for the internal AUX reply state machine status.

◆ XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK

#define XDP_TX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK   0x00000004

#include <xdp_hw.h>

AUX request is currently being transmitted.

◆ XDP_TX_SCRAMBLING_DISABLE

#define XDP_TX_SCRAMBLING_DISABLE   0x014

#include <xdp_hw.h>

Disable scrambler and transmit all symbols.

◆ XDP_TX_SOFT_RESET

#define XDP_TX_SOFT_RESET   0x01C

#include <xdp_hw.h>

Software reset.

◆ XDP_TX_SOFT_RESET_AUX_MASK

#define XDP_TX_SOFT_RESET_AUX_MASK   0x00000080

#include <xdp_hw.h>

Reset AUX logic.

◆ XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK

#define XDP_TX_SOFT_RESET_VIDEO_STREAM1_MASK   0x00000001

#include <xdp_hw.h>

Reset video logic.

◆ XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK

#define XDP_TX_SOFT_RESET_VIDEO_STREAM2_MASK   0x00000002

#include <xdp_hw.h>

Reset video logic.

◆ XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK

#define XDP_TX_SOFT_RESET_VIDEO_STREAM3_MASK   0x00000004

#include <xdp_hw.h>

Reset video logic.

◆ XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK

#define XDP_TX_SOFT_RESET_VIDEO_STREAM4_MASK   0x00000008

#include <xdp_hw.h>

Reset video logic.

◆ XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK

#define XDP_TX_SOFT_RESET_VIDEO_STREAM_ALL_MASK   0x0000000F

#include <xdp_hw.h>

Reset video logic for all streams.

◆ XDP_TX_STREAM1

#define XDP_TX_STREAM1   0x1D0

#include <xdp_hw.h>

Average stream symbol timeslots per MTP config.

◆ XDP_TX_STREAM1_MSA_START

#define XDP_TX_STREAM1_MSA_START   0x180

#include <xdp_hw.h>

Start of the MSA registers for stream 1.

◆ XDP_TX_STREAM2

#define XDP_TX_STREAM2   0x1D4

#include <xdp_hw.h>

Average stream symbol timeslots per MTP config.

◆ XDP_TX_STREAM2_MSA_START

#define XDP_TX_STREAM2_MSA_START   0x500

#include <xdp_hw.h>

Start of the MSA registers for stream 2.

◆ XDP_TX_STREAM2_MSA_START_OFFSET

#define XDP_TX_STREAM2_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_TX_STREAM1_MSA_START)
#define XDP_TX_STREAM2_MSA_START
Start of the MSA registers for stream 2.
Definition: xdp_hw.h:451

The MSA registers for stream 2 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().

◆ XDP_TX_STREAM3

#define XDP_TX_STREAM3   0x1D8

#include <xdp_hw.h>

Average stream symbol timeslots per MTP config.

◆ XDP_TX_STREAM3_MSA_START

#define XDP_TX_STREAM3_MSA_START   0x550

#include <xdp_hw.h>

Start of the MSA registers for stream 3.

◆ XDP_TX_STREAM3_MSA_START_OFFSET

#define XDP_TX_STREAM3_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_TX_STREAM1_MSA_START)
#define XDP_TX_STREAM3_MSA_START
Start of the MSA registers for stream 3.
Definition: xdp_hw.h:464

The MSA registers for stream 3 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().

◆ XDP_TX_STREAM4

#define XDP_TX_STREAM4   0x1DC

#include <xdp_hw.h>

Average stream symbol timeslots per MTP config.

◆ XDP_TX_STREAM4_MSA_START

#define XDP_TX_STREAM4_MSA_START   0x5A0

#include <xdp_hw.h>

Start of the MSA registers for stream 4.

◆ XDP_TX_STREAM4_MSA_START_OFFSET

#define XDP_TX_STREAM4_MSA_START_OFFSET

#include <xdp_hw.h>

Value:
XDP_TX_STREAM1_MSA_START)
#define XDP_TX_STREAM4_MSA_START
Start of the MSA registers for stream 4.
Definition: xdp_hw.h:477

The MSA registers for stream 4 are at an offset from the corresponding registers of stream 1.

Referenced by XDp_TxClearMsaValues(), and XDp_TxSetMsaValues().

◆ XDP_TX_TRAINING_PATTERN_SET

#define XDP_TX_TRAINING_PATTERN_SET   0x00C

#include <xdp_hw.h>

Set the link training pattern.

◆ XDP_TX_TRAINING_PATTERN_SET_OFF

#define XDP_TX_TRAINING_PATTERN_SET_OFF   0x0

#include <xdp_hw.h>

Training off.

◆ XDP_TX_TRAINING_PATTERN_SET_TP1

#define XDP_TX_TRAINING_PATTERN_SET_TP1   0x1

#include <xdp_hw.h>

Training pattern 1 used for clock recovery.

◆ XDP_TX_TRAINING_PATTERN_SET_TP2

#define XDP_TX_TRAINING_PATTERN_SET_TP2   0x2

#include <xdp_hw.h>

Training pattern 2 used for channel equalization.

◆ XDP_TX_TRAINING_PATTERN_SET_TP3

#define XDP_TX_TRAINING_PATTERN_SET_TP3   0x3

#include <xdp_hw.h>

Training pattern 3 used for channel equalization for cores with DP v1.2.

◆ XDP_TX_TU_SIZE

#define XDP_TX_TU_SIZE   0x1B0

#include <xdp_hw.h>

Size of a transfer unit in the framing logic.

◆ XDP_TX_USER_DATA_COUNT_PER_LANE

#define XDP_TX_USER_DATA_COUNT_PER_LANE   0x1BC

#include <xdp_hw.h>

Used to translate the number of pixels per line to the native internal 16-bit datapath.

◆ XDP_TX_USER_FIFO_OVERFLOW

#define XDP_TX_USER_FIFO_OVERFLOW   0x110

#include <xdp_hw.h>

Indicates an overflow in user FIFO.

◆ XDP_TX_USER_PIXEL_WIDTH

#define XDP_TX_USER_PIXEL_WIDTH   0x1B8

#include <xdp_hw.h>

Selects the width of the user data input port.

◆ XDP_TX_VC_PAYLOAD_BUFFER_ADDR

#define XDP_TX_VC_PAYLOAD_BUFFER_ADDR   0x800

#include <xdp_hw.h>

Virtual channel payload table (0xFF bytes).

◆ XDP_TX_VERSION

#define XDP_TX_VERSION   0x0F8

#include <xdp_hw.h>

Version and revision of the DisplayPort core.

◆ XDP_TX_VERSION_CORE_PATCH_MASK

#define XDP_TX_VERSION_CORE_PATCH_MASK   0x00000030

#include <xdp_hw.h>

Core patch details.

◆ XDP_TX_VERSION_CORE_PATCH_SHIFT

#define XDP_TX_VERSION_CORE_PATCH_SHIFT   8

#include <xdp_hw.h>

Shift bits for core patch details.

◆ XDP_TX_VERSION_CORE_VER_MJR_MASK

#define XDP_TX_VERSION_CORE_VER_MJR_MASK   0x0000F000

#include <xdp_hw.h>

Core major version.

◆ XDP_TX_VERSION_CORE_VER_MJR_SHIFT

#define XDP_TX_VERSION_CORE_VER_MJR_SHIFT   24

#include <xdp_hw.h>

Shift bits for core major version.

◆ XDP_TX_VERSION_CORE_VER_MNR_MASK

#define XDP_TX_VERSION_CORE_VER_MNR_MASK   0x00000F00

#include <xdp_hw.h>

Core minor version.

◆ XDP_TX_VERSION_CORE_VER_MNR_SHIFT

#define XDP_TX_VERSION_CORE_VER_MNR_SHIFT   16

#include <xdp_hw.h>

Shift bits for core minor version.

◆ XDP_TX_VERSION_CORE_VER_REV_MASK

#define XDP_TX_VERSION_CORE_VER_REV_MASK   0x000000C0

#include <xdp_hw.h>

Core version revision.

◆ XDP_TX_VERSION_CORE_VER_REV_SHIFT

#define XDP_TX_VERSION_CORE_VER_REV_SHIFT   12

#include <xdp_hw.h>

Shift bits for core version revision.

◆ XDP_TX_VERSION_INTER_REV_MASK

#define XDP_TX_VERSION_INTER_REV_MASK   0x0000000F

#include <xdp_hw.h>

Internal revision.

◆ XDP_TX_VS_LEVEL_0

#define XDP_TX_VS_LEVEL_0   0x2

#include <xdp_hw.h>

Voltage swing level 0.

◆ XDP_TX_VS_LEVEL_1

#define XDP_TX_VS_LEVEL_1   0x5

#include <xdp_hw.h>

Voltage swing level 1.

◆ XDP_TX_VS_LEVEL_2

#define XDP_TX_VS_LEVEL_2   0x8

#include <xdp_hw.h>

Voltage swing level 2.

◆ XDP_TX_VS_LEVEL_3

#define XDP_TX_VS_LEVEL_3   0xF

#include <xdp_hw.h>

Voltage swing level 3.

◆ XDP_TX_VS_LEVEL_OFFSET

#define XDP_TX_VS_LEVEL_OFFSET   0x4

#include <xdp_hw.h>

Voltage swing compensation offset used when there's no redriver in display path.

◆ XDp_TxCfgSetRGB

#define XDp_TxCfgSetRGB (   InstancePtr,
  Stream 
)

#include <xdp.h>

Value:
XDp_TxCfgSetColorEncode((InstancePtr), (Stream), \
XVIDC_CSF_RGB, XVIDC_BT_601, XDP_DR_VESA)
u32 XDp_TxCfgSetColorEncode(XDp *InstancePtr, u8 Stream, XVidC_ColorFormat Format, XVidC_ColorStd ColorCoeffs, XDp_DynamicRange Range)
This function will set the color encoding scheme for a given stream.
Definition: xdp_spm.c:574

The following functions set the color encoding scheme for a given stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to configure the color encoding scheme for.
Returns
XST_SUCCESS.
Note
C-style signatures: u32 XDp_TxCfgSetRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetSRGB(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYonly(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetYCbCr444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc422Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt601(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetXvYcc444Bt709(XDp *InstancePtr, u8 Stream) u32 XDp_TxCfgSetAdbRGB(XDp *InstancePtr, u8 Stream)

◆ XDp_TxGetDispIdTdtHLoc

#define XDp_TxGetDispIdTdtHLoc (   Tdt)

#include <xdp_hw.h>

Value:
((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HLOC_H_MASK) \
>> XDP_TX_DISPID_TDT_TOP2_HLOC_H_SHIFT) << 4) | \
((Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_HLOC_L_MASK) >> \
XDP_TX_DISPID_TDT_TOP1_HLOC_L_SHIFT))

Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled display.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The horizontal tile location in the tiled display represented by the specified TDT.
Note
C-style signature: u8 XDp_TxGetDispIdTdtHLoc(u8 *Tdt)

◆ XDp_TxGetDispIdTdtHTotal

#define XDp_TxGetDispIdTdtHTotal (   Tdt)

#include <xdp_hw.h>

Value:
(((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_HTOT_H_MASK) \
>> XDP_TX_DISPID_TDT_TOP2_HTOT_H_SHIFT) << 4) | \
((Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_HTOT_L_MASK) >> \
XDP_TX_DISPID_TDT_TOP0_HTOT_L_SHIFT)) + 1)

Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the tiled display.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The total number of horizontal tiles in the tiled display.
Note
C-style signature: u8 XDp_TxGetDispIdTdtHTotal(u8 *Tdt)

◆ XDp_TxGetDispIdTdtNumTiles

#define XDp_TxGetDispIdTdtNumTiles (   Tdt)    (XDp_TxGetDispIdTdtHTotal(Tdt) * XDp_TxGetDispIdTdtVTotal(Tdt))

#include <xdp_hw.h>

Given a Tiled Display Topology (TDT) data block, retrieve the total number of tiles in the tiled display.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The total number of tiles in the tiled display.
Note
C-style signature: u8 XDp_TxGetDispIdTdtNumTiles(u8 *Tdt)

◆ XDp_TxGetDispIdTdtTileOrder

#define XDp_TxGetDispIdTdtTileOrder (   Tdt)

#include <xdp_hw.h>

Value:
#define XDp_TxGetDispIdTdtVLoc(Tdt)
Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled dis...
Definition: xdp_hw.h:3682
#define XDp_TxGetDispIdTdtHLoc(Tdt)
Given a Tiled Display Topology (TDT) data block, retrieve the horizontal tile location in the tiled d...
Definition: xdp_hw.h:3661
#define XDp_TxGetDispIdTdtHTotal(Tdt)
Given a Tiled Display Topology (TDT) data block, retrieve the total number of horizontal tiles in the...
Definition: xdp_hw.h:3621

Given a Tiled Display Topology (TDT) data block, calculate the tiling order of the associated tile.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID. The tiling order starts at 0 for x,y coordinate 0,0 and increments as the horizontal location increases. Once the last horizontal tile has been reached, the next tile in the order is 0,y+1.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The total number of horizontal tiles in the tiled display.
Note
C-style signature: u8 XDp_TxGetDispIdTdtTileOrder(u8 *Tdt)

◆ XDp_TxGetDispIdTdtVLoc

#define XDp_TxGetDispIdTdtVLoc (   Tdt)

#include <xdp_hw.h>

Value:
(((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VLOC_H_MASK) << \
4) | (Tdt[XDP_TX_DISPID_TDT_TOP1] & XDP_TX_DISPID_TDT_TOP1_VLOC_L_MASK))

Given a Tiled Display Topology (TDT) data block, retrieve the vertical tile location in the tiled display.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The vertical tile location in the tiled display represented by the specified TDT.
Note
C-style signature: u8 XDp_TxGetDispIdTdtVLoc(u8 *Tdt)

◆ XDp_TxGetDispIdTdtVTotal

#define XDp_TxGetDispIdTdtVTotal (   Tdt)

#include <xdp_hw.h>

Value:
(((((Tdt[XDP_TX_DISPID_TDT_TOP2] & XDP_TX_DISPID_TDT_TOP2_VTOT_H_MASK) \
>> XDP_TX_DISPID_TDT_TOP2_VTOT_H_SHIFT) << 4) | \
(Tdt[XDP_TX_DISPID_TDT_TOP0] & XDP_TX_DISPID_TDT_TOP0_VTOT_L_MASK)) + 1)

Given a Tiled Display Topology (TDT) data block, retrieve the total number of vertical tiles in the tiled display.

The TDT block is part of an Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
Tdtis a pointer to the TDT data block.
Returns
The total number of vertical tiles in the tiled display.
Note
C-style signature: u8 XDp_TxGetDispIdTdtVTotal(u8 *Tdt)

◆ XDp_TxIsEdidExtBlockDispId

#define XDp_TxIsEdidExtBlockDispId (   Ext)    (Ext[XDP_EDID_EXT_BLOCK_TAG] == XDP_EDID_EXT_BLOCK_TAG_DISPID)

#include <xdp_hw.h>

Check if an Extended Display Identification Data (EDID) extension block is of type DisplayID.

Parameters
Extis a pointer to the EDID extension block under comparison.
Returns
  • 1 if the extension block is of type DisplayID.
  • Otherwise.
Note
C-style signature: u8 XDp_TxIsEdidExtBlockDispId(u8 *Ext)

◆ XDp_WriteReg

#define XDp_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    XDp_Out32((BaseAddress) + (RegOffset), (Data))

#include <xdp_hw.h>

This is a low-level function that writes to the specified register.

Parameters
BaseAddressis the base address of the device.
RegOffsetis the register offset to write to.
Datais the 32-bit data to write to the specified register.
Returns
None.
Note
C-style signature: void XDp_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)

Referenced by XDp_RxAllocatePayloadStream().

Typedef Documentation

◆ XDp_IntrHandler

typedef void(* XDp_IntrHandler) (void *InstancePtr)

#include <xdp.h>

Callback type which represents the handler for interrupts.

Parameters
InstancePtris a pointer to the XDp instance.
Note
None.

◆ XDp_TimerHandler

typedef void(* XDp_TimerHandler) (void *InstancePtr, u32 MicroSeconds)

#include <xdp.h>

Callback type which represents a custom timer wait handler.

This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.

Parameters
InstancePtris a pointer to the XDp instance.
MicroSecondsis the number of microseconds to be passed to the timer function.
Note
None.

Enumeration Type Documentation

◆ XDp_CoreType

#include <xdp.h>

This typedef enumerates the RX and TX modes of operation for the DisplayPort core.

◆ XDp_DynamicRange

#include <xdp.h>

This typedef enumerates the dynamic ranges available to the DisplayPort core.

◆ XDp_TxTrainingState

#include <xdp.c>

This typedef enumerates the list of training states used in the state machine during the link training process.

Function Documentation

◆ XDp_CfgInitialize()

void XDp_CfgInitialize ( XDp InstancePtr,
XDp_Config ConfigPtr,
UINTPTR  EffectiveAddr 
)

#include <xdp.c>

This function retrieves the configuration for this DisplayPort instance and fills in the InstancePtr->Config structure.

Parameters
InstancePtris a pointer to the XDp instance.
ConfigPtris a pointer to the configuration structure that will be used to copy the settings from.
EffectiveAddris the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.
Returns
None.
Note
Unexpected errors may occur if the address mapping is changed after this function is invoked.

References XDp_Config::BaseAddr, XDp::Config, and XDp_GetCoreType.

Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().

◆ XDp_Initialize()

u32 XDp_Initialize ( XDp InstancePtr)

#include <xdp.c>

This function prepares the DisplayPort core for use depending on whether the core is operating in TX or RX mode.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the DisplayPort core was successfully initialized.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

Referenced by Dptx_SetupExample().

◆ XDp_InterruptHandler()

void XDp_InterruptHandler ( XDp InstancePtr)

#include <xdp.h>

This function is the interrupt handler for the XDp driver.

When an interrupt happens, this interrupt handler will check which TX/RX mode of operation the core is running in, and will call the appropriate interrupt handler. The called interrupt handler will first detect what kind of interrupt happened, then decides which callback function to invoke.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_IsLaneCountValid()

u8 XDp_IsLaneCountValid ( XDp InstancePtr,
u8  LaneCount 
)

#include <xdp.c>

This function checks the validity of the lane count.

Parameters
InstancePtris a pointer to the XDp instance.
LaneCountis the number of lanes to check if valid.
Returns
  • 1 if specified lane count is valid.
  • 0 otherwise, if the lane count specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.
Note
None.

References XDp::Config, XDp_Config::MaxLaneCount, XDP_TX_LANE_COUNT_SET_1, XDP_TX_LANE_COUNT_SET_2, and XDP_TX_LANE_COUNT_SET_4.

◆ XDp_IsLinkRateValid()

u8 XDp_IsLinkRateValid ( XDp InstancePtr,
u8  LinkRate 
)

#include <xdp.c>

This function checks the validity of the link rate.

Parameters
InstancePtris a pointer to the XDp instance.
LinkRateis the link rate to check if valid.
Returns
  • 1 if specified link rate is valid.
  • 0 otherwise, if the link rate specified isn't valid as per spec, or if it exceeds the capabilities of the TX core.
Note
None.

References XDp::Config, XDp_Config::MaxLinkRate, XDP_TX_LINK_BW_SET_162GBPS, XDP_TX_LINK_BW_SET_270GBPS, and XDP_TX_LINK_BW_SET_540GBPS.

◆ XDp_LookupConfig()

XDp_Config * XDp_LookupConfig ( u16  DeviceId)

#include <xdp.h>

This function looks for the device configuration based on the unique device ID.

The table XDp_ConfigTable[] contains the configuration information for each device in the system.

Parameters
DeviceIdis the unique device ID of the device being looked up.
Returns
A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.
Note
None.

Referenced by Dp_SelfTestExample(), and Dptx_SetupExample().

◆ XDp_RxAllocatePayloadStream()

void XDp_RxAllocatePayloadStream ( XDp InstancePtr)

#include <xdp.h>

This function will set the virtual channel payload table both in software and in the DisplayPort RX core's hardware registers based on the MST allocation values from ALLOCATE_PAYLOAD and CLEAR_PAYLOAD sideband message requests.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp_Config::BaseAddr, XDp::Config, XDp_RxTopology::PayloadTable, XDp_Rx::Topology, XDp_ReadReg, XDP_RX_MST_ALLOC, XDP_RX_MST_ALLOC_COUNT_TS_MASK, XDP_RX_MST_ALLOC_COUNT_TS_SHIFT, XDP_RX_MST_ALLOC_START_TS_MASK, XDP_RX_MST_ALLOC_START_TS_SHIFT, XDP_RX_MST_ALLOC_VCP_ID_MASK, XDP_RX_MST_CAP, XDP_RX_MST_CAP_VCP_UPDATE_MASK, XDP_RX_VC_PAYLOAD_TABLE, and XDp_WriteReg.

◆ XDp_RxAudioDis()

void XDp_RxAudioDis ( XDp InstancePtr)

#include <xdp.c>

This function disables audio stream packets on the main link.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxAudioEn()

void XDp_RxAudioEn ( XDp InstancePtr)

#include <xdp.c>

This function enables audio stream packets on the main link.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxAudioReset()

void XDp_RxAudioReset ( XDp InstancePtr)

#include <xdp.c>

This function resets the RX core's reception of audio stream packets on the main link.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxCheckLinkStatus()

u32 XDp_RxCheckLinkStatus ( XDp InstancePtr)

#include <xdp.c>

This function checks if the receiver's internal registers indicate that link training has complete.

That is, training has achieved channel equalization, symbol lock, and interlane alignment for all lanes currently in use.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the RX device has achieved clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxDtgDis()

void XDp_RxDtgDis ( XDp InstancePtr)

#include <xdp.c>

This function disables the display timing generator (DTG).

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxDtgEn()

void XDp_RxDtgEn ( XDp InstancePtr)

#include <xdp.c>

This function enables the display timing generator (DTG).

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxGenerateHpdInterrupt()

void XDp_RxGenerateHpdInterrupt ( XDp InstancePtr,
u16  DurationUs 
)

#include <xdp.h>

This function generates a pulse on the hot-plug-detect (HPD) line of the specified duration.

Parameters
InstancePtris a pointer to the XDp instance.
DurationUsis the duration of the HPD pulse, in microseconds.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxGetBpc()

XVidC_ColorDepth XDp_RxGetBpc ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function extracts the bits per color from MISC0 of the stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number to make the calculations for.
Returns
The bits per color for the stream.
Note
RX clock must be stable.

References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.

◆ XDp_RxGetColorComponent()

XVidC_ColorFormat XDp_RxGetColorComponent ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function extracts the color component format from MISC0 of the stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number to make the calculations for.
Returns
The color component for the stream.
Note
RX clock must be stable.

References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.

◆ XDp_RxGetIicMapEntry()

XDp_RxIicMapEntry * XDp_RxGetIicMapEntry ( XDp InstancePtr,
u8  PortNum,
u8  IicAddress 
)

#include <xdp.h>

This function returns a pointer to the I2C map entry at the supplied I2C address for the specified port.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number for which to obtain the I2C map entry for.
IicAddressis the I2C address of the map entry.
Returns
  • NULL if no entry exists in the I2C map corresponding to the supplied I2C address for the given port.
  • Otherwise, a pointer to the I2C map entry with the specified I2C address.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxHandleDownReq()

u32 XDp_RxHandleDownReq ( XDp InstancePtr)

#include <xdp.h>

This function will handle incoming sideband messages.

It will 1) Read the contents of the down request registers, 2) Delegate control depending on the request type, and 3) Send a down reply.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the entire message was sent successfully.
  • XST_DEVICE_NOT_FOUND if no device is connected.
  • XST_ERROR_COUNT_MAX if sending one of the message fragments timed out.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxInterruptDisable()

void XDp_RxInterruptDisable ( XDp InstancePtr,
u32  Mask 
)

#include <xdp.h>

This function disables interrupts associated with the specified mask.

Parameters
InstancePtris a pointer to the XDp instance.
Maskspecifies which interrupts should be disabled. Bits set to 1 will disable the corresponding interrupts.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxInterruptEnable()

void XDp_RxInterruptEnable ( XDp InstancePtr,
u32  Mask 
)

#include <xdp.h>

This function enables interrupts associated with the specified mask.

Parameters
InstancePtris a pointer to the XDp instance.
Maskspecifies which interrupts should be enabled. Bits set to 1 will enable the corresponding interrupts.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxMstExposePort()

void XDp_RxMstExposePort ( XDp InstancePtr,
u8  PortNum,
u8  Expose 
)

#include <xdp.h>

This function allows the user to select which ports will be exposed when replying to a LINK_ADDRESS sideband message.

The number of ports will also be set. When an upstream device sends a LINK_ADDRESS sideband message, the RX will respond by forming a reply message containing port information for directly connected ports. If exposed, this information will be provided in the LINK_ADDRESS reply. Otherwise, the LINK_ADDRESS reply will not contain this information, hiding the port from the TX.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number to enable or disable exposure.
Exposewill expose the port at the specified PortNum as part of the LINK_ADDRESS reply when set to 1. Hidden otherwise.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxMstSetInputPort()

void XDp_RxMstSetInputPort ( XDp InstancePtr,
u8  PortNum,
XDp_SbMsgLinkAddressReplyPortDetail PortOverride 
)

#include <xdp.h>

This function, for an input port, sets the port information that is contained in the driver instance structure for the specified port number.

Some default values will be used if no port structure is supplied.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number to set the input port for.
PortOverrideis a pointer to the user-defined port structure, whose information is to be copied into the driver instance. If set to NULL, default values for the input port will be used.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxMstSetPbn()

void XDp_RxMstSetPbn ( XDp InstancePtr,
u8  PortNum,
u16  PbnVal 
)

#include <xdp.h>

This function will set the available payload bandwidth number (PBN) of the specified port that is available for allocation, and the full PBN that the port is capable of using.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number to set the PBN values for.
PbnValis the value to set the port's available and full PBN to.
Returns
None.
Note
The available PBN is set to 100% of the full PBN.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxMstSetPort()

void XDp_RxMstSetPort ( XDp InstancePtr,
u8  PortNum,
XDp_SbMsgLinkAddressReplyPortDetail PortDetails 
)

#include <xdp.h>

This function sets the port information that is contained in the driver instance structure for the specified port number, to be copied from the supplied port details structure.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number to set the port details for.
PortDetailsis a pointer to the user-defined port structure, whose information is to be copied into the driver instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxSetDpcdMap()

void XDp_RxSetDpcdMap ( XDp InstancePtr,
u8  PortNum,
u32  StartAddr,
u32  NumBytes,
u8 *  DpcdMap 
)

#include <xdp.h>

This function specified the DPCD address space for a given port.

The user provides a pointer to the data to be used. When an upstream device issues a REMOTE_DPCD_READ sideband message, the contents of this DPCD structure will be used as the reply's data.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number for which to set the DPCD.
StartAddris the starting address for which to define the DPCD.
NumBytesis the total number of bytes defined by the DPCD.
DpcdMapis a pointer to a user-defined data structure that will be used as read data when an upstream device issues a DPCD read.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxSetDrvIntrNoVideoHandler()

void XDp_RxSetDrvIntrNoVideoHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs driver callback function for when a no video interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetDrvIntrPowerStateHandler()

void XDp_RxSetDrvIntrPowerStateHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a driver callback function for when the power state interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetDrvIntrVideoHandler()

void XDp_RxSetDrvIntrVideoHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a driver callback function for when a valid video interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIicMapEntry()

u32 XDp_RxSetIicMapEntry ( XDp InstancePtr,
u8  PortNum,
u8  IicAddress,
u8  ReadNumBytes,
u8 *  ReadData 
)

#include <xdp.h>

This function adds an entry into the I2C map for a given port.

The user provides a pointer to the data to be used for the specified I2C address. When an upstream device issues a REMOTE_I2C_READ sideband message, this I2C map will be searched for an entry matching the requested I2C address read.

Parameters
InstancePtris a pointer to the XDp instance.
PortNumis the port number for which to set the I2C map entry.
IicAddressis the I2C address for which to set the data.
ReadNumBytesis number of bytes available for reading from the associated IicAddress.
ReadDatais a pointer to a user-defined data structure that will be used as read data when an upstream device issues an I2C read.
Returns
  • XST_SUCCESS if there is an available slot in the I2C map for a new entry and the I2C address isn't taken.
  • XST_FAILURE, otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxSetIntrActRxHandler()

void XDp_RxSetIntrActRxHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when an ACT received interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrAudioOverHandler()

void XDp_RxSetIntrAudioOverHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when an audio packet overflow interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrBwChangeHandler()

void XDp_RxSetIntrBwChangeHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a bandwidth change interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrCrcTestHandler()

void XDp_RxSetIntrCrcTestHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a CRC test start interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrDownReplyHandler()

void XDp_RxSetIntrDownReplyHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a down reply interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrDownReqHandler()

void XDp_RxSetIntrDownReqHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a down request interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrExtPktHandler()

void XDp_RxSetIntrExtPktHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when an audio extension packet interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpAinfoWriteHandler()

void XDp_RxSetIntrHdcpAinfoWriteHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a write to the hdcp Ainfo MSB register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpAksvWriteHandler()

void XDp_RxSetIntrHdcpAksvWriteHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a write to the hdcp Aksv MSB register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpAnWriteHandler()

void XDp_RxSetIntrHdcpAnWriteHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a write to the hdcp An MSB register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpBinfoReadHandler()

void XDp_RxSetIntrHdcpBinfoReadHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a read of the hdcp Binfo register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpDebugWriteHandler()

void XDp_RxSetIntrHdcpDebugWriteHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a write to any hdcp debug register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrHdcpRoReadHandler()

void XDp_RxSetIntrHdcpRoReadHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a read of the hdcp Ro/Ri MSB register occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrInfoPktHandler()

void XDp_RxSetIntrInfoPktHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when an audio info packet interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrNoVideoHandler()

void XDp_RxSetIntrNoVideoHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a no video interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrPayloadAllocHandler()

void XDp_RxSetIntrPayloadAllocHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when the RX's DPCD payload allocation registers have been written for allocation, de-allocation, or partial deletion.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrPowerStateHandler()

void XDp_RxSetIntrPowerStateHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when the power state interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrTp1Handler()

void XDp_RxSetIntrTp1Handler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a training pattern 1 interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrTp2Handler()

void XDp_RxSetIntrTp2Handler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a training pattern 2 interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrTp3Handler()

void XDp_RxSetIntrTp3Handler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a training pattern 3 interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrTrainingDoneHandler()

void XDp_RxSetIntrTrainingDoneHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a training done interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrTrainingLostHandler()

void XDp_RxSetIntrTrainingLostHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a training lost interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrUnplugHandler()

void XDp_RxSetIntrUnplugHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when an unplug event interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrVBlankHandler()

void XDp_RxSetIntrVBlankHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a vertical blanking interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrVideoHandler()

void XDp_RxSetIntrVideoHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a valid video interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetIntrVmChangeHandler()

void XDp_RxSetIntrVmChangeHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a video mode change interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_RxSetLaneCount()

void XDp_RxSetLaneCount ( XDp InstancePtr,
u8  LaneCount 
)

#include <xdp.c>

This function sets the maximum lane count to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.

Parameters
InstancePtris a pointer to the XDp instance.
LaneCountis the number of lanes to be used over the main link.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxSetLineReset()

void XDp_RxSetLineReset ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

Disable/enables the end of line reset to the internal video pipe in case of reduced blanking as required.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number to make the calculations for.
Returns
None.
Note
RX clock must be stable.

References XDp::IsReady, XDp_GetCoreType, XDP_RX_STREAM2_MSA_START_OFFSET, XDP_RX_STREAM3_MSA_START_OFFSET, and XDP_RX_STREAM4_MSA_START_OFFSET.

◆ XDp_RxSetLinkRate()

void XDp_RxSetLinkRate ( XDp InstancePtr,
u8  LinkRate 
)

#include <xdp.c>

This function sets the maximum data rate to be exposed in the RX device's DisplayPort Configuration Data (DPCD) registers.

Parameters
InstancePtris a pointer to the XDp instance.
LinkRateis the link rate to be used over the main link based on one of the following selects:
  • XDP_RX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
  • XDP_RX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
  • XDP_RX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_RxSetUserPixelWidth()

void XDp_RxSetUserPixelWidth ( XDp InstancePtr,
u8  UserPixelWidth 
)

#include <xdp.h>

This function configures the number of pixels output through the user data interface.

Parameters
InstancePtris a pointer to the XDp instance.
UserPixelWidthis the user pixel width to be configured.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_SelfTest()

u32 XDp_SelfTest ( XDp InstancePtr)

#include <xdp.h>

This function runs a self-test on the XDp driver/device depending on whether the core is operating in TX or RX mode.

The sanity test checks whether or not all tested registers hold their default reset values.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

Referenced by Dp_SelfTestExample().

◆ XDp_SetUserTimerHandler()

void XDp_SetUserTimerHandler ( XDp InstancePtr,
XDp_TimerHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.c>

This function installs a custom delay/sleep function to be used by the XDp driver.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.
Returns
None.
Note
None.

References XDp::UserTimerPtr, and XDp::UserTimerWaitUs.

◆ XDp_TxAllocatePayloadStreams()

u32 XDp_TxAllocatePayloadStreams ( XDp InstancePtr)

#include <xdp.h>

This function will allocate bandwidth for all enabled stream.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the payload ID tables were successfully updated with the new allocation.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, waiting for the payload ID table to be cleared or updated, or an AUX request timed out.
  • XST_BUFFER_TOO_SMALL if there is not enough free timeslots in the payload ID table for the requested Ts.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of a sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxAllocatePayloadVcIdTable()

u32 XDp_TxAllocatePayloadVcIdTable ( XDp InstancePtr,
u8  VcId,
u8  Ts,
u8  StartTs 
)

#include <xdp.h>

This function will allocate a bandwidth for a virtual channel in the payload ID table in both the DisplayPort TX and the downstream DisplayPort devices on the path to the target device specified by LinkCountTotal and RelativeAddress.

Parameters
InstancePtris a pointer to the XDp instance.
VcIdis the unique virtual channel ID to allocate into the payload ID tables.
Tsis the number of timeslots to allocate in the payload ID tables.
StartTsis the starting time slot to allocate the VcId to.
Returns
  • XST_SUCCESS if the payload ID tables were successfully updated with the new allocation.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_BUFFER_TOO_SMALL if there is not enough free timeslots in the payload ID table for the requested Ts.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of a sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxAuxRead()

u32 XDp_TxAuxRead ( XDp InstancePtr,
u32  DpcdAddress,
u32  BytesToRead,
void *  ReadData 
)

#include <xdp.c>

This function issues a read request over the AUX channel that will read from the RX device's DisplayPort Configuration Data (DPCD) address space.

The read message will be divided into multiple transactions which read a maximum of 16 bytes each.

Parameters
InstancePtris a pointer to the XDp instance.
DpcdAddressis the starting address to read from the RX device.
BytesToReadis the number of bytes to read from the RX device.
ReadDatais a pointer to the data buffer that will be filled with read data.
Returns
  • XST_SUCCESS if the AUX read request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxAuxWrite()

u32 XDp_TxAuxWrite ( XDp InstancePtr,
u32  DpcdAddress,
u32  BytesToWrite,
void *  WriteData 
)

#include <xdp.c>

This function issues a write request over the AUX channel that will write to the RX device's DisplayPort Configuration Data (DPCD) address space.

The write message will be divided into multiple transactions which write a maximum of 16 bytes each.

Parameters
InstancePtris a pointer to the XDp instance.
DpcdAddressis the starting address to write to the RX device.
BytesToWriteis the number of bytes to write to the RX device.
WriteDatais a pointer to the data buffer that contains the data to be written to the RX device.
Returns
  • XST_SUCCESS if the AUX write request was successfully acknowledged.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxCfgMainLinkMax()

u32 XDp_TxCfgMainLinkMax ( XDp InstancePtr)

#include <xdp.c>

This function determines the common capabilities between the DisplayPort TX core and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if main link settings were successfully set.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, XDp_Tx::LinkConfig, and XDp_GetCoreType.

◆ XDp_TxCfgMsaEnSynchClkMode()

void XDp_TxCfgMsaEnSynchClkMode ( XDp InstancePtr,
u8  Stream,
u8  Enable 
)

#include <xdp.h>

This function enables or disables synchronous clock mode for a video stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to enable or disable synchronous clock mode.
Enableif set to 1, will enable synchronous clock mode. Otherwise, if set to 0, synchronous clock mode will be disabled.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxCfgMsaRecalculate()

void XDp_TxCfgMsaRecalculate ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function calculates the following Main Stream Attributes (MSA):

  • Transfer unit size
  • User pixel width
  • Horizontal start
  • Vertical start
  • Horizontal total clock
  • Vertical total clock
  • Misc0
  • Misc1
  • Data per lane
  • Average number of bytes per transfer unit
  • Number of initial wait cycles These values are derived from:
  • Bits per color
  • Horizontal resolution
  • Vertical resolution
  • Pixel clock (in KHz)
  • Horizontal sync polarity
  • Vertical sync polarity
  • Horizontal front porch
  • Horizontal sync pulse width
  • Horizontal back porch
  • Vertical front porch
  • Vertical sync pulse width
  • Vertical back porch
Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to calculate the MSA values.
Returns
None.
Note
The MsaConfig structure is modified with the new, calculated values. The main stream attributes that were used to derive the calculated values are untouched in the MsaConfig structure.

References XDp_GetCoreType.

◆ XDp_TxCfgMsaSetBpc()

void XDp_TxCfgMsaSetBpc ( XDp InstancePtr,
u8  Stream,
u8  BitsPerColor 
)

#include <xdp.h>

This function sets the bits per color value of the video stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to set the color depth.
BitsPerColoris the new number of bits per color to use.
Returns
None.
Note
The InstancePtr->TxInstance.MsaConfig structure is modified to reflect the new main stream attributes associated with a new bits per color value.

References XDp_GetCoreType.

◆ XDp_TxCfgMsaUseCustom()

void XDp_TxCfgMsaUseCustom ( XDp InstancePtr,
u8  Stream,
XDp_TxMainStreamAttributes MsaConfigCustom,
u8  Recalculate 
)

#include <xdp.h>

This function takes a the main stream attributes from MsaConfigCustom and copies them into InstancePtr->TxInstance.MsaConfig.

If desired, given a base set of attributes, the rest of the attributes may be derived. The minimal required main stream attributes (MSA) that must be contained in the MsaConfigCustom structure are:

  • Pixel clock (in Hz)
  • Frame rate
  • Horizontal active resolution
  • Horizontal front porch
  • Horizontal sync pulse width
  • Horizontal back porch
  • Horizontal total
  • Horizontal sync polarity
  • Vertical active resolution
  • Vertical back porch
  • Vertical sync pulse width
  • Vertical front porch
  • Vertical total
  • Vertical sync polarity
Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which the MSA values will be used for.
MsaConfigCustomis the structure that will be used to copy the main stream attributes from (into InstancePtr->TxInstance.MsaConfig).
Recalculateis a boolean enable that determines whether or not the main stream attributes should be recalculated.
Returns
None.
Note
The InstancePtr->TxInstance.MsaConfig structure is modified with the new values.

References XDp_GetCoreType.

◆ XDp_TxCfgMsaUseEdidPreferredTiming()

void XDp_TxCfgMsaUseEdidPreferredTiming ( XDp InstancePtr,
u8  Stream,
u8 *  Edid 
)

#include <xdp.h>

This function sets the main stream attribute values in the configuration structure to match the preferred timing of the sink monitor.

This Preferred Timing Mode (PTM) information is stored in the sink's Extended Display Identification Data (EDID).

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which the MSA values will be used for.
Edidis a pointer to the Edid to use for the specified stream.
Returns
None.
Note
The InstancePtr->TxInstance.MsaConfig structure is modified to reflect the main stream attribute values associated to the preferred timing of the sink monitor.

References XDp_GetCoreType.

◆ XDp_TxCfgMsaUseStandardVideoMode()

void XDp_TxCfgMsaUseStandardVideoMode ( XDp InstancePtr,
u8  Stream,
XVidC_VideoMode  VideoMode 
)

#include <xdp.h>

This function sets the Main Stream Attribute (MSA) values in the configuration structure to match one of the standard display mode timings from the XDp_TxDmtModes[] standard Display Monitor Timing (DMT) table.

The XDp_TxVideoMode enumeration in xvidc.h lists the available video modes.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which the MSA values will be used for.
VideoModeis one of the enumerated standard video modes that is used to determine the MSA values to be used.
Returns
None.
Note
The InstancePtr->TxInstance.MsaConfig structure is modified to reflect the MSA values associated to the specified video mode.

References XDp_GetCoreType.

◆ XDp_TxCfgSetColorEncode()

u32 XDp_TxCfgSetColorEncode ( XDp InstancePtr,
u8  Stream,
XVidC_ColorFormat  Format,
XVidC_ColorStd  ColorCoeffs,
XDp_DynamicRange  Range 
)

#include <xdp.h>

This function will set the color encoding scheme for a given stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to configure the color encoding scheme for.
Formatis the color space format.
ColorCoeffsis the color space conversion standard to use which will determine which color coefficients to use.
Rangeis the dynamic range to use (CEA or VESA).
Returns
None.
Note
The InstancePtr->TxInstance.MsaConfig structure is modified to reflect the new color encoding scheme. This values are used for MISC0 and MISC1.

References XDp_GetCoreType.

◆ XDp_TxCfgTxPeLevel()

void XDp_TxCfgTxPeLevel ( XDp InstancePtr,
u8  Level,
u8  TxLevel 
)

#include <xdp.c>

This function sets the pre-emphasis level value in the DisplayPort TX that will be used during link training for a given pre-emphasis training level.

Parameters
InstancePtris a pointer to the XDp instance.
Levelis the pre-emphasis training level to set the DisplayPort TX level for.
TxLevelis the DisplayPort TX pre-emphasis level value to be used during link training.
Returns
None.
Note
There are 32 possible pre-emphasis levels in the DisplayPort TX core that map to 4 possible pre-emphasis training levels in the RX device.

References XDp_GetCoreType.

◆ XDp_TxCfgTxVsLevel()

void XDp_TxCfgTxVsLevel ( XDp InstancePtr,
u8  Level,
u8  TxLevel 
)

#include <xdp.c>

This function sets the voltage swing level value in the DisplayPort TX that will be used during link training for a given voltage swing training level.

Parameters
InstancePtris a pointer to the XDp instance.
Levelis the voltage swing training level to set the DisplayPort TX level for.
TxLevelis the DisplayPort TX voltage swing level value to be used during link training.
Returns
None.
Note
There are 16 possible voltage swing levels in the DisplayPort TX core that map to 4 possible voltage swing training levels in the RX device.

References XDp_GetCoreType.

◆ XDp_TxCfgTxVsOffset()

void XDp_TxCfgTxVsOffset ( XDp InstancePtr,
u8  Offset 
)

#include <xdp.c>

This function sets the voltage swing offset to use during training when no redriver exists.

The offset will be added to the DisplayPort TX's voltage swing level value when pre-emphasis is used (when the pre-emphasis level not equal to 0).

Parameters
InstancePtris a pointer to the XDp instance.
Offsetis the value to set for the voltage swing offset.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxCheckLinkStatus()

u32 XDp_TxCheckLinkStatus ( XDp InstancePtr,
u8  LaneCount 
)

#include <xdp.c>

This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates the receiver has achieved and maintained clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.

Parameters
InstancePtris a pointer to the XDp instance.
LaneCountis the number of lanes to check.
Returns
  • XST_SUCCESS if the RX device has maintained clock recovery, channel equalization, symbol lock, and interlane alignment.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxClearMsaValues()

void XDp_TxClearMsaValues ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function clears the main stream attributes registers of the DisplayPort TX core.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to clear the MSA values.
Returns
None.
Note
None.

References XDp::IsReady, XDp_GetCoreType, XDP_TX_STREAM2_MSA_START_OFFSET, XDP_TX_STREAM3_MSA_START_OFFSET, and XDP_TX_STREAM4_MSA_START_OFFSET.

◆ XDp_TxClearPayloadVcIdTable()

u32 XDp_TxClearPayloadVcIdTable ( XDp InstancePtr)

#include <xdp.h>

This function will clear the virtual channel payload ID table in both the DisplayPort TX and all downstream DisplayPort devices.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the payload ID tables were successfully cleared.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of a sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxDisableMainLink()

void XDp_TxDisableMainLink ( XDp InstancePtr)

#include <xdp.c>

This function disables the main link.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxDiscoverTopology()

u32 XDp_TxDiscoverTopology ( XDp InstancePtr)

#include <xdp.h>

This function will explore the DisplayPort topology of downstream devices connected to the DisplayPort TX.

It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the topology discovery is successful.
  • XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.
Note
The contents of the InstancePtr->TxInstance.Topology structure will be modified.

References XDp_TxFindAccessibleDpDevices().

◆ XDp_TxEnableMainLink()

void XDp_TxEnableMainLink ( XDp InstancePtr)

#include <xdp.c>

This function enables the main link.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxEnableTrainAdaptive()

void XDp_TxEnableTrainAdaptive ( XDp InstancePtr,
u8  Enable 
)

#include <xdp.c>

This function enables or disables downshifting during the training process.

Parameters
InstancePtris a pointer to the XDp instance.
Enablecontrols the downshift feature in the training process.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxEstablishLink()

u32 XDp_TxEstablishLink ( XDp InstancePtr)

#include <xdp.c>

This function checks if the link needs training and runs the training sequence if training is required.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS was either already trained, or has been trained successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, XDp_Tx::LinkConfig, and XDp_GetCoreType.

◆ XDp_TxFindAccessibleDpDevices()

u32 XDp_TxFindAccessibleDpDevices ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress 
)

#include <xdp.h>

This function will explore the DisplayPort topology of downstream devices starting from the branch device specified by the LinkCountTotal and RelativeAddress parameters.

It will recursively go through each branch device, obtain its information by sending a LINK_ADDRESS sideband message, and add this information to the the topology's node table. For each sink device connected to a branch's downstream port, this function will obtain the details of the sink, add it to the topology's node table, as well as add it to the topology's sink list.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the total DisplayPort links connecting the DisplayPort TX to the current downstream device in the recursion.
RelativeAddressis the relative address from the DisplayPort source to the current target DisplayPort device in the recursion.
Returns
  • XST_SUCCESS if the topology discovery is successful.
  • XST_FAILURE otherwise - if sending a LINK_ADDRESS sideband message to one of the branch devices in the topology failed.
Note
The contents of the InstancePtr->TxInstance.Topology structure will be modified.

References XDp::IsReady, and XDp_GetCoreType.

Referenced by XDp_TxDiscoverTopology().

◆ XDp_TxGetDispIdDataBlock()

u32 XDp_TxGetDispIdDataBlock ( u8 *  DisplayIdRaw,
u8  SectionTag,
u8 **  DataBlockPtr 
)

#include <xdp.h>

Given a section tag, search for and retrieve the appropriate section data block that is part of the specified DisplayID structure.

Parameters
DisplayIdRawis a pointer to the DisplayID data.
SectionTagis the tag to search for that represents the desired section data block.
DataBlockPtrwill be set by this function to point to the appropriate section data block that is part of the DisplayIdRaw.
Returns
  • XST_SUCCESS if the section data block with the specified tag was found.
  • XST_FAILURE otherwise.
Note
The DataBlockPtr argument is modified to point to the entry in DisplayIdRaw that represents the beginning of the desired section data block.

◆ XDp_TxGetEdid()

u32 XDp_TxGetEdid ( XDp InstancePtr,
u8 *  Edid 
)

#include <xdp.h>

This function retrieves an immediately connected RX device's Extended Display Identification Data (EDID) structure.

Parameters
InstancePtris a pointer to the XDp instance.
Edidis a pointer to the Edid buffer to save to.
Returns
  • XST_SUCCESS if the I2C transactions to read the EDID were successful.
  • XST_ERROR_COUNT_MAX if the EDID read request timed out.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetEdidBlock()

u32 XDp_TxGetEdidBlock ( XDp InstancePtr,
u8 *  Data,
u8  BlockNum 
)

#include <xdp.h>

Retrieve an immediately connected RX device's Extended Display Identification Data (EDID) block given the block number.

A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.

Parameters
InstancePtris a pointer to the XDp instance.
Datais a pointer to the data buffer to save the block data to.
BlockNumis the EDID block number to retrieve.
Returns
  • XST_SUCCESS if the block read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if a time out occurred while attempting to read the requested block.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetGuid()

void XDp_TxGetGuid ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8 *  Guid 
)

#include <xdp.h>

This function will obtain the global unique identifier (GUID) for the target DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target device.
RelativeAddressis the relative address from the DisplayPort source to the target device.
Guidis a pointer to the GUID that will store the existing GUID of the target device.
Returns
None.
Note
None.

References XDp::IsReady, XDp_GetCoreType, and XDP_GUID_NBYTES.

◆ XDp_TxGetRemoteEdid()

u32 XDp_TxGetRemoteEdid ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8 *  Edid 
)

#include <xdp.h>

This function retrieves a remote RX device's Extended Display Identification Data (EDID) structure.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
Edidis a pointer to the Edid buffer to save to.
Returns
  • XST_SUCCESS if the I2C transactions to read the EDID were successful.
  • XST_ERROR_COUNT_MAX if the EDID read request timed out.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetRemoteEdidBlock()

u32 XDp_TxGetRemoteEdidBlock ( XDp InstancePtr,
u8 *  Data,
u8  BlockNum,
u8  LinkCountTotal,
u8 *  RelativeAddress 
)

#include <xdp.h>

Retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) block given the block number.

A block number of 0 represents the base EDID and subsequent block numbers represent EDID extension blocks.

Parameters
InstancePtris a pointer to the XDp instance.
Datais a pointer to the data buffer to save the block data to.
BlockNumis the EDID block number to retrieve.
LinkCountTotalis the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device.
RelativeAddressis the relative address from the DisplayPort source to the targeted DisplayPort device.
Returns
  • XST_SUCCESS if the block read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if a time out occurred while attempting to read the requested block.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetRemoteEdidDispIdExt()

u32 XDp_TxGetRemoteEdidDispIdExt ( XDp InstancePtr,
u8 *  Data,
u8  LinkCountTotal,
u8 *  RelativeAddress 
)

#include <xdp.h>

Search for and retrieve a downstream DisplayPort device's Extended Display Identification Data (EDID) extension block of type DisplayID.

Parameters
InstancePtris a pointer to the XDp instance.
Datais a pointer to the data buffer to save the DisplayID to.
LinkCountTotalis the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device.
RelativeAddressis the relative address from the DisplayPort source to the targeted DisplayPort device.
Returns
  • XST_SUCCESS a DisplayID extension block was found.
  • XST_ERROR_COUNT_MAX if a time out occurred while attempting to read an extension block.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE if no DisplayID extension block was found or some error occurred in the search.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetRemoteTiledDisplayDb()

u32 XDp_TxGetRemoteTiledDisplayDb ( XDp InstancePtr,
u8 *  EdidExt,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8 **  DataBlockPtr 
)

#include <xdp.h>

Search for and retrieve a downstream DisplayPort device's Tiled Display Topology (TDT) section data block that is part of the downstream device's DisplayID structure.

The DisplayID structure is part of the Extended Display Identification Data (EDID) in the form of an extension block.

Parameters
InstancePtris a pointer to the XDp instance.
EdidExtis a pointer to the data area that will be filled by the retrieved DisplayID extension block.
LinkCountTotalis the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device.
RelativeAddressis the relative address from the DisplayPort source to the targeted DisplayPort device.
DataBlockPtrwill be set by this function to point to the TDT data block that is part of the EdidExt extension block.
Returns
  • XST_SUCCESS a DisplayID extension block was found.
  • XST_ERROR_COUNT_MAX if a time out occurred while attempting to read an extension block.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE if no DisplayID extension block was found or some error occurred in the search.
Note
The EdidExt will be filled with the DisplayID EDID extension block and the DataBlockPtr argument is modified to point to the EdidExt entry representing the TDT section data block.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxGetRxCapabilities()

u32 XDp_TxGetRxCapabilities ( XDp InstancePtr)

#include <xdp.c>

This function retrieves the RX device's capabilities from the RX device's DisplayPort Configuration Data (DPCD).

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the DisplayPort Configuration Data was read successfully.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::Config, XDp_TxSinkConfig::DpcdRxCapsField, XDp::IsReady, XDp_Tx::LinkConfig, XDp_Tx::RxConfig, and XDp_GetCoreType.

Referenced by Dptx_StartLink().

◆ XDp_TxIicRead()

u32 XDp_TxIicRead ( XDp InstancePtr,
u8  IicAddress,
u16  Offset,
u16  BytesToRead,
void *  ReadData 
)

#include <xdp.c>

This function performs an I2C read over the AUX channel.

The read message will be divided into multiple transactions if the requested data spans multiple segments. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:

  • 128, an I2C read is done on segptr=0; offset=128.
  • 256, an I2C read is done on segptr=1; offset=0.
  • 384, an I2C read is done on segptr=1; offset=128.
  • 512, an I2C read is done on segptr=2; offset=0.
  • etc.
Parameters
InstancePtris a pointer to the XDp instance.
IicAddressis the address on the I2C bus of the target device.
Offsetis the offset at the specified address of the targeted I2C device that the read will start from.
BytesToReadis the number of bytes to read.
ReadDatais a pointer to a buffer that will be filled with the I2C read data.
Returns
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxIicWrite()

u32 XDp_TxIicWrite ( XDp InstancePtr,
u8  IicAddress,
u8  BytesToWrite,
void *  WriteData 
)

#include <xdp.c>

This function performs an I2C write over the AUX channel.

Parameters
InstancePtris a pointer to the XDp instance.
IicAddressis the address on the I2C bus of the target device.
BytesToWriteis the number of bytes to write.
WriteDatais a pointer to a buffer which will be used as the data source for the write.
Returns
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX request timed out.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxIsConnected()

u32 XDp_TxIsConnected ( XDp InstancePtr)

#include <xdp.c>

This function checks if there is a connected RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • TRUE if there is a connection.
  • FALSE if there is no connection.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxMstCapable()

u32 XDp_TxMstCapable ( XDp InstancePtr)

#include <xdp.h>

This function will check if the immediate downstream RX device is capable of multi-stream transport (MST) mode.

A DisplayPort Configuration Data (DPCD) version of 1.2 or higher is required and the MST capability bit in the DPCD must be set for this function to return XST_SUCCESS.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the RX device is MST capable.
  • XST_NO_FEATURE if the RX device does not support MST.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if an AUX read request timed out.
  • XST_FAILURE otherwise - if an AUX read transaction failed.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxMstCfgModeDisable()

void XDp_TxMstCfgModeDisable ( XDp InstancePtr)

#include <xdp.h>

This function will disable multi-stream transport (MST) mode for the driver.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
When disabled, the driver will behave in single-stream transport (SST) mode.

References XDp_GetCoreType.

Referenced by Dptx_AudioExample(), and Dptx_TimerExample().

◆ XDp_TxMstCfgModeEnable()

void XDp_TxMstCfgModeEnable ( XDp InstancePtr)

#include <xdp.h>

This function will enable multi-stream transport (MST) mode for the driver.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxMstCfgStreamDisable()

void XDp_TxMstCfgStreamDisable ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to disable the specified stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream ID that will be disabled.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxMstCfgStreamEnable()

void XDp_TxMstCfgStreamEnable ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function will configure the InstancePtr->TxInstance.MstStreamConfig structure to enable the specified stream.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream ID that will be enabled.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxMstDisable()

u32 XDp_TxMstDisable ( XDp InstancePtr)

#include <xdp.h>

This function will disable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if MST mode has been successful disabled in hardware.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if the AUX write request timed out.
  • XST_FAILURE otherwise - if the AUX write transaction failed.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxMstEnable()

u32 XDp_TxMstEnable ( XDp InstancePtr)

#include <xdp.h>

This function will enable multi-stream transport (MST) mode in both the DisplayPort TX and the immediate downstream RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if MST mode has been successful enabled in hardware.
  • XST_NO_FEATURE if the immediate downstream RX device does not support MST - that is, if its DisplayPort Configuration Data (DPCD) version is less than 1.2, or if the DPCD indicates that it has no DPCD capabilities.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxMstStreamIsEnabled()

u8 XDp_TxMstStreamIsEnabled ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function will check whether.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream ID to check for enable/disable status.
Returns
  • 1 if the specified stream is enabled.
  • 0 if the specified stream is disabled.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxRemoteDpcdRead()

u32 XDp_TxRemoteDpcdRead ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u32  DpcdAddress,
u32  BytesToRead,
u8 *  ReadData 
)

#include <xdp.h>

This function performs a remote DisplayPort Configuration Data (DPCD) read by sending a sideband message.

In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
DpcdAddressis the starting address to read from the RX device.
BytesToReadis the number of bytes to read.
ReadDatais a pointer to the data buffer that will be filled with read data.
Returns
  • XST_SUCCESS if the DPCD read has successfully completed (has been acknowledged).
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToRead does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxRemoteDpcdWrite()

u32 XDp_TxRemoteDpcdWrite ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u32  DpcdAddress,
u32  BytesToWrite,
u8 *  WriteData 
)

#include <xdp.h>

This function performs a remote DisplayPort Configuration Data (DPCD) write by sending a sideband message.

In case message is directed at the RX device connected immediately to the TX, the message is issued over the AUX channel. The write message will be divided into multiple transactions which write a maximum of 16 bytes each.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
DpcdAddressis the starting address to write to the RX device.
BytesToWriteis the number of bytes to write.
WriteDatais a pointer to a buffer which will be used as the data source for the write.
Returns
  • XST_SUCCESS if the DPCD write has successfully completed (has been acknowledged).
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToWrite does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxRemoteIicRead()

u32 XDp_TxRemoteIicRead ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8  IicAddress,
u16  Offset,
u16  BytesToRead,
u8 *  ReadData 
)

#include <xdp.h>

This function performs a remote I2C read by sending a sideband message.

In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel. The read message will be divided into multiple transactions which read a maximum of 16 bytes each. The segment pointer is automatically incremented and the offset is calibrated as needed. E.g. For an overall offset of:

  • 128, an I2C read is done on segptr=0; offset=128.
  • 256, an I2C read is done on segptr=1; offset=0.
  • 384, an I2C read is done on segptr=1; offset=128.
  • 512, an I2C read is done on segptr=2; offset=0.
  • etc.
Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
IicAddressis the address on the I2C bus of the target device.
Offsetis the offset at the specified address of the targeted I2C device that the read will start from.
BytesToReadis the number of bytes to read.
ReadDatais a pointer to a buffer that will be filled with the I2C read data.
Returns
  • XST_SUCCESS if the I2C read has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToRead does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxRemoteIicWrite()

u32 XDp_TxRemoteIicWrite ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8  IicAddress,
u8  BytesToWrite,
u8 *  WriteData 
)

#include <xdp.h>

This function performs a remote I2C write by sending a sideband message.

In case message is directed at the RX device connected immediately to the TX, the message is sent over the AUX channel.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
IicAddressis the address on the I2C bus of the target device.
BytesToWriteis the number of bytes to write.
WriteDatais a pointer to a buffer which will be used as the data source for the write.
Returns
  • XST_SUCCESS if the I2C write has successfully completed with no errors.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToWrite does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxResetPhy()

void XDp_TxResetPhy ( XDp InstancePtr,
u32  Reset 
)

#include <xdp.c>

This function does a PHY reset.

Parameters
InstancePtris a pointer to the XDp instance.
Resetis the type of reset to assert.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgAllocatePayload()

u32 XDp_TxSendSbMsgAllocatePayload ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8  VcId,
u16  Pbn 
)

#include <xdp.h>

This function will send an ALLOCATE_PAYLOAD sideband message which will allocate bandwidth for a virtual channel in the payload ID tables of the downstream devices connecting the DisplayPort TX to the target device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
VcIdis the unique virtual channel ID to allocate into the payload ID tables.
Pbnis the payload bandwidth number that determines how much bandwidth will be allocated for the virtual channel.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
ALLOCATE_PAYLOAD is a path message that will be serviced by all downstream DisplayPort devices connecting the DisplayPort TX and the target device.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgClearPayloadIdTable()

u32 XDp_TxSendSbMsgClearPayloadIdTable ( XDp InstancePtr)

#include <xdp.h>

This function will send a CLEAR_PAYLOAD_ID_TABLE sideband message which will de-allocate all virtual channel payload ID tables.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
CLEAR_PAYLOAD_ID_TABLE is a broadcast message sent to all downstream devices.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgEnumPathResources()

u32 XDp_TxSendSbMsgEnumPathResources ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u16 *  AvailPbn,
u16 *  FullPbn 
)

#include <xdp.h>

This function will send an ENUM_PATH_RESOURCES sideband message which will determine the available payload bandwidth number (PBN) for a path to a target device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
AvailPbnis a pointer to the available PBN of the path whose value will be filled in by this function.
FullPbnis a pointer to the total PBN of the path whose value will be filled in by this function.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
ENUM_PATH_RESOURCES is a path message that will be serviced by all downstream DisplayPort devices connecting the DisplayPort TX and the target device.
AvailPbn will be modified with the available PBN from the reply.
FullPbn will be modified with the total PBN of the path from the reply.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgLinkAddress()

u32 XDp_TxSendSbMsgLinkAddress ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
XDp_SbMsgLinkAddressReplyDeviceInfo DeviceInfo 
)

#include <xdp.h>

This function will send a LINK_ADDRESS sideband message to a target DisplayPort branch device.

It is used to determine the resources available for that device and some device information for each of the ports connected to the branch device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort branch device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort branch device.
DeviceInfois a pointer to the device information structure whose contents will be filled in with the information obtained by the LINK_ADDRESS sideband message.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
The contents of the DeviceInfo structure will be modified with the information obtained from the LINK_ADDRESS sideband message reply.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgRemoteDpcdRead()

u32 XDp_TxSendSbMsgRemoteDpcdRead ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u32  DpcdAddress,
u32  BytesToRead,
u8 *  ReadData 
)

#include <xdp.h>

This function will send a REMOTE_DPCD_READ sideband message which will read from the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
DpcdAddressis the DPCD address of the target device that data will be read from.
BytesToReadis the number of bytes to read from the specified DPCD address.
ReadDatais a pointer to a buffer that will be filled with the DPCD read data.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToRead does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgRemoteDpcdWrite()

u32 XDp_TxSendSbMsgRemoteDpcdWrite ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u32  DpcdAddress,
u32  BytesToWrite,
u8 *  WriteData 
)

#include <xdp.h>

This function will send a REMOTE_DPCD_WRITE sideband message which will write some data to the specified DisplayPort Configuration Data (DPCD) address of a downstream DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
DpcdAddressis the DPCD address of the target device that data will be written to.
BytesToWriteis the number of bytes to write to the specified DPCD address.
WriteDatais a pointer to a buffer that stores the data to write to the DPCD location.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgRemoteIicRead()

u32 XDp_TxSendSbMsgRemoteIicRead ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8  IicDeviceId,
u8  Offset,
u8  BytesToRead,
u8 *  ReadData 
)

#include <xdp.h>

This function will send a REMOTE_I2C_READ sideband message which will read from the specified I2C address of a downstream DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
IicDeviceIdis the address on the I2C bus of the target device.
Offsetis the offset at the specified address of the targeted I2C device that the read will start from.
BytesToReadis the number of bytes to read from the I2C address.
ReadDatais a pointer to a buffer that will be filled with the I2C read data.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_DATA_LOST if the requested number of BytesToRead does not equal that actually received.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSendSbMsgRemoteIicWrite()

u32 XDp_TxSendSbMsgRemoteIicWrite ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8  IicDeviceId,
u8  BytesToWrite,
u8 *  WriteData 
)

#include <xdp.h>

This function will send a REMOTE_I2C_WRITE sideband message which will write to the specified I2C address of a downstream DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target DisplayPort device.
RelativeAddressis the relative address from the DisplayPort source to the target DisplayPort device.
IicDeviceIdis the address on the I2C bus of the target device.
BytesToWriteis the number of bytes to write to the I2C address.
WriteDatais a pointer to a buffer that will be written.
Returns
  • XST_SUCCESS if the reply to the sideband message was successfully obtained and it indicates an acknowledge.
    • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_ERROR_COUNT_MAX if either waiting for a reply, or an AUX request timed out.
  • XST_FAILURE otherwise - if an AUX read or write transaction failed, the header or body CRC of the sideband message did not match the calculated value, or the a reply was negative acknowledged (NACK'ed).
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetDownspread()

u32 XDp_TxSetDownspread ( XDp InstancePtr,
u8  Enable 
)

#include <xdp.c>

This function enables or disables 0.5% spreading of the clock for both the DisplayPort and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Enablewill downspread the main link signal if set to 1 and disable downspreading if set to 0.
Returns
  • XST_SUCCESS if setting the downspread control enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetDrvHpdEventHandler()

void XDp_TxSetDrvHpdEventHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a driver's internal callback function for when a hot-plug-detect event interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetDrvHpdPulseHandler()

void XDp_TxSetDrvHpdPulseHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a driver's internal callback function for when a hot-plug-detect pulse interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetEnhancedFrameMode()

u32 XDp_TxSetEnhancedFrameMode ( XDp InstancePtr,
u8  Enable 
)

#include <xdp.c>

This function enables or disables the enhanced framing symbol sequence for both the DisplayPort TX core and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Enablewill enable enhanced frame mode if set to 1 and disable it if set to 0.
Returns
  • XST_SUCCESS if setting the enhanced frame mode enable was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetHasRedriverInPath()

void XDp_TxSetHasRedriverInPath ( XDp InstancePtr,
u8  Set 
)

#include <xdp.c>

This function sets a software switch that signifies whether or not a redriver exists on the DisplayPort output path.

XDp_TxSetVswingPreemp uses this switch to determine which set of voltage swing and pre-emphasis values to use in the TX core.

Parameters
InstancePtris a pointer to the XDp instance.
Setestablishes that a redriver exists in the DisplayPort output path.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetHpdEventHandler()

void XDp_TxSetHpdEventHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a hot-plug-detect event interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetHpdPulseHandler()

void XDp_TxSetHpdPulseHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when a hot-plug-detect pulse interrupt occurs.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetLaneCount()

u32 XDp_TxSetLaneCount ( XDp InstancePtr,
u8  LaneCount 
)

#include <xdp.c>

This function sets the number of lanes to be used by the main link for both the DisplayPort TX core and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
LaneCountis the number of lanes to be used over the main link.
Returns
  • XST_SUCCESS if setting the new lane count was successful.
  • XST_DEVICE_NOT_FOUND if no RX is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetLaneCountChangeCallback()

void XDp_TxSetLaneCountChangeCallback ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.c>

This function installs a callback function for when the driver's lane count change function is called either directly by the user or during link training.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetLinkRate()

u32 XDp_TxSetLinkRate ( XDp InstancePtr,
u8  LinkRate 
)

#include <xdp.c>

This function sets the data rate to be used by the main link for both the DisplayPort TX core and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkRateis the link rate to be used over the main link based on one of the following selects:
  • XDP_TX_LINK_BW_SET_162GBPS = 0x06 (for a 1.62 Gbps data rate)
  • XDP_TX_LINK_BW_SET_270GBPS = 0x0A (for a 2.70 Gbps data rate)
  • XDP_TX_LINK_BW_SET_540GBPS = 0x14 (for a 5.40 Gbps data rate)
Returns
  • XST_SUCCESS if setting the new link rate was successful.
  • XST_DEVICE_NOT_FOUND if no RX device is connected.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetLinkRateChangeCallback()

void XDp_TxSetLinkRateChangeCallback ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.c>

This function installs a callback function for when the driver's link rate change function is called either directly by the user or during link training.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetMsaHandler()

void XDp_TxSetMsaHandler ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.h>

This function installs a callback function for when the main stream attribute (MSA) values are updated.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetMsaValues()

void XDp_TxSetMsaValues ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function sets the main stream attributes registers of the DisplayPort TX core with the values specified in the main stream attributes configuration structure.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to set the MSA values for.
Returns
None.
Note
None.

References XDp::IsReady, XDp_GetCoreType, XDP_TX_STREAM2_MSA_START_OFFSET, XDP_TX_STREAM3_MSA_START_OFFSET, and XDP_TX_STREAM4_MSA_START_OFFSET.

◆ XDp_TxSetPeVsAdjustCallback()

void XDp_TxSetPeVsAdjustCallback ( XDp InstancePtr,
XDp_IntrHandler  CallbackFunc,
void *  CallbackRef 
)

#include <xdp.c>

This function installs a callback function for when the driver's link rate change function is called during link training.

Parameters
InstancePtris a pointer to the XDp instance.
CallbackFuncis the address to the callback function.
CallbackRefis the user data item that will be passed to the callback function when it is invoked.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxSetPhyPolarityAll()

void XDp_TxSetPhyPolarityAll ( XDp InstancePtr,
u8  Polarity 
)

#include <xdp.c>

This function sets the PHY polarity on all lanes.

Parameters
InstancePtris a pointer to the XDp instance.
Polarityis the value to set for the polarity (0 or 1).
Returns
None.
Note
The individual PHY polarity option will be disabled if set.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetPhyPolarityLane()

void XDp_TxSetPhyPolarityLane ( XDp InstancePtr,
u8  Lane,
u8  Polarity 
)

#include <xdp.c>

This function sets the PHY polarity on a specified lane.

Parameters
InstancePtris a pointer to the XDp instance.
Laneis the lane number (0-3) to set the polarity for.
Polarityis the value to set for the polarity (0 or 1).
Returns
None.
Note
If individual lane polarity is used, it is recommended that this function is called for every lane in use.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetScrambler()

u32 XDp_TxSetScrambler ( XDp InstancePtr,
u8  Enable 
)

#include <xdp.c>

This function enables or disables scrambling of symbols for both the DisplayPort and the RX device.

Parameters
InstancePtris a pointer to the XDp instance.
Enablewill enable or disable scrambling.
Returns
  • XST_SUCCESS if setting the scrambling enable was successful.
  • XST_FAILURE otherwise.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetStreamSelectFromSinkList()

void XDp_TxSetStreamSelectFromSinkList ( XDp InstancePtr,
u8  Stream,
u8  SinkNum 
)

#include <xdp.h>

This function will map a stream to a downstream DisplayPort TX device that is associated with a sink from the InstancePtr->TxInstance.Topology.SinkList.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream ID that will be mapped to a DisplayPort device.
SinkNumis the sink ID in the sink list that will be mapped to the stream.
Returns
None.
Note
The contents of the InstancePtr->TxInstance. MstStreamConfig[Stream] will be modified.
The topology will need to be determined prior to calling this function using the XDp_TxFindAccessibleDpDevices.

References XDp_GetCoreType.

◆ XDp_TxSetStreamSinkRad()

void XDp_TxSetStreamSinkRad ( XDp InstancePtr,
u8  Stream,
u8  LinkCountTotal,
u8 *  RelativeAddress 
)

#include <xdp.h>

This function will map a stream to a downstream DisplayPort TX device determined by the relative address.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number that will be mapped to a DisplayPort device.
LinkCountTotalis the total DisplayPort links connecting the DisplayPort TX to the targeted downstream device.
RelativeAddressis the relative address from the DisplayPort source to the targeted DisplayPort device.
Returns
None.
Note
The contents of the InstancePtr->TxInstance. MstStreamConfig[Stream] will be modified.

References XDp_GetCoreType.

◆ XDp_TxSetUserPixelWidth()

void XDp_TxSetUserPixelWidth ( XDp InstancePtr,
u8  UserPixelWidth 
)

#include <xdp.h>

This function configures the number of pixels output through the user data interface for DisplayPort TX core.

Parameters
InstancePtris a pointer to the XDp instance.
UserPixelWidthis the user pixel width to be configured.
Returns
None.
Note
None.

References XDp::IsReady, and XDp_GetCoreType.

◆ XDp_TxSetVideoMode()

void XDp_TxSetVideoMode ( XDp InstancePtr,
u8  Stream 
)

#include <xdp.h>

This function clears the main stream attributes registers of the DisplayPort TX core and sets them to the values specified in the main stream attributes configuration structure.

Parameters
InstancePtris a pointer to the XDp instance.
Streamis the stream number for which to set the MSA values for.
Returns
None.
Note
None.

References XDp::IsReady.

◆ XDp_TxTopologySortSinksByTiling()

void XDp_TxTopologySortSinksByTiling ( XDp InstancePtr)

#include <xdp.h>

Order the sink list with all sinks of the same tiled display being sorted by 'tile order'.

Refer to the XDp_TxGetDispIdTdtTileOrder macro on how to determine the 'tile order'. Sinks of a tiled display will have an index in the sink list that is lower than all indices of other sinks within that same tiled display that have a greater 'tile order'. When operations are done on the sink list, this ordering will ensure that sinks within the same tiled display will be acted upon in a consistent manner - with an incrementing sink list index, sinks with a lower 'tile order' will be acted upon first relative to the other sinks in the same tiled display. Multiple tiled displays may exist in the sink list.

Parameters
InstancePtris a pointer to the XDp instance.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxTopologySwapSinks()

void XDp_TxTopologySwapSinks ( XDp InstancePtr,
u8  Index0,
u8  Index1 
)

#include <xdp.h>

Swap the ordering of the sinks in the topology's sink list.

All sink information is preserved in the node table - the swapping takes place only on the pointers to the sinks in the node table. The reason this swapping is done is so that functions that use the sink list will act on the sinks in a different order.

Parameters
InstancePtris a pointer to the XDp instance.
Index0is the sink list's index of one of the sink pointers to be swapped.
Index1is the sink list's index of the other sink pointer to be swapped.
Returns
None.
Note
None.

References XDp_GetCoreType.

◆ XDp_TxWriteGuid()

void XDp_TxWriteGuid ( XDp InstancePtr,
u8  LinkCountTotal,
u8 *  RelativeAddress,
u8 *  Guid 
)

#include <xdp.h>

This function will write a global unique identifier (GUID) to the target DisplayPort device.

Parameters
InstancePtris a pointer to the XDp instance.
LinkCountTotalis the number of DisplayPort links from the DisplayPort source to the target device.
RelativeAddressis the relative address from the DisplayPort source to the target device.
Guidis a pointer to the GUID to write to the target device.
Returns
None.
Note
None.

References XDp::IsReady, XDp_GetCoreType, and XDP_GUID_NBYTES.

◆ XDp_WaitUs()

void XDp_WaitUs ( XDp InstancePtr,
u32  MicroSeconds 
)

#include <xdp.c>

This function is the delay/sleep function for the XDp driver.

For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

Parameters
InstancePtris a pointer to the XDp instance.
MicroSecondsis the number of microseconds to delay/sleep for.
Returns
None.
Note
None.

References XDp::IsReady, and XDp::UserTimerWaitUs.

Variable Documentation

◆ GuidTable

u8 GuidTable[16][XDP_GUID_NBYTES]

#include <xdp_mst.c>

This table contains a list of global unique identifiers (GUIDs) that will be issued when exploring the topology using the algorithm in the XDp_TxFindAccessibleDpDevices function.

◆ RxResetValues

u32 RxResetValues[2][2]

#include <xdp_selftest.c>

Initial value:
=
{
{XDP_RX_VERSION, 0x07000000},
{XDP_RX_CORE_ID, 0x01020A01}
}
#define XDP_RX_VERSION
Version and revision of the DisplayPort core.
Definition: xdp_hw.h:1344
#define XDP_RX_CORE_ID
DisplayPort protocol version and revision.
Definition: xdp_hw.h:1347

This table contains the default values for the DisplayPort RX core's general usage registers.

◆ TxResetValues

u32 TxResetValues[2][2]

#include <xdp_selftest.c>

Initial value:
=
{
{XDP_TX_VERSION, 0x07000000},
{XDP_TX_CORE_ID, 0x01020A00}
}
#define XDP_TX_CORE_ID
DisplayPort protocol version and revision.
Definition: xdp_hw.h:130
#define XDP_TX_VERSION
Version and revision of the DisplayPort core.
Definition: xdp_hw.h:127

This table contains the default values for the DisplayPort TX core's general usage registers.

◆ TxResetValuesMsa

u32 TxResetValuesMsa[20][2]

#include <xdp_selftest.c>

Initial value:
=
{
}
#define XDP_TX_M_VID
M value for the video stream as computed by the source core in asynchronous clock mode...
Definition: xdp_hw.h:241
#define XDP_TX_MAIN_STREAM_HTOTAL
Total number of clocks in the horizontal framing period.
Definition: xdp_hw.h:194
#define XDP_TX_MAIN_STREAM_VSWIDTH
Width of the vertical sync pulse.
Definition: xdp_hw.h:208
#define XDP_TX_MAIN_STREAM_VSTART
Number of lines between the leading edge of the vertical sync and the first line of active data...
Definition: xdp_hw.h:226
#define XDP_TX_FRAC_BYTES_PER_TU
The fractional component when calculated the XDP_TX_MIN_BYTES_PER_TU register value.
Definition: xdp_hw.h:282
#define XDP_TX_MAIN_STREAM_VRES
Number of active lines (the vertical resolution).
Definition: xdp_hw.h:216
#define XDP_TX_MAIN_STREAM_MISC0
Miscellaneous stream attributes.
Definition: xdp_hw.h:235
#define XDP_TX_TU_SIZE
Size of a transfer unit in the framing logic.
Definition: xdp_hw.h:252
#define XDP_TX_MAIN_STREAM_HRES
Number of active pixels per line (the horizontal resolution).
Definition: xdp_hw.h:211
#define XDP_TX_MAIN_STREAM_POLARITY
Polarity for the video sync signals.
Definition: xdp_hw.h:202
#define XDP_TX_INIT_WAIT
Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data t...
Definition: xdp_hw.h:289
#define XDP_TX_USER_DATA_COUNT_PER_LANE
Used to translate the number of pixels per line to the native internal 16-bit datapath.
Definition: xdp_hw.h:269
#define XDP_TX_USER_PIXEL_WIDTH
Selects the width of the user data input port.
Definition: xdp_hw.h:266
#define XDP_TX_MAIN_STREAM_VTOTAL
Total number of lines in the video frame.
Definition: xdp_hw.h:199
#define XDP_TX_MAIN_STREAM_HSWIDTH
Width of the horizontal sync pulse.
Definition: xdp_hw.h:205
#define XDP_TX_MIN_BYTES_PER_TU
The minimum number of bytes per transfer unit.
Definition: xdp_hw.h:279
#define XDP_TX_MAIN_STREAM_INTERLACED
Video is interlaced.
Definition: xdp_hw.h:278
#define XDP_TX_MAIN_STREAM_MISC1
Miscellaneous stream attributes.
Definition: xdp_hw.h:238
#define XDP_TX_N_VID
N value for the video stream as computed by the source core in asynchronous clock mode...
Definition: xdp_hw.h:255
#define XDP_TX_MAIN_STREAM_HSTART
Number of clocks between the leading edge of the horizontal sync and the start of active data...
Definition: xdp_hw.h:219

This table contains the default values for the DisplayPort TX core's main stream attribute (MSA) registers.

◆ XDp_ConfigTable

XDp_Config XDp_ConfigTable[XPAR_XDP_NUM_INSTANCES]

#include <xdp_sinit.c>

A table of configuration structures containing the configuration information for each DisplayPort TX core in the system.