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qspipsu
Xilinx SDK Drivers API Documentation
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Data Structures | |
struct | XQspiPsu_Msg |
This typedef contains configuration information for a flash message. More... | |
struct | XQspiPsu_Config |
This typedef contains configuration information for the device. More... | |
struct | XQspiPsu |
The XQspiPsu driver instance data. More... | |
Macros | |
#define | XQSPIPS_BASEADDR 0XFF0F0000U |
QSPI Base Address. More... | |
#define | XQSPIPSU_BASEADDR 0xFF0F0100U |
GQSPI Base Address. More... | |
#define | XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U ) |
Register: XQSPIPS_EN_REG. More... | |
#define | XQSPIPSU_CFG_OFFSET 0X00000000U |
Register: XQSPIPSU_CFG. More... | |
#define | XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U |
Register: XQSPIPSU_CFG. More... | |
#define | XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U |
Register: XQSPIPSU_CFG. More... | |
#define | XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000 |
LQSPI mode enable. More... | |
#define | XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000 |
Both memories or one. More... | |
#define | XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000 |
Seperate memory bus. More... | |
#define | XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000 |
Upper memory page. More... | |
#define | XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000 |
Upper memory page. More... | |
#define | XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000 |
Enable mode bits. More... | |
#define | XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000 |
Mode on. More... | |
#define | XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 |
Mode value for dual I/O or quad I/O. More... | |
#define | XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF |
Read instr code. More... | |
#define | XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 |
Default LQSPI CR value. More... | |
#define | XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 |
Default LQSPI CFG value. More... | |
#define | XQSPIPSU_ISR_OFFSET 0X00000004U |
Register: XQSPIPSU_ISR. More... | |
#define | XQSPIPSU_IER_OFFSET 0X00000008U |
Register: XQSPIPSU_IER. More... | |
#define | XQSPIPSU_IDR_OFFSET 0X0000000CU |
Register: XQSPIPSU_IDR. More... | |
#define | XQSPIPSU_IMR_OFFSET 0X00000010U |
Register: XQSPIPSU_IMR. More... | |
#define | XQSPIPSU_EN_OFFSET 0X00000014U |
Register: XQSPIPSU_EN_REG. More... | |
#define | XQSPIPSU_TXD_OFFSET 0X0000001CU |
Register: XQSPIPSU_TXD. More... | |
#define | XQSPIPSU_RXD_OFFSET 0X00000020U |
Register: XQSPIPSU_RXD. More... | |
#define | XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U |
Register: XQSPIPSU_TX_THRESHOLD. More... | |
#define | XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU |
Register: XQSPIPSU_RX_THRESHOLD. More... | |
#define | XQSPIPSU_GPIO_OFFSET 0X00000030U |
Register: XQSPIPSU_GPIO. More... | |
#define | XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U |
Register: XQSPIPSU_LPBK_DLY_ADJ. More... | |
#define | XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U |
Register: XQSPIPSU_GEN_FIFO. More... | |
#define | XQSPIPSU_SEL_OFFSET 0X00000044U |
Register: XQSPIPSU_SEL. More... | |
#define | XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU |
Register: XQSPIPSU_FIFO_CTRL. More... | |
#define | XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U |
Register: XQSPIPSU_GF_THRESHOLD. More... | |
#define | XQSPIPSU_POLL_CFG_OFFSET 0X00000054U |
Register: XQSPIPSU_POLL_CFG. More... | |
#define | XQSPIPSU_P_TO_OFFSET 0X00000058U |
Register: XQSPIPSU_P_TIMEOUT. More... | |
#define | XQSPIPSU_XFER_STS_OFFSET 0X0000005CU |
Register: XQSPIPSU_XFER_STS. More... | |
#define | XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U |
Register: XQSPIPSU_GF_SNAPSHOT. More... | |
#define | XQSPIPSU_RX_COPY_OFFSET 0X00000064U |
Register: XQSPIPSU_RX_COPY. More... | |
#define | XQSPIPSU_MOD_ID_OFFSET 0X000000FCU |
Register: XQSPIPSU_MOD_ID. More... | |
#define | XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U |
Register: XQSPIPSU_QSPIDMA_DST_ADDR. More... | |
#define | XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U |
Register: XQSPIPSU_QSPIDMA_DST_SIZE. More... | |
#define | XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U |
Register: XQSPIPSU_QSPIDMA_DST_STS. More... | |
#define | XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU |
Register: XQSPIPSU_QSPIDMA_DST_CTRL. More... | |
#define | XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U |
Register: XQSPIPSU_QSPIDMA_DST_I_STS. More... | |
#define | XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U |
Register: XQSPIPSU_QSPIDMA_DST_I_EN. More... | |
#define | XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU |
Register: XQSPIPSU_QSPIDMA_DST_I_DIS. More... | |
#define | XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U |
Register: XQSPIPSU_QSPIDMA_DST_IMR. More... | |
#define | XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U |
Register: XQSPIPSU_QSPIDMA_DST_CTRL2. More... | |
#define | XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U |
Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB. More... | |
#define | XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU |
Register: XQSPIPSU_QSPIDMA_FUTURE_ECO. More... | |
#define | XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset)) |
Read a register. More... | |
#define | XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
Write to a register. More... | |
Typedefs | |
typedef void(* | XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 ByteCount) |
The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. More... | |
Functions | |
s32 | XQspiPsu_CfgInitialize (XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, u32 EffectiveAddr) |
Initializes a specific XQspiPsu instance such that the driver is ready to use. More... | |
void | XQspiPsu_Reset (XQspiPsu *InstancePtr) |
Resets the QSPIPSU device. More... | |
void | XQspiPsu_Abort (XQspiPsu *InstancePtr) |
Aborts a transfer in progress by. More... | |
s32 | XQspiPsu_PolledTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 NumMsg) |
This function performs a transfer on the bus in polled mode. More... | |
s32 | XQspiPsu_InterruptTransfer (XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, u32 NumMsg) |
This function initiates a transfer on the bus and enables interrupts. More... | |
s32 | XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr) |
Handles interrupt based transfers by acting on GENFIFO and DMA interurpts. More... | |
void | XQspiPsu_SetStatusHandler (XQspiPsu *InstancePtr, void *CallBackRef, XQspiPsu_StatusHandler FuncPointer) |
Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More... | |
XQspiPsu_Config * | XQspiPsu_LookupConfig (u16 DeviceId) |
Looks up the device configuration based on the unique device ID. More... | |
s32 | XQspiPsu_SetClkPrescaler (XQspiPsu *InstancePtr, u8 Prescaler) |
Configures the clock according to the prescaler passed. More... | |
void | XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus) |
This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used. More... | |
s32 | XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options) |
This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More... | |
s32 | XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options) |
This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More... | |
u32 | XQspiPsu_GetOptions (XQspiPsu *InstancePtr) |
This function gets the options for the QSPIPSU device. More... | |
s32 | XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode) |
This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options. More... | |
Variables | |
XQspiPsu_Config | XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES] |
This table contains configuration information for each QSPIPSU device in the system. More... | |
XQspiPsu_Config | XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES] |
This table contains configuration information for each QSPIPSU device in the system. More... | |
#define XQSPIPS_BASEADDR 0XFF0F0000U |
#include <xqspipsu_hw.h>
QSPI Base Address.
#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U ) |
#include <xqspipsu_hw.h>
Register: XQSPIPS_EN_REG.
#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 |
#include <xqspipsu_hw.h>
Default LQSPI CFG value.
#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF |
#include <xqspipsu_hw.h>
Read instr code.
#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 |
#include <xqspipsu_hw.h>
Default LQSPI CR value.
#define XQSPIPSU_BASEADDR 0xFF0F0100U |
#include <xqspipsu_hw.h>
GQSPI Base Address.
#define XQSPIPSU_CFG_OFFSET 0X00000000U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_CFG.
Referenced by XQspiPsu_ClearOptions(), XQspiPsu_GetOptions(), XQspiPsu_Reset(), XQspiPsu_SetOptions(), and XQspiPsu_SetReadMode().
#define XQSPIPSU_EN_OFFSET 0X00000014U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_EN_REG.
#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_FIFO_CTRL.
#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_GEN_FIFO.
#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_GF_SNAPSHOT.
#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_GF_THRESHOLD.
#define XQSPIPSU_GPIO_OFFSET 0X00000030U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_GPIO.
#define XQSPIPSU_IDR_OFFSET 0X0000000CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_IDR.
#define XQSPIPSU_IER_OFFSET 0X00000008U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_IER.
#define XQSPIPSU_IMR_OFFSET 0X00000010U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_IMR.
#define XQSPIPSU_ISR_OFFSET 0X00000004U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_ISR.
Referenced by XQspiPsu_Abort(), and XQspiPsu_InterruptHandler().
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_LPBK_DLY_ADJ.
#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000 |
#include <xqspipsu_hw.h>
Upper memory page.
#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000 |
#include <xqspipsu_hw.h>
LQSPI mode enable.
#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 |
#include <xqspipsu_hw.h>
Mode value for dual I/O or quad I/O.
#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000 |
#include <xqspipsu_hw.h>
Enable mode bits.
#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000 |
#include <xqspipsu_hw.h>
Mode on.
#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_CFG.
#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_CFG.
#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000 |
#include <xqspipsu_hw.h>
Seperate memory bus.
#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000 |
#include <xqspipsu_hw.h>
Both memories or one.
#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000 |
#include <xqspipsu_hw.h>
Upper memory page.
#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_MOD_ID.
#define XQSPIPSU_P_TO_OFFSET 0X00000058U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_P_TIMEOUT.
#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_POLL_CFG.
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB.
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_ADDR.
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_CTRL2.
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_CTRL.
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_I_DIS.
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_I_EN.
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_I_STS.
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_IMR.
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_SIZE.
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_DST_STS.
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_QSPIDMA_FUTURE_ECO.
#define XQspiPsu_ReadReg | ( | BaseAddress, | |
RegOffset | |||
) | XQspiPsu_In32((BaseAddress) + (RegOffset)) |
#include <xqspipsu_hw.h>
Read a register.
BaseAddress | contains the base address of the device. |
RegOffset | contains the offset from the 1st register of the device to the target register. |
Referenced by XQspiPsu_Abort(), XQspiPsu_ClearOptions(), XQspiPsu_GetOptions(), XQspiPsu_InterruptHandler(), XQspiPsu_Reset(), XQspiPsu_SetOptions(), and XQspiPsu_SetReadMode().
#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_RX_COPY.
#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_RX_THRESHOLD.
#define XQSPIPSU_RXD_OFFSET 0X00000020U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_RXD.
#define XQSPIPSU_SEL_OFFSET 0X00000044U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_SEL.
#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_TX_THRESHOLD.
#define XQSPIPSU_TXD_OFFSET 0X0000001CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_TXD.
#define XQspiPsu_WriteReg | ( | BaseAddress, | |
RegOffset, | |||
RegisterValue | |||
) | XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
#include <xqspipsu_hw.h>
Write to a register.
BaseAddress | contains the base address of the device. |
RegOffset | contains the offset from the 1st register of the device to target register. |
RegisterValue | is the value to be written to the register. |
Referenced by XQspiPsu_Abort().
#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU |
#include <xqspipsu_hw.h>
Register: XQSPIPSU_XFER_STS.
typedef void(* XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 ByteCount) |
#include <xqspipsu.h>
The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device.
The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.
CallBackRef | is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer. |
StatusEvent | holds one or more status events that have occurred. See the XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback. |
ByteCount | indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error. |
void XQspiPsu_Abort | ( | XQspiPsu * | InstancePtr | ) |
#include <xqspipsu.c>
Aborts a transfer in progress by.
InstancePtr | is a pointer to the XQspiPsu instance. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQSPIPSU_ISR_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.
Referenced by XQspiPsu_Reset().
s32 XQspiPsu_CfgInitialize | ( | XQspiPsu * | InstancePtr, |
XQspiPsu_Config * | ConfigPtr, | ||
u32 | EffectiveAddr | ||
) |
#include <xqspipsu.c>
Initializes a specific XQspiPsu instance such that the driver is ready to use.
InstancePtr | is a pointer to the XQspiPsu instance. |
ConfigPtr | is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config. |
EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, and XQspiPsu::IsBusy.
s32 XQspiPsu_ClearOptions | ( | XQspiPsu * | InstancePtr, |
u32 | Options | ||
) |
#include <xqspipsu.h>
This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.
The device must be idle rather than busy transferring data before setting these device options.
InstancePtr | is a pointer to the XQspiPsu instance. |
Options | contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.
u32 XQspiPsu_GetOptions | ( | XQspiPsu * | InstancePtr | ) |
#include <xqspipsu.h>
This function gets the options for the QSPIPSU device.
The options control how the device behaves relative to the QSPIPSU bus.
InstancePtr | is a pointer to the XQspiPsu instance. |
Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.
s32 XQspiPsu_InterruptHandler | ( | XQspiPsu * | InstancePtr | ) |
#include <xqspipsu.c>
Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
InstancePtr | is a pointer to the XQspiPsu instance. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::ReadMode, XQSPIPSU_ISR_OFFSET, and XQspiPsu_ReadReg.
s32 XQspiPsu_InterruptTransfer | ( | XQspiPsu * | InstancePtr, |
XQspiPsu_Msg * | Msg, | ||
u32 | NumMsg | ||
) |
#include <xqspipsu.c>
This function initiates a transfer on the bus and enables interrupts.
The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.
InstancePtr | is a pointer to the XQspiPsu instance. |
Msg | is a pointer to the structure containing transfer data. |
NumMsg | is the number of messages to be transferred. |
References XQspiPsu::IsBusy, and XQspiPsu::IsReady.
XQspiPsu_Config * XQspiPsu_LookupConfig | ( | u16 | DeviceId | ) |
#include <xqspipsu.h>
Looks up the device configuration based on the unique device ID.
A table contains the configuration info for each device in the system.
DeviceId | contains the ID of the device to look up the configuration for. |
A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.
s32 XQspiPsu_PolledTransfer | ( | XQspiPsu * | InstancePtr, |
XQspiPsu_Msg * | Msg, | ||
u32 | NumMsg | ||
) |
#include <xqspipsu.c>
This function performs a transfer on the bus in polled mode.
The messages passed are all transferred on the bus between one CS assert and de-assert.
InstancePtr | is a pointer to the XQspiPsu instance. |
Msg | is a pointer to the structure containing transfer data. |
NumMsg | is the number of messages to be transferred. |
References XQspiPsu::IsBusy, and XQspiPsu::IsReady.
void XQspiPsu_Reset | ( | XQspiPsu * | InstancePtr | ) |
#include <xqspipsu.c>
Resets the QSPIPSU device.
Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.
The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.
InstancePtr | is a pointer to the XQspiPsu instance. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Abort(), XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.
void XQspiPsu_SelectFlash | ( | XQspiPsu * | InstancePtr, |
u8 | FlashCS, | ||
u8 | FlashBus | ||
) |
#include <xqspipsu.h>
This funciton should be used to tell the QSPIPSU driver the HW flash configuration being used.
This API should be called atleast once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.
InstancePtr | is a pointer to the XQspiPsu instance. |
FlashCS | - Flash Chip Select. |
FlashBus | - Flash Bus (Upper, Lower or Both). |
s32 XQspiPsu_SetClkPrescaler | ( | XQspiPsu * | InstancePtr, |
u8 | Prescaler | ||
) |
#include <xqspipsu.h>
Configures the clock according to the prescaler passed.
InstancePtr | is a pointer to the XQspiPsu instance. |
Prescaler | - clock prescaler to be set. |
References XQspiPsu::IsReady.
s32 XQspiPsu_SetOptions | ( | XQspiPsu * | InstancePtr, |
u32 | Options | ||
) |
#include <xqspipsu.h>
This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.
The device must be idle rather than busy transferring data before setting these device options.
InstancePtr | is a pointer to the XQspiPsu instance. |
Options | contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.
s32 XQspiPsu_SetReadMode | ( | XQspiPsu * | InstancePtr, |
u32 | Mode | ||
) |
#include <xqspipsu.h>
This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.
InstancePtr | is a pointer to the XQspiPsu instance. |
Mode | contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h. |
References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, and XQspiPsu_ReadReg.
void XQspiPsu_SetStatusHandler | ( | XQspiPsu * | InstancePtr, |
void * | CallBackRef, | ||
XQspiPsu_StatusHandler | FuncPointer | ||
) |
#include <xqspipsu.c>
Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.
The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.
XST_SPI_TRANSFER_DONE The requested data transfer is done
XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data but there were none available in the transmit register/FIFO. This typically means the slave application did not issue a transfer request fast enough, or the processor/driver could not fill the transmit register/FIFO fast enough.
XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received but the receive data register/FIFO was full.
InstancePtr | is a pointer to the XQspiPsu instance. |
CallBackRef | is the upper layer callback reference passed back when the callback function is invoked. |
FuncPointer | is the pointer to the callback function. |
The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.
References XQspiPsu::IsReady, and XQspiPsu::StatusRef.
XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] |
#include <xqspipsu_sinit.c>
This table contains configuration information for each QSPIPSU device in the system.
XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] |
#include <xqspipsu_g.c>
This table contains configuration information for each QSPIPSU device in the system.