i2srx
Xilinx SDK Drivers API Documentation
I2srx_v1_0

Data Structures

struct  XI2srx_Config
 This typedef contains configuration information for the XI2s Receiver. More...
 
struct  XI2s_Rx
 The XI2s Receiver driver instance data. More...
 
struct  XI2s_Rx_LogItem
 This structure is used to store log events. More...
 
struct  XI2s_Rx_Log
 The XI2s Receiver Log buffer. More...
 

Macros

#define XI2s_Rx_GetMaxChannels(InstancePtr)
 This macro reads the maximum number of XI2s channels available. More...
 
#define XI2s_Rx_IsXI2sMaster(InstancePtr)
 This macro returns the XI2s operating mode. More...
 

Typedefs

typedef void(* XI2s_Rx_Callback) (void *CallbackRef)
 Callback function data type for handling interrupt requests from the XI2s Receiver peripheral. More...
 

Enumerations

enum  XI2s_Rx_ChMuxInput {
  XI2S_RX_CHMUX_DISABLED = 0, XI2S_RX_CHMUX_XI2S_01, XI2S_RX_CHMUX_XI2S_23, XI2S_RX_CHMUX_XI2S_45,
  XI2S_RX_CHMUX_XI2S_67, XI2S_RX_CHMUX_WAVEGEN
}
 This typedef specifies the input sources of the the XI2s Receiver. More...
 

Functions

int XI2s_Rx_CfgInitialize (XI2s_Rx *InstancePtr, XI2srx_Config *CfgPtr, UINTPTR EffectiveAddr)
 This function initializes the XI2s Receiver. More...
 
void XI2s_Rx_Enable (XI2s_Rx *InstancePtr, u8 Enable)
 This function enables/disables the XI2s Receiver. More...
 
void XI2s_Rx_LatchAesChannelStatus (XI2s_Rx *InstancePtr)
 This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers. More...
 
void XI2s_Rx_IntrEnable (XI2s_Rx *InstancePtr, u32 Mask)
 This function enables the specified interrupt of the XI2s Receiver. More...
 
void XI2s_Rx_IntrDisable (XI2s_Rx *InstancePtr, u32 Mask)
 This function disables the specified interrupt of the XI2s Receiver. More...
 
int XI2s_Rx_SetChMux (XI2s_Rx *InstancePtr, XI2s_Rx_ChannelId ChID, XI2s_Rx_ChMuxInput InputSource)
 This function sets the input source for the specified AXI-Stream channel pair. More...
 
u32 XI2s_Rx_SetSclkOutDiv (XI2s_Rx *InstancePtr, u32 MClk, u32 Fs)
 This function calculates the SCLK Output divider value of the I2s timing generator. More...
 
void XI2s_Rx_SetAesChStatus (XI2s_Rx *InstancePtr, u8 *AesChStatusBuf)
 This function sets the AES Channel Status bits to insert. More...
 
void XI2s_Rx_ClrAesChStatRegs (XI2s_Rx *InstancePtr)
 This function clears the captured AES Channel Status bits. More...
 
int XI2s_Rx_SelfTest (XI2s_Rx *InstancePtr)
 Runs a self-test on the driver/device. More...
 
XI2srx_ConfigXI2s_Rx_LookupConfig (u16 DeviceId)
 This function returns a reference to an XI2srx_Config structure based on the core id, DeviceId. More...
 
int XI2s_Rx_Initialize (XI2s_Rx *InstancePtr, u16 DeviceId)
 Initializes a specific XI2s_Rx instance such that the driver is ready to use. More...
 
void XI2s_Rx_IntrHandler (void *InstancePtr)
 This function is the interrupt handler for the XI2s Receiver driver. More...
 
int XI2s_Rx_SetHandler (XI2s_Rx *InstancePtr, XI2s_Rx_HandlerType HandlerType, XI2s_Rx_Callback FuncPtr, void *CallbackRef)
 This function installs an asynchronous callback function for the given HandlerType: More...
 
void XI2s_Rx_LogDisplay (XI2s_Rx *InstancePtr)
 This function prints the contents of the logging buffer. More...
 
void XI2s_Rx_LogReset (XI2s_Rx *InstancePtr)
 This function clears the contents of the logging buffer. More...
 
void XI2s_Rx_LogWrite (XI2s_Rx *InstancePtr, XI2s_Rx_LogEvt Event, u8 Data)
 This function writes XI2s Receiver logs into the buffer. More...
 
XI2s_Rx_LogItemXI2s_Rx_LogRead (XI2s_Rx *InstancePtr)
 This function returns the next item in the logging buffer. More...
 
void XI2s_Rx_SetAesChStat (u32 I2srx_SrcBuf[], u8 I2srx_DstBuf[])
 This function reads the source buffer and writes to a destination buffer. More...
 

Handler Types

enum  XI2s_Rx_HandlerType { XI2S_RX_HANDLER_AES_BLKCMPLT = 0, XI2S_RX_HANDLER_AUD_OVRFLW, XI2S_RX_NUM_HANDLERS }
 These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. More...
 
enum  XI2s_Rx_ChannelId {
  XI2S_RX_CHID0 = 0, XI2S_RX_CHID1, XI2S_RX_CHID2, XI2S_RX_CHID3,
  XI2S_RX_NUM_CHANNELS
}
 These constants specify different channel ID's. More...
 
#define XI2S_RX_LOG_ITEM_BUFFER_SIZE   (256)
 @ name Log Item Buffer Size More...
 

Handler Types

enum  XI2s_Rx_LogEvt { XI2S_RX_AES_BLKCMPLT_EVT, XI2S_RX_AUD_OVERFLOW_EVT, XI2S_RX_LOG_EVT_INVALID }
 These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. More...
 

Register Map

Register offsets for the XI2srx device.

#define XI2S_RX_CORE_VER_OFFSET   0x00
 Core Version Register. More...
 
#define XI2S_RX_CORE_CFG_OFFSET   0x04
 Core Configuration Register. More...
 
#define XI2S_RX_CORE_CTRL_OFFSET   0x08
 Core Control Register. More...
 
#define XI2S_RX_IRQCTRL_OFFSET   0x10
 Interrupt Control Register. More...
 
#define XI2S_RX_IRQSTS_OFFSET   0x14
 Interrupt Status Register. More...
 
#define XI2S_RX_TMR_CTRL_OFFSET   0x20
 XI2S Timing Control Register. More...
 
#define XI2S_RX_CH01_OFFSET   0x30
 Audio Channel 0/1 Control Register. More...
 
#define XI2S_RX_CH23_OFFSET   0x34
 Audio Channel 2/3 Control Register. More...
 
#define XI2S_RX_CH45_OFFSET   0x38
 Audio Channel 4/5 Control Register. More...
 
#define XI2S_RX_CH67_OFFSET   0x3C
 Audio Channel 6/7 Control Register. More...
 
#define XI2S_RX_AES_CHSTS0_OFFSET   0x50
 AES Channel Status 0 Register. More...
 
#define XI2S_RX_AES_CHSTS1_OFFSET   0x54
 AES Channel Status 1 Register. More...
 
#define XI2S_RX_AES_CHSTS2_OFFSET   0x58
 AES Channel Status 2 Register. More...
 
#define XI2S_RX_AES_CHSTS3_OFFSET   0x5C
 AES Channel Status 3 Register. More...
 
#define XI2S_RX_AES_CHSTS4_OFFSET   0x60
 AES Channel Status 4 Register. More...
 
#define XI2S_RX_AES_CHSTS5_OFFSET   0x64
 AES Channel Status 5 Register. More...
 

Core Configuration Register masks and shifts

#define XI2S_RX_REG_CFG_MSTR_SHIFT   (0)
 Is XI2S Master bit shift. More...
 
#define XI2S_RX_REG_CFG_MSTR_MASK   (1 << XI2S_RX_REG_CFG_MSTR_SHIFT)
 Is XI2S Master mask. More...
 
#define XI2S_RX_REG_CFG_NUM_CH_SHIFT   (8)
 Maximum number of channels bit shift. More...
 
#define XI2S_RX_REG_CFG_NUM_CH_MASK   (0xF << XI2S_RX_REG_CFG_NUM_CH_SHIFT)
 Maximum number of channels mask. More...
 
#define XI2S_RX_REG_CFG_DWDTH_SHIFT   (16)
 XI2S Data Width bit shift. More...
 
#define XI2S_RX_REG_CFG_DWDTH_MASK   (1 << XI2S_RX_REG_CFG_DWDTH_SHIFT)
 XI2S Data Width mask. More...
 

Core Control Register masks and shifts

#define XI2S_RX_REG_CTRL_EN_SHIFT   (0)
 Module Enable bit shift. More...
 
#define XI2S_RX_REG_CTRL_EN_MASK   (1 << XI2S_RX_REG_CTRL_EN_SHIFT)
 Module Enable mask. More...
 
#define XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT   (16)
 Latch AES Channel Status bit shift. More...
 
#define XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK   (1 << XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT)
 Latch AES Channel Status mask. More...
 

Interrupt masks and shifts

#define XI2S_RX_INTR_AES_BLKCMPLT_SHIFT   (0)
 AES Block Complete Interrupt bit shift. More...
 
#define XI2S_RX_INTR_AES_BLKCMPLT_MASK   (1 << XI2S_RX_INTR_AES_BLKCMPLT_SHIFT)
 AES Block Complete Interrupt mask. More...
 
#define XI2S_RX_INTR_AUDOVRFLW_SHIFT   (1)
 Audio Overflow Detected Interrupt bit shift. More...
 
#define XI2S_RX_INTR_AUDOVRFLW_MASK   (1 << XI2S_RX_INTR_AUDOVRFLW_SHIFT)
 Audio Overflow Detected Interrupt mask. More...
 
#define XI2S_RX_GINTR_EN_SHIFT   (31)
 Global Interrupt Enable bit shift. More...
 
#define XI2S_RX_GINTR_EN_MASK   (1 << XI2S_RX_GINTR_EN_SHIFT)
 Global Interrupt Enable mask. More...
 

XI2S Timing Control Register masks and shifts

#define XI2S_RX_REG_TMR_SCLKDIV_SHIFT   (0)
 SClk Divider bit shift. More...
 
#define XI2S_RX_REG_TMR_SCLKDIV_MASK   (0xF << XI2S_RX_REG_TMR_SCLKDIV_SHIFT)
 SClk Divider mask. More...
 

Audio Channel Control Register masks and shifts

#define XI2S_RX_REG_CHCTRL_CHMUX_SHIFT   (0)
 Channel MUX bit shift. More...
 
#define XI2S_RX_REG_CHCTRL_CHMUX_MASK   (0x7 << XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)
 Channel MUX mask. More...
 

Register access macro definition

#define XI2s_Rx_In32   Xil_In32
 Input Operations. More...
 
#define XI2s_Rx_Out32   Xil_Out32
 Output Operations. More...
 
#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)   XI2s_Rx_In32((BaseAddress) + ((u32)RegOffset))
 This macro reads a value from a XI2s Receiver register. More...
 
#define XI2s_Rx_WriteReg(BaseAddress, RegOffset, Data)   XI2s_Rx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
 This macro writes a value to a XI2s Receiver register. More...
 

Macro Definition Documentation

◆ XI2S_RX_AES_CHSTS0_OFFSET

#define XI2S_RX_AES_CHSTS0_OFFSET   0x50

#include <xi2srx_hw.h>

AES Channel Status 0 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs(), and XI2s_Rx_SetAesChStatus().

◆ XI2S_RX_AES_CHSTS1_OFFSET

#define XI2S_RX_AES_CHSTS1_OFFSET   0x54

#include <xi2srx_hw.h>

AES Channel Status 1 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

◆ XI2S_RX_AES_CHSTS2_OFFSET

#define XI2S_RX_AES_CHSTS2_OFFSET   0x58

#include <xi2srx_hw.h>

AES Channel Status 2 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

◆ XI2S_RX_AES_CHSTS3_OFFSET

#define XI2S_RX_AES_CHSTS3_OFFSET   0x5C

#include <xi2srx_hw.h>

AES Channel Status 3 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

◆ XI2S_RX_AES_CHSTS4_OFFSET

#define XI2S_RX_AES_CHSTS4_OFFSET   0x60

#include <xi2srx_hw.h>

AES Channel Status 4 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

◆ XI2S_RX_AES_CHSTS5_OFFSET

#define XI2S_RX_AES_CHSTS5_OFFSET   0x64

#include <xi2srx_hw.h>

AES Channel Status 5 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

◆ XI2S_RX_CH01_OFFSET

#define XI2S_RX_CH01_OFFSET   0x30

#include <xi2srx_hw.h>

Audio Channel 0/1 Control Register.

Referenced by XI2s_Rx_SetChMux().

◆ XI2S_RX_CH23_OFFSET

#define XI2S_RX_CH23_OFFSET   0x34

#include <xi2srx_hw.h>

Audio Channel 2/3 Control Register.

◆ XI2S_RX_CH45_OFFSET

#define XI2S_RX_CH45_OFFSET   0x38

#include <xi2srx_hw.h>

Audio Channel 4/5 Control Register.

◆ XI2S_RX_CH67_OFFSET

#define XI2S_RX_CH67_OFFSET   0x3C

#include <xi2srx_hw.h>

Audio Channel 6/7 Control Register.

◆ XI2S_RX_CORE_CFG_OFFSET

#define XI2S_RX_CORE_CFG_OFFSET   0x04

#include <xi2srx_hw.h>

Core Configuration Register.

◆ XI2S_RX_CORE_CTRL_OFFSET

#define XI2S_RX_CORE_CTRL_OFFSET   0x08

#include <xi2srx_hw.h>

Core Control Register.

Referenced by XI2s_Rx_Enable(), and XI2s_Rx_LatchAesChannelStatus().

◆ XI2S_RX_CORE_VER_OFFSET

#define XI2S_RX_CORE_VER_OFFSET   0x00

#include <xi2srx_hw.h>

Core Version Register.

◆ XI2s_Rx_GetMaxChannels

#define XI2s_Rx_GetMaxChannels (   InstancePtr)

#include <xi2srx_selftest.c>

Value:
((XI2s_Rx_ReadReg((InstancePtr)->Config.BaseAddress, (XI2S_RX_CORE_CFG_OFFSET))\
#define XI2S_RX_REG_CFG_NUM_CH_MASK
Maximum number of channels mask.
Definition: xi2srx_hw.h:96
#define XI2S_RX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2srx_hw.h:66
#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a XI2s Receiver register.
Definition: xi2srx_hw.h:185
#define XI2S_RX_REG_CFG_NUM_CH_SHIFT
Maximum number of channels bit shift.
Definition: xi2srx_hw.h:94

This macro reads the maximum number of XI2s channels available.

Parameters
InstancePtris a pointer to the XI2s_Rx core instance.
Returns
Maximum number of XI2s Channels.
Note
C-style signature: u32 XI2s_Rx_GetMaxChannels(XI2s_Rx *InstancePtr)

◆ XI2S_RX_GINTR_EN_MASK

#define XI2S_RX_GINTR_EN_MASK   (1 << XI2S_RX_GINTR_EN_SHIFT)

#include <xi2srx_hw.h>

Global Interrupt Enable mask.

◆ XI2S_RX_GINTR_EN_SHIFT

#define XI2S_RX_GINTR_EN_SHIFT   (31)

#include <xi2srx_hw.h>

Global Interrupt Enable bit shift.

◆ XI2s_Rx_In32

#define XI2s_Rx_In32   Xil_In32

#include <xi2srx_hw.h>

Input Operations.

◆ XI2S_RX_INTR_AES_BLKCMPLT_MASK

#define XI2S_RX_INTR_AES_BLKCMPLT_MASK   (1 << XI2S_RX_INTR_AES_BLKCMPLT_SHIFT)

#include <xi2srx_hw.h>

AES Block Complete Interrupt mask.

Referenced by XI2s_Rx_IntrHandler().

◆ XI2S_RX_INTR_AES_BLKCMPLT_SHIFT

#define XI2S_RX_INTR_AES_BLKCMPLT_SHIFT   (0)

#include <xi2srx_hw.h>

AES Block Complete Interrupt bit shift.

◆ XI2S_RX_INTR_AUDOVRFLW_MASK

#define XI2S_RX_INTR_AUDOVRFLW_MASK   (1 << XI2S_RX_INTR_AUDOVRFLW_SHIFT)

#include <xi2srx_hw.h>

Audio Overflow Detected Interrupt mask.

◆ XI2S_RX_INTR_AUDOVRFLW_SHIFT

#define XI2S_RX_INTR_AUDOVRFLW_SHIFT   (1)

#include <xi2srx_hw.h>

Audio Overflow Detected Interrupt bit shift.

◆ XI2S_RX_IRQCTRL_OFFSET

#define XI2S_RX_IRQCTRL_OFFSET   0x10

#include <xi2srx_hw.h>

Interrupt Control Register.

Referenced by XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), and XI2s_Rx_IntrHandler().

◆ XI2S_RX_IRQSTS_OFFSET

#define XI2S_RX_IRQSTS_OFFSET   0x14

#include <xi2srx_hw.h>

Interrupt Status Register.

Referenced by XI2s_Rx_IntrHandler().

◆ XI2s_Rx_IsXI2sMaster

#define XI2s_Rx_IsXI2sMaster (   InstancePtr)

#include <xi2srx_selftest.c>

Value:
((XI2s_Rx_ReadReg((InstancePtr)->Config.BaseAddress, (XI2S_RX_CORE_CFG_OFFSET))\
& XI2S_RX_REG_CFG_MSTR_MASK) ? TRUE : FALSE)
#define XI2S_RX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2srx_hw.h:66
#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a XI2s Receiver register.
Definition: xi2srx_hw.h:185
#define XI2S_RX_REG_CFG_MSTR_MASK
Is XI2S Master mask.
Definition: xi2srx_hw.h:92

This macro returns the XI2s operating mode.

Parameters
InstancePtris a pointer to the XI2s_Rx core instance.
Returns
  • TRUE : is XI2s Master
  • FALSE : is XI2s Slave
Note
C-style signature: u8 XI2s_Rx_IsXI2sMaster(XI2s_Rx *InstancePtr)

◆ XI2S_RX_LOG_ITEM_BUFFER_SIZE

#define XI2S_RX_LOG_ITEM_BUFFER_SIZE   (256)

#include <xi2srx_debug.h>

@ name Log Item Buffer Size

◆ XI2s_Rx_Out32

#define XI2s_Rx_Out32   Xil_Out32

#include <xi2srx_hw.h>

Output Operations.

◆ XI2s_Rx_ReadReg

#define XI2s_Rx_ReadReg (   BaseAddress,
  RegOffset 
)    XI2s_Rx_In32((BaseAddress) + ((u32)RegOffset))

#include <xi2srx_hw.h>

This macro reads a value from a XI2s Receiver register.

A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.

Parameters
BaseAddressis the base address of the XI2s Receiver core instance.
RegOffsetis the register offset of the register (defined at the top of this file).
Returns
The 32-bit value of the register.
Note
C-style signature: u32 XI2s_Rx_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XI2s_Rx_Enable(), XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), XI2s_Rx_IntrHandler(), and XI2s_Rx_LatchAesChannelStatus().

◆ XI2S_RX_REG_CFG_DWDTH_MASK

#define XI2S_RX_REG_CFG_DWDTH_MASK   (1 << XI2S_RX_REG_CFG_DWDTH_SHIFT)

#include <xi2srx_hw.h>

XI2S Data Width mask.

◆ XI2S_RX_REG_CFG_DWDTH_SHIFT

#define XI2S_RX_REG_CFG_DWDTH_SHIFT   (16)

#include <xi2srx_hw.h>

XI2S Data Width bit shift.

◆ XI2S_RX_REG_CFG_MSTR_MASK

#define XI2S_RX_REG_CFG_MSTR_MASK   (1 << XI2S_RX_REG_CFG_MSTR_SHIFT)

#include <xi2srx_hw.h>

Is XI2S Master mask.

◆ XI2S_RX_REG_CFG_MSTR_SHIFT

#define XI2S_RX_REG_CFG_MSTR_SHIFT   (0)

#include <xi2srx_hw.h>

Is XI2S Master bit shift.

◆ XI2S_RX_REG_CFG_NUM_CH_MASK

#define XI2S_RX_REG_CFG_NUM_CH_MASK   (0xF << XI2S_RX_REG_CFG_NUM_CH_SHIFT)

#include <xi2srx_hw.h>

Maximum number of channels mask.

◆ XI2S_RX_REG_CFG_NUM_CH_SHIFT

#define XI2S_RX_REG_CFG_NUM_CH_SHIFT   (8)

#include <xi2srx_hw.h>

Maximum number of channels bit shift.

◆ XI2S_RX_REG_CHCTRL_CHMUX_MASK

#define XI2S_RX_REG_CHCTRL_CHMUX_MASK   (0x7 << XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)

#include <xi2srx_hw.h>

Channel MUX mask.

◆ XI2S_RX_REG_CHCTRL_CHMUX_SHIFT

#define XI2S_RX_REG_CHCTRL_CHMUX_SHIFT   (0)

#include <xi2srx_hw.h>

Channel MUX bit shift.

◆ XI2S_RX_REG_CTRL_EN_MASK

#define XI2S_RX_REG_CTRL_EN_MASK   (1 << XI2S_RX_REG_CTRL_EN_SHIFT)

#include <xi2srx_hw.h>

Module Enable mask.

Referenced by XI2s_Rx_Enable().

◆ XI2S_RX_REG_CTRL_EN_SHIFT

#define XI2S_RX_REG_CTRL_EN_SHIFT   (0)

#include <xi2srx_hw.h>

Module Enable bit shift.

◆ XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK

#define XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK   (1 << XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT)

#include <xi2srx_hw.h>

Latch AES Channel Status mask.

Referenced by XI2s_Rx_LatchAesChannelStatus().

◆ XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT

#define XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT   (16)

#include <xi2srx_hw.h>

Latch AES Channel Status bit shift.

◆ XI2S_RX_REG_TMR_SCLKDIV_MASK

#define XI2S_RX_REG_TMR_SCLKDIV_MASK   (0xF << XI2S_RX_REG_TMR_SCLKDIV_SHIFT)

#include <xi2srx_hw.h>

SClk Divider mask.

◆ XI2S_RX_REG_TMR_SCLKDIV_SHIFT

#define XI2S_RX_REG_TMR_SCLKDIV_SHIFT   (0)

#include <xi2srx_hw.h>

SClk Divider bit shift.

◆ XI2S_RX_TMR_CTRL_OFFSET

#define XI2S_RX_TMR_CTRL_OFFSET   0x20

#include <xi2srx_hw.h>

XI2S Timing Control Register.

Referenced by XI2s_Rx_SetSclkOutDiv().

◆ XI2s_Rx_WriteReg

#define XI2s_Rx_WriteReg (   BaseAddress,
  RegOffset,
  Data 
)    XI2s_Rx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))

#include <xi2srx_hw.h>

This macro writes a value to a XI2s Receiver register.

A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.

Parameters
BaseAddressis the base address of the XI2s Receiver core instance.
RegOffsetis the register offset of the register (defined at the top of this file) to be written.
Datais the 32-bit value to write into the register.
Returns
None.
Note
C-style signature: void XI2s_Rx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XI2s_Rx_ClrAesChStatRegs(), XI2s_Rx_Enable(), XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), XI2s_Rx_LatchAesChannelStatus(), XI2s_Rx_SetAesChStatus(), XI2s_Rx_SetChMux(), and XI2s_Rx_SetSclkOutDiv().

Typedef Documentation

◆ XI2s_Rx_Callback

typedef void(* XI2s_Rx_Callback) (void *CallbackRef)

#include <xi2srx.h>

Callback function data type for handling interrupt requests from the XI2s Receiver peripheral.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler is called in an interrupt context such that minimal processing should be performed.

Parameters
CallBackRefis a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.
Returns
None
Note
None

Enumeration Type Documentation

◆ XI2s_Rx_ChannelId

#include <xi2srx.h>

These constants specify different channel ID's.

Enumerator
XI2S_RX_CHID0 

Channel 0.

XI2S_RX_CHID1 

Channel 1.

XI2S_RX_CHID2 

Channel 2.

XI2S_RX_CHID3 

Channel 3.

XI2S_RX_NUM_CHANNELS 

Number of Channel ID's.

◆ XI2s_Rx_ChMuxInput

#include <xi2srx.h>

This typedef specifies the input sources of the the XI2s Receiver.

Enumerator
XI2S_RX_CHMUX_DISABLED 

Channel disabled.

XI2S_RX_CHMUX_XI2S_01 

XI2S Audio Channel 0 and 1.

XI2S_RX_CHMUX_XI2S_23 

XI2S Audio Channel 2 and 3.

XI2S_RX_CHMUX_XI2S_45 

XI2S Audio Channel 4 and 5.

XI2S_RX_CHMUX_XI2S_67 

XI2S Audio Channel 6 and 7.

XI2S_RX_CHMUX_WAVEGEN 

Wave Generator.

◆ XI2s_Rx_HandlerType

#include <xi2srx.h>

These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.

Enumerator
XI2S_RX_HANDLER_AES_BLKCMPLT 

AES Block Complete Handler.

XI2S_RX_HANDLER_AUD_OVRFLW 

Audio Overflow Detected Handler.

XI2S_RX_NUM_HANDLERS 

Number of handler types.

◆ XI2s_Rx_LogEvt

#include <xi2srx_debug.h>

These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.

Enumerator
XI2S_RX_AES_BLKCMPLT_EVT 

AES Block Complete Event.

XI2S_RX_AUD_OVERFLOW_EVT 

Audio Overflow Detected Event.

XI2S_RX_LOG_EVT_INVALID 

Invalid Log Event.

Function Documentation

◆ XI2s_Rx_CfgInitialize()

int XI2s_Rx_CfgInitialize ( XI2s_Rx InstancePtr,
XI2srx_Config CfgPtr,
UINTPTR  EffectiveAddr 
)

#include <xi2srx.c>

This function initializes the XI2s Receiver.

This function must be called prior to using the core. Initialization of the XI2s Receiver includes setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
CfgPtrpoints to the configuration structure associated with the XI2s Receiver.
EffectiveAddris the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.
Returns
  • XST_SUCCESS : if successful.
  • XST_FAILURE : if version mismatched.
Note
None.

References XI2s_Rx::Config, XI2s_Rx::IsReady, XI2s_Rx_Enable(), and XI2s_Rx_SelfTest().

Referenced by I2srx_SelfTest_Example(), and XI2s_Rx_Initialize().

◆ XI2s_Rx_ClrAesChStatRegs()

void XI2s_Rx_ClrAesChStatRegs ( XI2s_Rx InstancePtr)

#include <xi2srx.c>

This function clears the captured AES Channel Status bits.

This will clear all the 6 channel status registers.

Parameters
InstancePtris a pointer to the XI2s_Rx core instance.
Returns
None.

References XI2S_RX_AES_CHSTS0_OFFSET, XI2S_RX_AES_CHSTS1_OFFSET, XI2S_RX_AES_CHSTS2_OFFSET, XI2S_RX_AES_CHSTS3_OFFSET, XI2S_RX_AES_CHSTS4_OFFSET, XI2S_RX_AES_CHSTS5_OFFSET, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_Enable()

void XI2s_Rx_Enable ( XI2s_Rx InstancePtr,
u8  Enable 
)

#include <xi2srx.c>

This function enables/disables the XI2s Receiver.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
Enablespecifies TRUE/FALSE value to either enable or disable the XI2s Receiver.
Returns
None.

References XI2s_Rx::Config, XI2s_Rx::IsStarted, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_EN_MASK, and XI2s_Rx_WriteReg.

Referenced by XI2s_Rx_CfgInitialize().

◆ XI2s_Rx_Initialize()

int XI2s_Rx_Initialize ( XI2s_Rx InstancePtr,
u16  DeviceId 
)

#include <xi2srx.h>

Initializes a specific XI2s_Rx instance such that the driver is ready to use.

Parameters
InstancePtris a pointer to the XI2s_Rx instance to be worked on.
DeviceIdis the unique id of the device controlled by this XI2s_Rx instance. Passing in a device id associates the generic XI2s_Rx instance to a specific device, as chosen by the caller or application developer.
Returns
  • XST_SUCCESS if successful.
  • XST_DEVICE_NOT_FOUND if the device was not found in the configuration such that initialization could not be accomplished.
  • XST_INVALID_VERSION if version mismatched

References XI2s_Rx_CfgInitialize(), and XI2s_Rx_LookupConfig().

◆ XI2s_Rx_IntrDisable()

void XI2s_Rx_IntrDisable ( XI2s_Rx InstancePtr,
u32  Mask 
)

#include <xi2srx.c>

This function disables the specified interrupt of the XI2s Receiver.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
Maskis a bit mask of the interrupts to be disabled.
Returns
None.
See also
XI2s_Receiver_HW for the available interrupt masks.

References XI2s_Rx::Config, XI2S_RX_IRQCTRL_OFFSET, XI2s_Rx_ReadReg, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_IntrEnable()

void XI2s_Rx_IntrEnable ( XI2s_Rx InstancePtr,
u32  Mask 
)

#include <xi2srx.c>

This function enables the specified interrupt of the XI2s Receiver.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
Maskis a bit mask of the interrupts to be enabled.
Returns
None.
See also
XI2srx_HW for the available interrupt masks.

References XI2s_Rx::Config, XI2S_RX_IRQCTRL_OFFSET, XI2s_Rx_ReadReg, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_IntrHandler()

void XI2s_Rx_IntrHandler ( void *  InstancePtr)

#include <xi2srx.h>

This function is the interrupt handler for the XI2s Receiver driver.

This handler reads the pending interrupt from the XI2s Receiver peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Returns
None.
Note
None.

References XI2s_Rx::Config, XI2s_Rx::IsReady, XI2S_RX_INTR_AES_BLKCMPLT_MASK, XI2S_RX_IRQCTRL_OFFSET, XI2S_RX_IRQSTS_OFFSET, and XI2s_Rx_ReadReg.

◆ XI2s_Rx_LatchAesChannelStatus()

void XI2s_Rx_LatchAesChannelStatus ( XI2s_Rx InstancePtr)

#include <xi2srx.c>

This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
Returns
None.

References XI2s_Rx::Config, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_LogDisplay()

void XI2s_Rx_LogDisplay ( XI2s_Rx InstancePtr)

#include <xi2srx.h>

This function prints the contents of the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Returns
None.
Note
None.

References XI2s_Rx::Config, XI2srx_Config::DeviceId, XI2s_Rx_LogItem::Event, XI2S_RX_AES_BLKCMPLT_EVT, XI2S_RX_AUD_OVERFLOW_EVT, XI2S_RX_LOG_EVT_INVALID, and XI2s_Rx_LogRead().

◆ XI2s_Rx_LogRead()

XI2s_Rx_LogItem * XI2s_Rx_LogRead ( XI2s_Rx InstancePtr)

#include <xi2srx.h>

This function returns the next item in the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Returns
When the buffer is filled, the next log item is returned. When the buffer is empty, NULL is returned.
Note
None.

References XI2s_Rx_Log::Head, XI2s_Rx_Log::Items, XI2s_Rx::Log, and XI2s_Rx_Log::Tail.

Referenced by XI2s_Rx_LogDisplay().

◆ XI2s_Rx_LogReset()

void XI2s_Rx_LogReset ( XI2s_Rx InstancePtr)

#include <xi2srx.h>

This function clears the contents of the logging buffer.

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Returns
None.
Note
None.

References XI2s_Rx_Log::Head, XI2s_Rx_Log::IsEnabled, XI2s_Rx::Log, and XI2s_Rx_Log::Tail.

◆ XI2s_Rx_LogWrite()

void XI2s_Rx_LogWrite ( XI2s_Rx InstancePtr,
XI2s_Rx_LogEvt  Event,
u8  Data 
)

#include <xi2srx.h>

This function writes XI2s Receiver logs into the buffer.

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Eventis the log event type.
Datais the log data.
Returns
None.
Note
Log write is done only if the log is enabled.

References XI2s_Rx_LogItem::Data, XI2s_Rx_LogItem::Event, XI2s_Rx_Log::Head, XI2s_Rx_Log::IsEnabled, XI2s_Rx_Log::Items, XI2s_Rx::Log, XI2s_Rx_Log::Tail, and XI2S_RX_LOG_EVT_INVALID.

◆ XI2s_Rx_LookupConfig()

XI2srx_Config * XI2s_Rx_LookupConfig ( u16  DeviceId)

#include <xi2srx.h>

This function returns a reference to an XI2srx_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xi2srx_g.c file.

Parameters
DeviceIdis the unique core ID of the XI2s Receiver core for the lookup operation.
Returns
returns a reference to a config record in the configuration table corresponding to DeviceId, or NULL if no match is found.
Note
None.

Referenced by I2srx_SelfTest_Example(), and XI2s_Rx_Initialize().

◆ XI2s_Rx_SelfTest()

int XI2s_Rx_SelfTest ( XI2s_Rx InstancePtr)

#include <xi2srx.h>

Runs a self-test on the driver/device.

The self-test reads the version register, data width , max channels, Master or slave configuration and verifies the values

Parameters
InstancePtris a pointer to the XI2s_Rx instance.
Returns
  • XST_SUCCESS if successful i.e. if the self test passes.
  • XST_FAILURE if unsuccessful i.e. if the self test fails
Note
None.

Referenced by XI2s_Rx_CfgInitialize().

◆ XI2s_Rx_SetAesChStat()

void XI2s_Rx_SetAesChStat ( u32  I2srx_SrcBuf[],
u8  I2srx_DstBuf[] 
)

#include <xi2srx_chsts.c>

This function reads the source buffer and writes to a destination buffer.

Before calling this API user application should write 192 bits i.e. 24 bytes to the array I2srx_SrcBuf.

Parameters
I2srx_SrcBufis the source buffer which has 192 channel status bits.
I2srx_DstBufis the destination buffer to store the 24 bytes.
Returns
void.

< use of channel status block

< linear PCM identification

< audio signal Pre-emphasis

< lock indication

< sampling frequency

< channel mode

< user bits management

< use of auxiliary sample bits

< source word length

< indication of alignment level

< channel mode

< Channel number 0

< Channel number 1

< multi channel1 mode number

< digital audio reference signal

< reserved but undefined

< sampling frequency

< sampling frequency scaling flag

< reserved but undefined

< Alphanumeric channel origin data

< Alphanumeric channel destination data

< Local sample address code

< Time-of-day sample address code

< Reliability flags

< Cyclic redundancy check character

◆ XI2s_Rx_SetAesChStatus()

void XI2s_Rx_SetAesChStatus ( XI2s_Rx InstancePtr,
u8 *  AesChStatusBuf 
)

#include <xi2srx.c>

This function sets the AES Channel Status bits to insert.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
AesChStatusBufis a pointer to a buffer containing the AES channel status bits.
Returns
None.

References XI2s_Rx::Config, XI2S_RX_AES_CHSTS0_OFFSET, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_SetChMux()

int XI2s_Rx_SetChMux ( XI2s_Rx InstancePtr,
XI2s_Rx_ChannelId  ChID,
XI2s_Rx_ChMuxInput  InputSource 
)

#include <xi2srx.c>

This function sets the input source for the specified AXI-Stream channel pair.

Parameters
InstancePtris a pointer to the XI2s Receiver instance.
ChIDspecifies the AXI-Stream channel pair
  • 0 : AXI-Stream channel 0 and 1
  • 1 : AXI-Stream channel 2 and 3
  • 2 : AXI-Stream channel 4 and 5
  • 3 : AXI-Stream channel 6 and 7
InputSourcespecifies the input source
Returns
  • XST_SUCCESS : if successful.
  • XST_FAILURE : if the AXI-Stream channel pair is invalid.

References XI2s_Rx::Config, XI2S_RX_CH01_OFFSET, XI2S_RX_CHMUX_WAVEGEN, XI2S_RX_CHMUX_XI2S_01, XI2S_RX_CHMUX_XI2S_23, XI2S_RX_CHMUX_XI2S_45, XI2S_RX_CHMUX_XI2S_67, XI2S_RX_NUM_CHANNELS, and XI2s_Rx_WriteReg.

◆ XI2s_Rx_SetHandler()

int XI2s_Rx_SetHandler ( XI2s_Rx InstancePtr,
XI2s_Rx_HandlerType  HandlerType,
XI2s_Rx_Callback  FuncPtr,
void *  CallbackRef 
)

#include <xi2srx.h>

This function installs an asynchronous callback function for the given HandlerType:

HandlerType                              Callback Function
--------------------------------         ----------------------------------
(XI2S_RX_HANDLER_AES_BLKCMPLT)            AesBlkCmpltHandler
(XI2S_RX_HANDLER_AUD_OVERFLOW)            AudOverflowHandler
Parameters
InstancePtris a pointer to the XI2s_Rx core instance.
HandlerTypespecifies the type of handler.
FuncPtris a pointer to the callback function.
CallbackRefis a reference pointer passed on actual calling of the callback function.
Returns
  • XST_SUCCESS if callback function installed successfully.
  • XST_INVALID_PARAM when HandlerType is invalid.
Note
Invoking this function for a handler that already has been installed replaces it with the new handler.

References XI2s_Rx::AudOverflowHandler, XI2S_RX_HANDLER_AES_BLKCMPLT, XI2S_RX_HANDLER_AUD_OVRFLW, and XI2S_RX_NUM_HANDLERS.

◆ XI2s_Rx_SetSclkOutDiv()

u32 XI2s_Rx_SetSclkOutDiv ( XI2s_Rx InstancePtr,
u32  MClk,
u32  Fs 
)

#include <xi2srx.c>

This function calculates the SCLK Output divider value of the I2s timing generator.

Parameters
InstancePtris a pointer to the I2s Receiver instance.
MClkis the frequency of the MClk.
Fsis the sampling frequency of the system. Divider value for the SCLK generation MCLK/SCLK = SCLKOUT_DIV x 2 i.e. MCLK = 384xFs, SCLK = 48xFs (2x24bits) -> SCLKOUT_DIV = MCLK/SCLK/2 = 4 Valid values are 1 through 15.
Returns
- XST_FAILURE if SCLK Output divider is not calculated to be a positive integer.
  • XST_SUCCESS, otherwise.

References XI2s_Rx::Config, XI2srx_Config::DWidth, XI2S_RX_TMR_CTRL_OFFSET, and XI2s_Rx_WriteReg.