csi2tx
Xilinx SDK Drivers API Documentation
XCsi2Tx_Config Struct Reference

The configuration structure for CSI Controller. More...

Data Fields

u32 DeviceId
 Device Id. More...
 
UINTPTR BaseAddr
 Base address of CSI2 Rx Controller. More...
 
u32 MaxLanesPresent
 Max value of Lanes. More...
 
u32 ActiveLanes
 Number of Lanes configured. More...
 
u32 FEGenEnabled
 Frame End generation enabled. More...
 

Detailed Description

The configuration structure for CSI Controller.

This structure passes the hardware building information to the driver

Field Documentation

◆ ActiveLanes

u32 XCsi2Tx_Config::ActiveLanes

Number of Lanes configured.

Range 0 - 3

◆ BaseAddr

UINTPTR XCsi2Tx_Config::BaseAddr

Base address of CSI2 Rx Controller.

Referenced by Csi2TxSelfTestExample(), and XCsi2Tx_CfgInitialize().

◆ DeviceId

u32 XCsi2Tx_Config::DeviceId

Device Id.

◆ FEGenEnabled

u32 XCsi2Tx_Config::FEGenEnabled

Frame End generation enabled.

Referenced by XCsi2Tx_GetLineCountForVC(), XCsi2Tx_IntrHandler(), and XCsi2Tx_SetLineCountForVC().

◆ MaxLanesPresent

u32 XCsi2Tx_Config::MaxLanesPresent

Max value of Lanes.

Range 0 - 3

Referenced by XCsi2Tx_IsActiveLaneCountValid().