hwicap
Xilinx SDK Drivers API Documentation
Hwicap_v11_1

Data Structures

struct  XHwIcap_Config
 This typedef contains configuration information for the device. More...
 
struct  XHwIcap
 The XHwIcap driver instance data. More...
 

Macros

#define PCAP_CR_OFFSET   0xFFCA3008
 PCAP CR Register. More...
 
#define XHwIcap_FifoWrite(InstancePtr, Data)
 Write data to the Write FIFO. More...
 
#define XHwIcap_FifoRead(InstancePtr)   (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_RF_OFFSET))
 Read data from the Read FIFO. More...
 
#define XHwIcap_SetSizeReg(InstancePtr, Data)
 Set the number of words to be read from the Icap in the Size register. More...
 
#define XHwIcap_GetControlReg(InstancePtr)   (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_CR_OFFSET))
 Get the contents of the Control register. More...
 
#define XHwIcap_StartConfig(InstancePtr)
 Set the Control Register to initiate a configuration (write) to the device. More...
 
#define XHwIcap_StartReadBack(InstancePtr)
 Set the Control Register to initiate a ReadBack from the device. More...
 
#define XHwIcap_GetStatusReg(InstancePtr)   (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_SR_OFFSET))
 Get the contents of the status register. More...
 
#define XHwIcap_IsTransferDone(InstancePtr)   ((InstancePtr->IsTransferInProgress) ? FALSE : TRUE)
 This macro checks if the last Read/Write of the data to the Read/Write FIFO of the HwIcap device is completed. More...
 
#define XHwIcap_IsDeviceBusy(InstancePtr)
 This macro checks if the last Read/Write to the ICAP device in the FPGA is completed. More...
 
#define XHwIcap_IntrGlobalEnable(InstancePtr)
 This macro enables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the HwIcap device is enabled. More...
 
#define XHwIcap_IntrGlobalDisable(InstancePtr)
 This macro disables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the HwIcap device is disabled. More...
 
#define XHwIcap_IntrGetStatus(InstancePtr)
 This macro returns the interrupt status read from Interrupt Status Register(IPISR). More...
 
#define XHwIcap_IntrDisable(InstancePtr, IntrMask)
 This macro disables the specified interrupts in the Interrupt Enable Register. More...
 
#define XHwIcap_IntrEnable(InstancePtr, IntrMask)
 This macro enables the specified interrupts in the Interrupt Enable Register. More...
 
#define XHwIcap_IntrGetEnabled(InstancePtr)
 This macro returns the interrupt status read from Interrupt Enable Register(IIER). More...
 
#define XHwIcap_IntrClear(InstancePtr, IntrMask)
 This macro clears the specified interrupts in the Interrupt Status Register (IPISR). More...
 
#define XHwIcap_GetWrFifoVacancy(InstancePtr)   XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_WFV_OFFSET)
 This macro returns the vacancy of the Write FIFO. More...
 
#define XHwIcap_GetRdFifoOccupancy(InstancePtr)   XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_RFO_OFFSET)
 This macro returns the occupancy of the Read FIFO. More...
 
#define XHwIcap_Type1Read(Register)
 Generates a Type 1 packet header that reads back the requested Configuration register. More...
 
#define XHwIcap_Type2Read(Register)   ( XHI_TYPE_2_READ | (Register << XHI_REGISTER_SHIFT))
 Generates a Type 2 packet header that reads back the requested Configuration register. More...
 
#define XHwIcap_Type1Write(Register)
 Generates a Type 1 packet header that writes to the requested Configuration register. More...
 
#define XHwIcap_Type2Write(Register)
 Generates a Type 2 packet header that writes to the requested Configuration register. More...
 
#define XHwIcap_SetupFarV5(Top, Block, Row, ColumnAddress, MinorAddress)
 Generates a Type 1 packet header that is written to the Frame Address Register (FAR). More...
 
#define XHwIcap_ReadReg(BaseAddress, RegOffset)   XHwIcap_In32((BaseAddress) + (RegOffset))
 Read from the specified HwIcap device register. More...
 
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)   XHwIcap_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 Write to the specified HwIcap device register. More...
 

Typedefs

typedef void(* XHwIcap_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 WordCount)
 The handler data type allows the user to define a callback function to handle the asynchronous processing of the HwIcap driver. More...
 

Functions

int XHwIcap_CfgInitialize (XHwIcap *InstancePtr, XHwIcap_Config *ConfigPtr, UINTPTR EffectiveAddr)
 This function initializes a specific XHwIcap instance. More...
 
int XHwIcap_DeviceWrite (XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords)
 This function writes the given user data to the Write FIFO in both the polled mode and the interrupt mode and starts the transfer of the data to the ICAP device. More...
 
int XHwIcap_DeviceRead (XHwIcap *InstancePtr, u32 *FrameBuffer, u32 NumWords)
 This function reads the specified number of words from the ICAP device in the polled mode. More...
 
void XHwIcap_Reset (XHwIcap *InstancePtr)
 This function forces the software reset of the complete HWICAP device. More...
 
void XHwIcap_FlushFifo (XHwIcap *InstancePtr)
 This function flushes the FIFOs in the device. More...
 
void XHwIcap_Abort (XHwIcap *InstancePtr)
 This function initiates the Abort Sequence by setting the Abort bit in the control register. More...
 
XHwIcap_ConfigXHwIcap_LookupConfig (u16 DeviceId)
 Looks up the device configuration based on the unique device ID. More...
 
int XHwIcap_CommandDesync (XHwIcap *InstancePtr)
 Sends a DESYNC command to the ICAP port. More...
 
int XHwIcap_CommandCapture (XHwIcap *InstancePtr)
 Sends a CAPTURE command to the ICAP port. More...
 
u32 XHwIcap_GetConfigReg (XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
 This function returns the value of the specified configuration register. More...
 
int XHwIcap_SelfTest (XHwIcap *InstancePtr)
 Run a self-test on the driver/device. More...
 
void XHwIcap_IntrHandler (void *InstancePtr)
 The interrupt handler for HwIcap interrupts. More...
 
void XHwIcap_SetInterruptHandler (XHwIcap *InstancePtr, void *CallBackRef, XHwIcap_StatusHandler FuncPtr)
 Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More...
 
int XHwIcap_DeviceReadFrame (XHwIcap *InstancePtr, long Top, long Block, long HClkRow, long MajorFrame, long MinorFrame, u32 *FrameBuffer)
 Reads one frame from the device and puts it in memory specified by the user. More...
 
int XHwIcap_DeviceWriteFrame (XHwIcap *InstancePtr, long Top, long Block, long HClkRow, long MajorFrame, long MinorFrame, u32 *FrameData)
 Writes one frame from the specified buffer and puts it in the device (ICAP). More...
 
int XHwIcap_SetClbBits (XHwIcap *InstancePtr, long Row, long Col, const u8 Resource[][2], const u8 Value[], long NumBits)
 Sets bits contained in a Center tile specified by the CLB row and col coordinates. More...
 
int XHwIcap_GetClbBits (XHwIcap *InstancePtr, long Row, long Col, const u8 Resource[][2], u8 Value[], long NumBits)
 Gets bits contained in a Center tile specified by the CLB row and col coordinates. More...
 

Variables

XHwIcap_Config XHwIcap_ConfigTable [XPAR_XHWICAP_NUM_INSTANCES]
 The configuration table for opb_hwicap devices. More...
 
XHwIcap_Config XHwIcap_ConfigTable []
 The configuration table for opb_hwicap devices. More...
 

Configuration Type1/Type2 packet headers masks

#define XHI_TYPE_MASK   0x7
 
#define XHI_REGISTER_MASK   0x1F
 
#define XHI_OP_MASK   0x3
 
#define XHI_WORD_COUNT_MASK_TYPE_1   0x7FF
 
#define XHI_WORD_COUNT_MASK_TYPE_2   0x07FFFFFF
 
#define XHI_TYPE_SHIFT   29
 
#define XHI_REGISTER_SHIFT   13
 
#define XHI_OP_SHIFT   27
 
#define XHI_TYPE_1   1
 
#define XHI_TYPE_2   2
 
#define XHI_OP_WRITE   2
 
#define XHI_OP_READ   1
 

Frame Address Register mask(s)

#define XHI_FAR_BLOCK_MASK   0x7
 
#define XHI_FAR_TOP_BOTTOM_MASK   0x1
 
#define XHI_FAR_ROW_ADDR_MASK   0x1F
 
#define XHI_FAR_COLUMN_ADDR_MASK   0x3FF
 
#define XHI_FAR_MINOR_ADDR_MASK   0x7F
 
#define XHI_FAR_BLOCK_SHIFT   23
 
#define XHI_FAR_TOP_BOTTOM_SHIFT   22
 
#define XHI_FAR_ROW_ADDR_SHIFT   17
 
#define XHI_FAR_COLUMN_ADDR_SHIFT   7
 
#define XHI_FAR_MINOR_ADDR_SHIFT   0
 
#define XHI_FAR_CLB_BLOCK   0
 CLB/IO/CLK Block. More...
 
#define XHI_FAR_BRAM_BLOCK   1
 Block RAM interconnect. More...
 
#define XHI_FAR_CFG_CLB_BLOCK   2
 CFG CLB Block. More...
 

Register Map

Register offsets for the XHwIcap device.

#define XHI_GIER_OFFSET   0x1C
 Device Global Interrupt Enable Reg. More...
 
#define XHI_IPISR_OFFSET   0x20
 Interrupt Status Register. More...
 
#define XHI_IPIER_OFFSET   0x28
 Interrupt Enable Register. More...
 
#define XHI_WF_OFFSET   0x100
 Write FIFO. More...
 
#define XHI_RF_OFFSET   0x104
 Read FIFO. More...
 
#define XHI_SZ_OFFSET   0x108
 Size Register. More...
 
#define XHI_CR_OFFSET   0x10C
 Control Register. More...
 
#define XHI_SR_OFFSET   0x110
 Status Register. More...
 
#define XHI_WFV_OFFSET   0x114
 Write FIFO Vacancy Register. More...
 
#define XHI_RFO_OFFSET   0x118
 Read FIFO Occupancy Register. More...
 

Device Global Interrupt Enable Register (GIER) bit definitions

#define XHI_GIER_GIE_MASK   0x80000000
 Global Interrupt enable Mask. More...
 

HwIcap Device Interrupt Status/Enable Registers

Interrupt Status Register (IPISR)

This register holds the interrupt status flags for the device. These bits are toggle on write.

Interrupt Enable Register (IPIER)

This register is used to enable interrupt sources for the device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.

IPISR/IPIER registers have the same bit definitions and are only defined once.

#define XHI_IPIXR_RFULL_MASK   0x00000008
 Read FIFO Full. More...
 
#define XHI_IPIXR_WEMPTY_MASK   0x00000004
 Write FIFO Empty. More...
 
#define XHI_IPIXR_RDP_MASK   0x00000002
 Read FIFO half full. More...
 
#define XHI_IPIXR_WRP_MASK   0x00000001
 Write FIFO half full. More...
 
#define XHI_IPIXR_ALL_MASK   0x0000000F
 Mask of all interrupts. More...
 

Control Register (CR)

#define XHI_CR_SW_ABORT_MASK   0x00000010
 Abort current ICAP Read/Write. More...
 
#define XHI_CR_SW_RESET_MASK   0x00000008
 SW Reset Mask. More...
 
#define XHI_CR_FIFO_CLR_MASK   0x00000004
 FIFO Clear Mask. More...
 
#define XHI_CR_READ_MASK   0x00000002
 Read from ICAP to FIFO. More...
 
#define XHI_CR_WRITE_MASK   0x00000001
 Write from FIFO to ICAP. More...
 

Status Register (SR)

#define XHI_SR_CFGERR_N_MASK   0x00000100
 Config Error Mask. More...
 
#define XHI_SR_DALIGN_MASK   0x00000080
 Data Alignment Mask. More...
 
#define XHI_SR_RIP_MASK   0x00000040
 Read back Mask. More...
 
#define XHI_SR_IN_ABORT_N_MASK   0x00000020
 Select Map Abort Mask. More...
 
#define XHI_SR_DONE_MASK   0x00000001
 Done bit Mask. More...
 
#define XHI_SR_EOS_MASK   0x00000004
 EOS bit Mask. More...
 

Macro Definition Documentation

◆ PCAP_CR_OFFSET

#define PCAP_CR_OFFSET   0xFFCA3008

#include <xhwicap.h>

PCAP CR Register.

◆ XHI_CR_FIFO_CLR_MASK

#define XHI_CR_FIFO_CLR_MASK   0x00000004

#include <xhwicap_l.h>

FIFO Clear Mask.

Referenced by XHwIcap_FlushFifo().

◆ XHI_CR_OFFSET

#define XHI_CR_OFFSET   0x10C

#include <xhwicap_l.h>

Control Register.

Referenced by XHwIcap_Abort(), XHwIcap_DeviceWrite(), XHwIcap_FlushFifo(), and XHwIcap_Reset().

◆ XHI_CR_READ_MASK

#define XHI_CR_READ_MASK   0x00000002

#include <xhwicap_l.h>

Read from ICAP to FIFO.

◆ XHI_CR_SW_ABORT_MASK

#define XHI_CR_SW_ABORT_MASK   0x00000010

#include <xhwicap_l.h>

Abort current ICAP Read/Write.

Referenced by XHwIcap_Abort().

◆ XHI_CR_SW_RESET_MASK

#define XHI_CR_SW_RESET_MASK   0x00000008

#include <xhwicap_l.h>

SW Reset Mask.

Referenced by XHwIcap_Reset().

◆ XHI_CR_WRITE_MASK

#define XHI_CR_WRITE_MASK   0x00000001

#include <xhwicap_l.h>

Write from FIFO to ICAP.

Referenced by XHwIcap_DeviceWrite().

◆ XHI_FAR_BRAM_BLOCK

#define XHI_FAR_BRAM_BLOCK   1

#include <xhwicap_i.h>

Block RAM interconnect.

◆ XHI_FAR_CFG_CLB_BLOCK

#define XHI_FAR_CFG_CLB_BLOCK   2

#include <xhwicap_i.h>

CFG CLB Block.

◆ XHI_FAR_CLB_BLOCK

#define XHI_FAR_CLB_BLOCK   0

#include <xhwicap_i.h>

CLB/IO/CLK Block.

◆ XHI_GIER_GIE_MASK

#define XHI_GIER_GIE_MASK   0x80000000

#include <xhwicap_l.h>

Global Interrupt enable Mask.

◆ XHI_GIER_OFFSET

#define XHI_GIER_OFFSET   0x1C

#include <xhwicap_l.h>

Device Global Interrupt Enable Reg.

Referenced by XHwIcap_SelfTest().

◆ XHI_IPIER_OFFSET

#define XHI_IPIER_OFFSET   0x28

#include <xhwicap_l.h>

Interrupt Enable Register.

◆ XHI_IPISR_OFFSET

#define XHI_IPISR_OFFSET   0x20

#include <xhwicap_l.h>

Interrupt Status Register.

◆ XHI_IPIXR_ALL_MASK

#define XHI_IPIXR_ALL_MASK   0x0000000F

#include <xhwicap_l.h>

Mask of all interrupts.

Referenced by XHwIcap_SelfTest().

◆ XHI_IPIXR_RDP_MASK

#define XHI_IPIXR_RDP_MASK   0x00000002

#include <xhwicap_l.h>

Read FIFO half full.

Referenced by XHwIcap_SelfTest().

◆ XHI_IPIXR_RFULL_MASK

#define XHI_IPIXR_RFULL_MASK   0x00000008

#include <xhwicap_l.h>

Read FIFO Full.

◆ XHI_IPIXR_WEMPTY_MASK

#define XHI_IPIXR_WEMPTY_MASK   0x00000004

#include <xhwicap_l.h>

Write FIFO Empty.

Referenced by XHwIcap_SelfTest().

◆ XHI_IPIXR_WRP_MASK

#define XHI_IPIXR_WRP_MASK   0x00000001

#include <xhwicap_l.h>

Write FIFO half full.

Referenced by XHwIcap_IntrHandler().

◆ XHI_RF_OFFSET

#define XHI_RF_OFFSET   0x104

#include <xhwicap_l.h>

Read FIFO.

◆ XHI_RFO_OFFSET

#define XHI_RFO_OFFSET   0x118

#include <xhwicap_l.h>

Read FIFO Occupancy Register.

◆ XHI_SR_CFGERR_N_MASK

#define XHI_SR_CFGERR_N_MASK   0x00000100

#include <xhwicap_l.h>

Config Error Mask.

◆ XHI_SR_DALIGN_MASK

#define XHI_SR_DALIGN_MASK   0x00000080

#include <xhwicap_l.h>

Data Alignment Mask.

◆ XHI_SR_DONE_MASK

#define XHI_SR_DONE_MASK   0x00000001

#include <xhwicap_l.h>

Done bit Mask.

◆ XHI_SR_EOS_MASK

#define XHI_SR_EOS_MASK   0x00000004

#include <xhwicap_l.h>

EOS bit Mask.

◆ XHI_SR_IN_ABORT_N_MASK

#define XHI_SR_IN_ABORT_N_MASK   0x00000020

#include <xhwicap_l.h>

Select Map Abort Mask.

◆ XHI_SR_OFFSET

#define XHI_SR_OFFSET   0x110

#include <xhwicap_l.h>

Status Register.

◆ XHI_SR_RIP_MASK

#define XHI_SR_RIP_MASK   0x00000040

#include <xhwicap_l.h>

Read back Mask.

◆ XHI_SZ_OFFSET

#define XHI_SZ_OFFSET   0x108

#include <xhwicap_l.h>

Size Register.

◆ XHI_WF_OFFSET

#define XHI_WF_OFFSET   0x100

#include <xhwicap_l.h>

Write FIFO.

◆ XHI_WFV_OFFSET

#define XHI_WFV_OFFSET   0x114

#include <xhwicap_l.h>

Write FIFO Vacancy Register.

◆ XHwIcap_FifoRead

#define XHwIcap_FifoRead (   InstancePtr)    (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_RF_OFFSET))

#include <xhwicap.h>

Read data from the Read FIFO.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
The 32-bit Data read from the FIFO.
Note
C-style Signature: u32 XHwIcap_FifoRead(XHwIcap *InstancePtr);

◆ XHwIcap_FifoWrite

#define XHwIcap_FifoWrite (   InstancePtr,
  Data 
)

#include <xhwicap.h>

Value:
(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress), \
XHI_WF_OFFSET, (Data)))
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_WF_OFFSET
Write FIFO.
Definition: xhwicap_l.h:92

Write data to the Write FIFO.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Datais the 32-bit value to be written to the FIFO.
Returns
None.
Note
C-style Signature: void XHwIcap_FifoWrite(XHwIcap *InstancePtr, u32 Data);

Referenced by XHwIcap_DeviceWrite(), and XHwIcap_IntrHandler().

◆ XHwIcap_GetControlReg

#define XHwIcap_GetControlReg (   InstancePtr)    (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_CR_OFFSET))

#include <xhwicap.h>

Get the contents of the Control register.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
A 32-bit value representing the contents of the Control register.
Note
u32 XHwIcap_GetControlReg(XHwIcap *InstancePtr);

◆ XHwIcap_GetRdFifoOccupancy

#define XHwIcap_GetRdFifoOccupancy (   InstancePtr)    XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_RFO_OFFSET)

#include <xhwicap.h>

This macro returns the occupancy of the Read FIFO.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
The contents read from the Read FIFO Occupancy Register.
Note
C-Style signature: u32 XHwIcap_GetRdFifoOccupancy(InstancePtr)

Referenced by XHwIcap_DeviceRead().

◆ XHwIcap_GetStatusReg

#define XHwIcap_GetStatusReg (   InstancePtr)    (XHwIcap_ReadReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_SR_OFFSET))

#include <xhwicap.h>

Get the contents of the status register.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
A 32-bit value representing the contents of the status register.
Note
u32 XHwIcap_GetStatusReg(XHwIcap *InstancePtr);

◆ XHwIcap_GetWrFifoVacancy

#define XHwIcap_GetWrFifoVacancy (   InstancePtr)    XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, XHI_WFV_OFFSET)

#include <xhwicap.h>

This macro returns the vacancy of the Write FIFO.

This indicates the number of words that can be written to the Write FIFO before it becomes full.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
The contents read from the Write FIFO Vacancy Register.
Note
C-Style signature: u32 XHwIcap_GetWrFifoVacancy(InstancePtr)

Referenced by XHwIcap_DeviceWrite(), and XHwIcap_IntrHandler().

◆ XHwIcap_IntrClear

#define XHwIcap_IntrClear (   InstancePtr,
  IntrMask 
)

#include <xhwicap.h>

Value:
XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, \
XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
#define XHwIcap_ReadReg(BaseAddress, RegOffset)
Read from the specified HwIcap device register.
Definition: xhwicap_l.h:185
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_IPIXR_ALL_MASK
Mask of all interrupts.
Definition: xhwicap_l.h:132
#define XHI_IPISR_OFFSET
Interrupt Status Register.
Definition: xhwicap_l.h:90

This macro clears the specified interrupts in the Interrupt Status Register (IPISR).

Parameters
InstancePtris a pointer to the HwIcap instance.
IntrMaskcontains the interrupts to be cleared.
Returns
None.
Note
Signature: void XHwIcap_DisableIntr(XHwIcap *InstancePtr, u32 IntrMask)

Referenced by XHwIcap_DeviceWrite(), and XHwIcap_IntrHandler().

◆ XHwIcap_IntrDisable

#define XHwIcap_IntrDisable (   InstancePtr,
  IntrMask 
)

#include <xhwicap.h>

Value:
XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, \
XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
XHI_IPIER_OFFSET) & (~ (IntrMask & XHI_IPIXR_ALL_MASK)));\
(InstancePtr)->IsPolled = TRUE;
#define XHwIcap_ReadReg(BaseAddress, RegOffset)
Read from the specified HwIcap device register.
Definition: xhwicap_l.h:185
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_IPIXR_ALL_MASK
Mask of all interrupts.
Definition: xhwicap_l.h:132
#define XHI_IPIER_OFFSET
Interrupt Enable Register.
Definition: xhwicap_l.h:91

This macro disables the specified interrupts in the Interrupt Enable Register.

It is non-destructive in that the register is read and only the interrupts specified is changed.

Parameters
InstancePtris a pointer to the HwIcap instance.
IntrMaskis the bit-mask of the interrupts to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XHI_IPIXR_*_MASK bits defined in xhwicap_l.h.
Returns
None.
Note
Signature: void XHwIcap_IntrDisable(XHwIcap *InstancePtr, u32 IntrMask)

Referenced by XHwIcap_SelfTest().

◆ XHwIcap_IntrEnable

#define XHwIcap_IntrEnable (   InstancePtr,
  IntrMask 
)

#include <xhwicap.h>

Value:
XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, \
(XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
XHI_IPIER_OFFSET) | ((IntrMask) & XHI_IPIXR_ALL_MASK))); \
(InstancePtr)->IsPolled = FALSE;
#define XHwIcap_ReadReg(BaseAddress, RegOffset)
Read from the specified HwIcap device register.
Definition: xhwicap_l.h:185
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_IPIXR_ALL_MASK
Mask of all interrupts.
Definition: xhwicap_l.h:132
#define XHI_IPIER_OFFSET
Interrupt Enable Register.
Definition: xhwicap_l.h:91

This macro enables the specified interrupts in the Interrupt Enable Register.

It is non-destructive in that the register is read and only the interrupts specified is changed.

Parameters
InstancePtris a pointer to the HwIcap instance.
IntrMaskis the bit-mask of the interrupts to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XHI_IPIXR_*_MASK bits defined in xhwicap_l.h.
Returns
None.
Note
Signature: void XHwIcap_IntrEnable(XHwIcap *InstancePtr, u32 IntrMask)

Referenced by XHwIcap_SelfTest().

◆ XHwIcap_IntrGetEnabled

#define XHwIcap_IntrGetEnabled (   InstancePtr)

#include <xhwicap.h>

Value:
XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
#define XHwIcap_ReadReg(BaseAddress, RegOffset)
Read from the specified HwIcap device register.
Definition: xhwicap_l.h:185
#define XHI_IPIER_OFFSET
Interrupt Enable Register.
Definition: xhwicap_l.h:91

This macro returns the interrupt status read from Interrupt Enable Register(IIER).

Use the XHI_IPIXR_* constants defined in xhwicap_l.h to interpret the returned value.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
The contents read from the Interrupt Enable Register.
Note
C-Style signature: u32 XHwIcap_IntrGetEnabled(InstancePtr)

Referenced by XHwIcap_SelfTest().

◆ XHwIcap_IntrGetStatus

#define XHwIcap_IntrGetStatus (   InstancePtr)

#include <xhwicap.h>

Value:
XHwIcap_ReadReg((InstancePtr)->HwIcapConfig.BaseAddress, \
#define XHwIcap_ReadReg(BaseAddress, RegOffset)
Read from the specified HwIcap device register.
Definition: xhwicap_l.h:185
#define XHI_IPISR_OFFSET
Interrupt Status Register.
Definition: xhwicap_l.h:90

This macro returns the interrupt status read from Interrupt Status Register(IPISR).

Use the XHI_IPIXR_* constants defined in xhwicap_l.h to interpret the returned value.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
The contents read from the Interrupt Status Register.
Note
C-Style signature: u32 XHwIcap_IntrGetStatus(InstancePtr)

Referenced by XHwIcap_DeviceWrite(), and XHwIcap_IntrHandler().

◆ XHwIcap_IntrGlobalDisable

#define XHwIcap_IntrGlobalDisable (   InstancePtr)

#include <xhwicap.h>

Value:
XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, \
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_GIER_OFFSET
Device Global Interrupt Enable Reg.
Definition: xhwicap_l.h:89

This macro disables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the HwIcap device is disabled.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
None.
Note
C-Style signature: void XHwIcap_IntrGlobalDisable(InstancePtr)

Referenced by XHwIcap_DeviceWrite(), XHwIcap_IntrHandler(), and XHwIcap_SelfTest().

◆ XHwIcap_IntrGlobalEnable

#define XHwIcap_IntrGlobalEnable (   InstancePtr)

#include <xhwicap.h>

Value:
XHwIcap_WriteReg((InstancePtr)->HwIcapConfig.BaseAddress, \
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_GIER_GIE_MASK
Global Interrupt enable Mask.
Definition: xhwicap_l.h:107
#define XHI_GIER_OFFSET
Device Global Interrupt Enable Reg.
Definition: xhwicap_l.h:89

This macro enables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the HwIcap device is enabled.

Interrupts enabled using XHwIcap_IntrEnable() will not occur until the global interrupt enable bit is set by using this macro.

Parameters
InstancePtris a pointer to the HwIcap instance.
Returns
None.
Note
C-Style signature: void XHwIcap_IntrGlobalEnable(InstancePtr)

Referenced by XHwIcap_DeviceWrite().

◆ XHwIcap_IsDeviceBusy

#define XHwIcap_IsDeviceBusy (   InstancePtr)

#include <xhwicap.h>

Value:
FALSE : TRUE)
#define XHI_SR_DONE_MASK
Done bit Mask.
Definition: xhwicap_l.h:157
#define XHwIcap_GetStatusReg(InstancePtr)
Get the contents of the status register.
Definition: xhwicap.h:415

This macro checks if the last Read/Write to the ICAP device in the FPGA is completed.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
  • TRUE if the last Read/Write(Config) to the ICAP is NOT completed.
  • FALSE if the Read/Write(Config) to the ICAP is completed..
Note
C-Style signature: int XHwIcap_IsDeviceBusy(XHwIcap *InstancePtr);

Referenced by XHwIcap_DeviceRead(), and XHwIcap_DeviceWrite().

◆ XHwIcap_IsTransferDone

#define XHwIcap_IsTransferDone (   InstancePtr)    ((InstancePtr->IsTransferInProgress) ? FALSE : TRUE)

#include <xhwicap.h>

This macro checks if the last Read/Write of the data to the Read/Write FIFO of the HwIcap device is completed.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
  • TRUE if the Read/Write to the FIFO's is completed.
  • FALSE if the Read/Write to the FIFO's is NOT completed..
Note
C-Style signature: int XHwIcap_IsTransferDone(XHwIcap *InstancePtr);

Referenced by XHwIcap_DeviceRead(), and XHwIcap_DeviceWrite().

◆ XHwIcap_ReadReg

#define XHwIcap_ReadReg (   BaseAddress,
  RegOffset 
)    XHwIcap_In32((BaseAddress) + (RegOffset))

#include <xhwicap_l.h>

Read from the specified HwIcap device register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to select the specific register.
Returns
The value read from the register.
Note
C-Style signature: u32 XHwIcap_ReadReg(u32 BaseAddress, u32 RegOffset);

Referenced by XHwIcap_Abort(), XHwIcap_DeviceWrite(), XHwIcap_FlushFifo(), XHwIcap_Reset(), and XHwIcap_SelfTest().

◆ XHwIcap_SetSizeReg

#define XHwIcap_SetSizeReg (   InstancePtr,
  Data 
)

#include <xhwicap.h>

Value:
(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress), \
XHI_SZ_OFFSET, (Data)))
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHI_SZ_OFFSET
Size Register.
Definition: xhwicap_l.h:94

Set the number of words to be read from the Icap in the Size register.

The Size Register holds the number of 32 bit words to transfer from the the Icap to the Read FIFO of the HwIcap device.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Datais the size in words.
Returns
None.
Note
C-style Signature: void XHwIcap_SetSizeReg(XHwIcap *InstancePtr, u32 Data);

Referenced by XHwIcap_DeviceRead().

◆ XHwIcap_SetupFarV5

#define XHwIcap_SetupFarV5 (   Top,
  Block,
  Row,
  ColumnAddress,
  MinorAddress 
)

#include <xhwicap_i.h>

Value:
(Block << XHI_FAR_BLOCK_SHIFT) | \
((Top << XHI_FAR_TOP_BOTTOM_SHIFT) | \
(Row << XHI_FAR_ROW_ADDR_SHIFT) | \
(ColumnAddress << XHI_FAR_COLUMN_ADDR_SHIFT) | \
(MinorAddress << XHI_FAR_MINOR_ADDR_SHIFT))

Generates a Type 1 packet header that is written to the Frame Address Register (FAR).

Parameters
Block- Address Block Type (CLB or BRAM address space)
Top- top (0) or bottom (1) half of device
Row- Row Address
ColumnAddress- CLB or BRAM column
MinorAddress- Frame within a column
Returns
Type 1 packet header to write the FAR
Note
We are retaining this Macro for Backwards compatiblity Use the XHwIcap_SetupFar macro.

◆ XHwIcap_StartConfig

#define XHwIcap_StartConfig (   InstancePtr)

#include <xhwicap.h>

Value:
(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress), XHI_CR_OFFSET, \
(XHwIcap_GetControlReg(InstancePtr) & \
#define XHI_CR_WRITE_MASK
Write from FIFO to ICAP.
Definition: xhwicap_l.h:144
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHwIcap_GetControlReg(InstancePtr)
Get the contents of the Control register.
Definition: xhwicap.h:361
#define XHI_CR_OFFSET
Control Register.
Definition: xhwicap_l.h:95
#define XHI_CR_READ_MASK
Read from ICAP to FIFO.
Definition: xhwicap_l.h:143

Set the Control Register to initiate a configuration (write) to the device.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
C-style Signature: void XHwIcap_StartConfig(XHwIcap *InstancePtr);

Referenced by XHwIcap_DeviceWrite(), and XHwIcap_IntrHandler().

◆ XHwIcap_StartReadBack

#define XHwIcap_StartReadBack (   InstancePtr)

#include <xhwicap.h>

Value:
(XHwIcap_WriteReg(((InstancePtr)->HwIcapConfig.BaseAddress) , XHI_CR_OFFSET, \
(XHwIcap_GetControlReg(InstancePtr) & \
#define XHI_CR_WRITE_MASK
Write from FIFO to ICAP.
Definition: xhwicap_l.h:144
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)
Write to the specified HwIcap device register.
Definition: xhwicap_l.h:204
#define XHwIcap_GetControlReg(InstancePtr)
Get the contents of the Control register.
Definition: xhwicap.h:361
#define XHI_CR_OFFSET
Control Register.
Definition: xhwicap_l.h:95
#define XHI_CR_READ_MASK
Read from ICAP to FIFO.
Definition: xhwicap_l.h:143

Set the Control Register to initiate a ReadBack from the device.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
C-style Signature: void XHwIcap_StartReadBack(XHwIcap *InstancePtr);

Referenced by XHwIcap_DeviceRead().

◆ XHwIcap_Type1Read

#define XHwIcap_Type1Read (   Register)

#include <xhwicap_i.h>

Value:
( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
(XHI_OP_READ << XHI_OP_SHIFT) )

Generates a Type 1 packet header that reads back the requested Configuration register.

Parameters
Registeris the address of the register to be read back.
Returns
Type 1 packet header to read the specified register
Note
None.

◆ XHwIcap_Type1Write

#define XHwIcap_Type1Write (   Register)

#include <xhwicap_i.h>

Value:
( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
(XHI_OP_WRITE << XHI_OP_SHIFT) )

Generates a Type 1 packet header that writes to the requested Configuration register.

Parameters
Registeris the address of the register to be written to.
Returns
Type 1 packet header to write the specified register
Note
None.

◆ XHwIcap_Type2Read

#define XHwIcap_Type2Read (   Register)    ( XHI_TYPE_2_READ | (Register << XHI_REGISTER_SHIFT))

#include <xhwicap_i.h>

Generates a Type 2 packet header that reads back the requested Configuration register.

Parameters
Registeris the address of the register to be read back.
Returns
Type 1 packet header to read the specified register
Note
None.

◆ XHwIcap_Type2Write

#define XHwIcap_Type2Write (   Register)

#include <xhwicap_i.h>

Value:
( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
(XHI_OP_WRITE << XHI_OP_SHIFT) )

Generates a Type 2 packet header that writes to the requested Configuration register.

Parameters
Registeris the address of the register to be written to.
Returns
Type 1 packet header to write the specified register
Note
None.

◆ XHwIcap_WriteReg

#define XHwIcap_WriteReg (   BaseAddress,
  RegOffset,
  RegisterValue 
)    XHwIcap_Out32((BaseAddress) + (RegOffset), (RegisterValue))

#include <xhwicap_l.h>

Write to the specified HwIcap device register.

Parameters
BaseAddresscontains the base address of the device.
RegOffsetcontains the offset from the 1st register of the device to select the specific register.
RegisterValueis the value to be written to the register.
Returns
None.
Note
C-Style signature: void XHwIcap_WriteReg(u32 BaseAddress, u32 RegOffset, u32 RegisterValue);

Referenced by XHwIcap_Abort(), XHwIcap_FlushFifo(), XHwIcap_Reset(), and XHwIcap_SelfTest().

Typedef Documentation

◆ XHwIcap_StatusHandler

typedef void(* XHwIcap_StatusHandler) (void *CallBackRef, u32 StatusEvent, u32 WordCount)

#include <xhwicap.h>

The handler data type allows the user to define a callback function to handle the asynchronous processing of the HwIcap driver.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context such that minimal processing should be performed.

Parameters
CallBackRefis a callback reference passed in by the application layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is unimportant to the driver component, so it is a void pointer.
StatusEventindicates one or more status events that occurred. See the XHwIcap_SetInterruptHandler for details on the status events that can be passed in the callback.
WordCountindicates how many words of data were successfully transferred. This may be less than the number of words requested if there was an error.

Function Documentation

◆ XHwIcap_Abort()

void XHwIcap_Abort ( XHwIcap InstancePtr)

#include <xhwicap.c>

This function initiates the Abort Sequence by setting the Abort bit in the control register.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
None.

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap::IsReady, XHI_CR_OFFSET, XHI_CR_SW_ABORT_MASK, XHwIcap_ReadReg, and XHwIcap_WriteReg.

◆ XHwIcap_CfgInitialize()

int XHwIcap_CfgInitialize ( XHwIcap InstancePtr,
XHwIcap_Config ConfigPtr,
UINTPTR  EffectiveAddr 
)

#include <xhwicap.c>

This function initializes a specific XHwIcap instance.

The IDCODE is read from the FPGA and based on the IDCODE the information about the resources in the FPGA is filled in the instance structure.

The HwIcap device will be in put in a reset state before exiting this function.

Parameters
InstancePtris a pointer to the XHwIcap instance.
ConfigPtrpoints to the XHwIcap device configuration structure.
EffectiveAddris the device base address in the virtual memory address space. If the address translation is not used then the physical address is passed. Unexpected errors may occur if the address mapping is changed after this function is invoked.
Returns
XST_SUCCESS else XST_FAILURE
Note
None.

Set IcapWidth

Set IsLiteMode

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap::IsPolled, XHwIcap::IsReady, XHwIcap::IsTransferInProgress, and XHwIcap::StatusHandler.

Referenced by HwIcapIntrExample(), HwIcapReadConfigRegExample(), and HwIcapTestAppExample().

◆ XHwIcap_CommandCapture()

int XHwIcap_CommandCapture ( XHwIcap InstancePtr)

#include <xhwicap.h>

Sends a CAPTURE command to the ICAP port.

This command captures all of the flip flop states so they will be available during readback. One can use this command instead of enabling the CAPTURE block in the design.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
XST_SUCCESS or XST_FAILURE
Note
None.

◆ XHwIcap_CommandDesync()

int XHwIcap_CommandDesync ( XHwIcap InstancePtr)

#include <xhwicap.h>

Sends a DESYNC command to the ICAP port.

Parameters
InstancePtr- a pointer to the XHwIcap instance to be worked on
Returns
XST_SUCCESS else XST_FAILURE
Note
None.

◆ XHwIcap_DeviceRead()

int XHwIcap_DeviceRead ( XHwIcap InstancePtr,
u32 *  FrameBuffer,
u32  NumWords 
)

#include <xhwicap.c>

This function reads the specified number of words from the ICAP device in the polled mode.

Interrupt mode is not supported in reading data from the ICAP device.

Parameters
InstancePtris a pointer to the XHwIcap instance.
FrameBufferis a pointer to the memory where the frame read from the ICAP device is stored.
NumWordsis the number of words (16 bit for S6 and 32 bit for all other devices) to write to the ICAP device.
Returns
  • XST_SUCCESS if the specified number of words have been read from the ICAP device
  • XST_FAILURE if the device is busy with the last Read/Write or if the requested number of words have not been read from the ICAP device, or there is a timeout.
Note
This is a blocking function.

References XHwIcap::HwIcapConfig, XHwIcap_Config::IcapWidth, XHwIcap::IsReady, XHwIcap::IsTransferInProgress, XHwIcap::RemainingWords, XHwIcap::RequestedWords, XHwIcap_GetRdFifoOccupancy, XHwIcap_IsDeviceBusy, XHwIcap_IsTransferDone, XHwIcap_SetSizeReg, and XHwIcap_StartReadBack.

◆ XHwIcap_DeviceReadFrame()

int XHwIcap_DeviceReadFrame ( XHwIcap InstancePtr,
long  Top,
long  Block,
long  HClkRow,
long  MajorFrame,
long  MinorFrame,
u32 *  FrameBuffer 
)

#include <xhwicap.h>

Reads one frame from the device and puts it in memory specified by the user.

Parameters
InstancePtr- a pointer to the XHwIcap instance to be worked on.
Top- top (0) or bottom (1) half of device
Block- Block Address (XHI_FAR_CLB_BLOCK, XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
HClkRow- selects the HClk Row
MajorFrame- selects the column
MinorFrame- selects frame inside column
FrameBufferis a pointer to the memory where the frame read from the device is stored
Returns
XST_SUCCESS else XST_FAILURE.
Note
This is a blocking call.

◆ XHwIcap_DeviceWrite()

int XHwIcap_DeviceWrite ( XHwIcap InstancePtr,
u32 *  FrameBuffer,
u32  NumWords 
)

#include <xhwicap.c>

This function writes the given user data to the Write FIFO in both the polled mode and the interrupt mode and starts the transfer of the data to the ICAP device.

In the polled mode, this function will write the specified number of words into the FIFO before returning.

In the interrupt mode, this function will write the words upto the size of the Write FIFO and starts the transfer, then subsequent transfer of the data is performed by the interrupt service routine until the entire buffer has been transferred. The status callback function is called when the entire buffer has been sent. In order to use interrupts, it is necessary for the user to connect the driver interrupt handler, XHwIcap_IntrHandler(), to the interrupt system of the application and enable the interrupts associated with the Write FIFO. The user has to enable the interrupts each time this function is called using the XHwIcap_IntrEnable macro.

Parameters
InstancePtris a pointer to the XHwIcap instance.
FrameBufferis a pointer to the data to be written to the ICAP device.
NumWordsis the number of words (16 bit for S6 and 32 bit for all other devices)to write to the ICAP device.
Returns
XST_SUCCESS or XST_FAILURE
Note
This function is a blocking for the polled mode of operation and is non-blocking for the interrupt mode of operation. Use the function XHwIcap_DeviceWriteFrame for writing a frame of data to the ICAP device.

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap_Config::IcapWidth, XHwIcap::IsPolled, XHwIcap::IsReady, XHwIcap::IsTransferInProgress, XHwIcap::RemainingWords, XHwIcap::RequestedWords, XHI_CR_OFFSET, XHI_CR_WRITE_MASK, XHwIcap_FifoWrite, XHwIcap_GetWrFifoVacancy, XHwIcap_IntrClear, XHwIcap_IntrGetStatus, XHwIcap_IntrGlobalDisable, XHwIcap_IntrGlobalEnable, XHwIcap_IsDeviceBusy, XHwIcap_IsTransferDone, XHwIcap_ReadReg, and XHwIcap_StartConfig.

◆ XHwIcap_DeviceWriteFrame()

int XHwIcap_DeviceWriteFrame ( XHwIcap InstancePtr,
long  Top,
long  Block,
long  HClkRow,
long  MajorFrame,
long  MinorFrame,
u32 *  FrameData 
)

#include <xhwicap.h>

Writes one frame from the specified buffer and puts it in the device (ICAP).

Parameters
InstancePtris a pointer to the XHwIcap instance.
Top- top (0) or bottom (1) half of device
Block- Block Address (XHI_FAR_CLB_BLOCK, XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
HClkRow- selects the HClk Row
MajorFrame- selects the column
MinorFrame- selects frame inside column
FrameDatais a pointer to the frame that is to be written to the device.
Returns
XST_SUCCESS else XST_FAILURE.
Note
This is a blocking function. This function is used in conjunction with the function XHwIcap_DeviceReadFrame. This function is used to write back the frame of data read using the XHwIcap_DeviceReadFrame.

◆ XHwIcap_FlushFifo()

void XHwIcap_FlushFifo ( XHwIcap InstancePtr)

#include <xhwicap.c>

This function flushes the FIFOs in the device.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
None.

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap::IsReady, XHI_CR_FIFO_CLR_MASK, XHI_CR_OFFSET, XHwIcap_ReadReg, and XHwIcap_WriteReg.

◆ XHwIcap_GetClbBits()

int XHwIcap_GetClbBits ( XHwIcap InstancePtr,
long  Row,
long  Col,
const u8  Resource[][2],
u8  Value[],
long  NumBits 
)

#include <xhwicap.h>

Gets bits contained in a Center tile specified by the CLB row and col coordinates.

The coordinate system lables the upper left CLB as (1,1).

Parameters
InstancePtris a pointer to the XHwIcap instance.
Rowis the CLB row. (1,1) is the upper left CLB.
Colis the CLB col. (1,1) is the upper left CLB.
Resourceis the Target bits (first dimension length will be the number of bits to set and must match the numBits parameter) (second dimension contains two value – one for minor row and one for col information from within the Center tile targetted by the above row and col coords).
Valueis the values to set each of the targets bits to. The size of this array must be euqal to NumBits.
NumBitsis the number of Bits to change in this method.
Returns
XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
Note
The source code for this function is not included. This function is delivered as .o file. Libgen uses the appropriate .o file for the target processor.

◆ XHwIcap_GetConfigReg()

u32 XHwIcap_GetConfigReg ( XHwIcap InstancePtr,
u32  ConfigReg,
u32 *  RegData 
)

#include <xhwicap.h>

This function returns the value of the specified configuration register.

Parameters
InstancePtris a pointer to the XHwIcap instance.
ConfigRegis a constant which represents the configuration register value to be returned. Constants specified in xhwicap_i.h. Examples: XHI_IDCODE, XHI_FLR.
RegDatais the value of the specified configuration register.
Returns
XST_SUCCESS or XST_FAILURE
Note
This is a blocking call.

Referenced by HwIcapTestAppExample().

◆ XHwIcap_IntrHandler()

void XHwIcap_IntrHandler ( void *  InstancePtr)

#include <xhwicap.h>

The interrupt handler for HwIcap interrupts.

This function must be connected by the user to an interrupt source.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
The interrupts are being used only while writing data to the ICAP device. The reading of the data from the ICAP device is done in polled mode. In a worst case scenario the interrupt handler can be busy writing large amount of data to the Write FIFO.

References XHwIcap::IsTransferInProgress, XHwIcap::RemainingWords, XHwIcap::RequestedWords, XHwIcap::StatusHandler, XHwIcap::StatusRef, XHI_IPIXR_WRP_MASK, XHwIcap_FifoWrite, XHwIcap_GetWrFifoVacancy, XHwIcap_IntrClear, XHwIcap_IntrGetStatus, XHwIcap_IntrGlobalDisable, and XHwIcap_StartConfig.

◆ XHwIcap_LookupConfig()

XHwIcap_Config * XHwIcap_LookupConfig ( u16  DeviceId)

#include <xhwicap.h>

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters
DeviceIdcontains the ID of the device for which the device configuration pointer is to be returned.
Returns
  • A pointer to the configuration found.
  • NULL if the specified device ID was not found.
Note
None.

Referenced by HwIcapIntrExample(), HwIcapReadConfigRegExample(), and HwIcapTestAppExample().

◆ XHwIcap_Reset()

void XHwIcap_Reset ( XHwIcap InstancePtr)

#include <xhwicap.c>

This function forces the software reset of the complete HWICAP device.

All the registers will return to the default value and the FIFO is also flushed as a part of this software reset.

Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
None.
Note
None.

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap::IsReady, XHI_CR_OFFSET, XHI_CR_SW_RESET_MASK, XHwIcap_ReadReg, and XHwIcap_WriteReg.

◆ XHwIcap_SelfTest()

int XHwIcap_SelfTest ( XHwIcap InstancePtr)

#include <xhwicap.h>

Run a self-test on the driver/device.

The test

  • Writes to the Interrupt Enable Register and reads it back for comparison.
Parameters
InstancePtris a pointer to the XHwIcap instance.
Returns
  • XST_SUCCESS if the value read from the register is the same as the value written.
  • XST_FAILURE otherwise
Note
None.

References XHwIcap_Config::BaseAddress, XHwIcap::HwIcapConfig, XHwIcap::IsReady, XHI_GIER_OFFSET, XHI_IPIXR_ALL_MASK, XHI_IPIXR_RDP_MASK, XHI_IPIXR_WEMPTY_MASK, XHwIcap_IntrDisable, XHwIcap_IntrEnable, XHwIcap_IntrGetEnabled, XHwIcap_IntrGlobalDisable, XHwIcap_ReadReg, and XHwIcap_WriteReg.

Referenced by HwIcapIntrExample(), HwIcapReadConfigRegExample(), and HwIcapTestAppExample().

◆ XHwIcap_SetClbBits()

int XHwIcap_SetClbBits ( XHwIcap InstancePtr,
long  Row,
long  Col,
const u8  Resource[][2],
const u8  Value[],
long  NumBits 
)

#include <xhwicap.h>

Sets bits contained in a Center tile specified by the CLB row and col coordinates.

The coordinate system lables the upper left CLB as (1,1).

Parameters
InstancePtris a pointer to XHwIcap instance to be worked on
Rowis the CLB row. (1,1) is the upper left CLB.
Colis the CLB col. (1,1) is the upper left CLB.
Resourceis the Target bits (first dimension length will be the number of bits to set and must match the numBits parameter) (second dimension contains two value – one for minor row and one for col information from within the Center tile targetted by the above row and col coords).
Valueis the values to set each of the targets bits to. The size of this array must be euqal to NumBits.
NumBitsis the number of Bits to change in this method.
Returns
XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
Note
The source code for this function is not included. This function is delivered as .o file. Libgen uses the appropriate .o file for the target processor.

◆ XHwIcap_SetInterruptHandler()

void XHwIcap_SetInterruptHandler ( XHwIcap InstancePtr,
void *  CallBackRef,
XHwIcap_StatusHandler  FuncPtr 
)

#include <xhwicap.h>

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed such as transferring data to a thread context. One of the following status events is passed to the status handler.

 
Parameters
InstancePtris a pointer to the XHwIcap instance.
CallBackRefis the upper layer callback reference passed back when the callback function is invoked.
FuncPtris the pointer to the callback function.
Returns
None.
Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XHwIcap::IsReady, XHwIcap::StatusHandler, and XHwIcap::StatusRef.

Variable Documentation

◆ XHwIcap_ConfigTable [1/2]

XHwIcap_Config XHwIcap_ConfigTable[]

#include <xhwicap_sinit.c>

The configuration table for opb_hwicap devices.

◆ XHwIcap_ConfigTable [2/2]

XHwIcap_Config XHwIcap_ConfigTable[XPAR_XHWICAP_NUM_INSTANCES]

#include <xhwicap_g.c>

Initial value:
=
{
{
XPAR_HWICAP_0_DEVICE_ID,
XPAR_HWICAP_0_BASEADDR,
},
}

The configuration table for opb_hwicap devices.