dphy
Xilinx SDK Drivers API Documentation
XDphy_Config Struct Reference

The configuration structure for DPHY. More...

Data Fields

u32 DeviceId
 Device Id. More...
 
UINTPTR BaseAddr
 Base address of DPHY. More...
 
u32 IsRx
 TX or RX Mode. More...
 
u32 IsRegisterPresent
 Is register access allowed. More...
 
u32 MaxLanesPresent
 Number of Lanes. More...
 
u32 EscClkPeriod
 Escape Clock Peroid. More...
 
u32 EscTimeout
 Escape Timeout. More...
 
u32 HSLineRate
 High Speed Line Rate. More...
 
u32 HSTimeOut
 Max Frame Length. More...
 
u32 Wakeup
 Time to exit ULPS mode. More...
 
u32 EnableTimeOutRegs
 Enable HS and Esc Timeout Regs. More...
 

Detailed Description

The configuration structure for DPHY.

This structure passes the hardware building information to the driver

Field Documentation

◆ BaseAddr

UINTPTR XDphy_Config::BaseAddr

Base address of DPHY.

Referenced by DphySelfTestExample(), and XDphy_CfgInitialize().

◆ DeviceId

u32 XDphy_Config::DeviceId

Device Id.

◆ EnableTimeOutRegs

u32 XDphy_Config::EnableTimeOutRegs

Enable HS and Esc Timeout Regs.

◆ EscClkPeriod

u32 XDphy_Config::EscClkPeriod

Escape Clock Peroid.

◆ EscTimeout

u32 XDphy_Config::EscTimeout

Escape Timeout.

◆ HSLineRate

u32 XDphy_Config::HSLineRate

High Speed Line Rate.

◆ HSTimeOut

u32 XDphy_Config::HSTimeOut

Max Frame Length.

Referenced by XDphy_SelfTest().

◆ IsRegisterPresent

u32 XDphy_Config::IsRegisterPresent

Is register access allowed.

Referenced by XDphy_Configure(), XDphy_GetInfo(), and XDphy_GetRegIntfcPresent().

◆ IsRx

u32 XDphy_Config::IsRx

TX or RX Mode.

◆ MaxLanesPresent

u32 XDphy_Config::MaxLanesPresent

Number of Lanes.

Range 1 - 4

◆ Wakeup

u32 XDphy_Config::Wakeup

Time to exit ULPS mode.