hwicap
Xilinx SDK Drivers API Documentation
xhwicap_l.h File Reference

Macros

#define XHwIcap_ReadReg(BaseAddress, RegOffset)   XHwIcap_In32((BaseAddress) + (RegOffset))
 Read from the specified HwIcap device register. More...
 
#define XHwIcap_WriteReg(BaseAddress, RegOffset, RegisterValue)   XHwIcap_Out32((BaseAddress) + (RegOffset), (RegisterValue))
 Write to the specified HwIcap device register. More...
 
Register Map

Register offsets for the XHwIcap device.

#define XHI_GIER_OFFSET   0x1C
 Device Global Interrupt Enable Reg. More...
 
#define XHI_IPISR_OFFSET   0x20
 Interrupt Status Register. More...
 
#define XHI_IPIER_OFFSET   0x28
 Interrupt Enable Register. More...
 
#define XHI_WF_OFFSET   0x100
 Write FIFO. More...
 
#define XHI_RF_OFFSET   0x104
 Read FIFO. More...
 
#define XHI_SZ_OFFSET   0x108
 Size Register. More...
 
#define XHI_CR_OFFSET   0x10C
 Control Register. More...
 
#define XHI_SR_OFFSET   0x110
 Status Register. More...
 
#define XHI_WFV_OFFSET   0x114
 Write FIFO Vacancy Register. More...
 
#define XHI_RFO_OFFSET   0x118
 Read FIFO Occupancy Register. More...
 
Device Global Interrupt Enable Register (GIER) bit definitions
#define XHI_GIER_GIE_MASK   0x80000000
 Global Interrupt enable Mask. More...
 
HwIcap Device Interrupt Status/Enable Registers

Interrupt Status Register (IPISR)

This register holds the interrupt status flags for the device. These bits are toggle on write.

Interrupt Enable Register (IPIER)

This register is used to enable interrupt sources for the device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.

IPISR/IPIER registers have the same bit definitions and are only defined once.

#define XHI_IPIXR_RFULL_MASK   0x00000008
 Read FIFO Full. More...
 
#define XHI_IPIXR_WEMPTY_MASK   0x00000004
 Write FIFO Empty. More...
 
#define XHI_IPIXR_RDP_MASK   0x00000002
 Read FIFO half full. More...
 
#define XHI_IPIXR_WRP_MASK   0x00000001
 Write FIFO half full. More...
 
#define XHI_IPIXR_ALL_MASK   0x0000000F
 Mask of all interrupts. More...
 
Control Register (CR)
#define XHI_CR_SW_ABORT_MASK   0x00000010
 Abort current ICAP Read/Write. More...
 
#define XHI_CR_SW_RESET_MASK   0x00000008
 SW Reset Mask. More...
 
#define XHI_CR_FIFO_CLR_MASK   0x00000004
 FIFO Clear Mask. More...
 
#define XHI_CR_READ_MASK   0x00000002
 Read from ICAP to FIFO. More...
 
#define XHI_CR_WRITE_MASK   0x00000001
 Write from FIFO to ICAP. More...
 
Status Register (SR)
#define XHI_SR_CFGERR_N_MASK   0x00000100
 Config Error Mask. More...
 
#define XHI_SR_DALIGN_MASK   0x00000080
 Data Alignment Mask. More...
 
#define XHI_SR_RIP_MASK   0x00000040
 Read back Mask. More...
 
#define XHI_SR_IN_ABORT_N_MASK   0x00000020
 Select Map Abort Mask. More...
 
#define XHI_SR_DONE_MASK   0x00000001
 Done bit Mask. More...
 
#define XHI_SR_EOS_MASK   0x00000004
 EOS bit Mask. More...