i2stx
Xilinx SDK Drivers API Documentation
xi2stx_hw.h File Reference

Macros

Register Map

Register offsets for the XI2S_Transmitter device.

#define XI2S_TX_CORE_VER_OFFSET   0x00
 Core Version Register. More...
 
#define XI2S_TX_CORE_CFG_OFFSET   0x04
 Core Configuration Register. More...
 
#define XI2S_TX_CORE_CTRL_OFFSET   0x08
 Core Control Register. More...
 
#define XI2S_TX_IRQCTRL_OFFSET   0x10
 Interrupt Control Register. More...
 
#define XI2S_TX_IRQSTS_OFFSET   0x14
 Interrupt Status Register. More...
 
#define XI2S_TX_TMR_CTRL_OFFSET   0x20
 I2S Timing Control Register. More...
 
#define XI2S_TX_CH01_OFFSET   0x30
 Audio Channel 0/1 Control Register. More...
 
#define XI2S_TX_CH23_OFFSET   0x34
 Audio Channel 2/3 Control Register. More...
 
#define XI2S_TX_CH45_OFFSET   0x38
 Audio Channel 4/5 Control Register. More...
 
#define XI2S_TX_CH67_OFFSET   0x3C
 Audio Channel 6/7 Control Register. More...
 
#define XI2S_TX_AES_CHSTS0_OFFSET   0x50
 AES Channel Status 0 Register. More...
 
#define XI2S_TX_AES_CHSTS1_OFFSET   0x54
 AES Channel Status 1 Register. More...
 
#define XI2S_TX_AES_CHSTS2_OFFSET   0x58
 AES Channel Status 2 Register. More...
 
#define XI2S_TX_AES_CHSTS3_OFFSET   0x5C
 AES Channel Status 3 Register. More...
 
#define XI2S_TX_AES_CHSTS4_OFFSET   0x60
 AES Channel Status 4 Register. More...
 
#define XI2S_TX_AES_CHSTS5_OFFSET   0x64
 AES Channel Status 5 Register. More...
 
Core Configuration Register masks and shifts
#define XI2S_TX_REG_CFG_MSTR_SHIFT   (0)
 Is I2S Master bit shift. More...
 
#define XI2S_TX_REG_CFG_MSTR_MASK   (1 << XI2S_TX_REG_CFG_MSTR_SHIFT)
 Is I2S Master mask. More...
 
#define XI2S_TX_REG_CFG_NUM_CH_SHIFT   (8)
 Maximum number of channels bit shift. More...
 
#define XI2S_TX_REG_CFG_NUM_CH_MASK   (0xF << XI2S_TX_REG_CFG_NUM_CH_SHIFT)
 Maximum number of channels mask. More...
 
#define XI2S_TX_REG_CFG_DWDTH_SHIFT   (16)
 I2S Data Width bit shift. More...
 
#define XI2S_TX_REG_CFG_DWDTH_MASK   (1 << XI2S_TX_REG_CFG_DWDTH_SHIFT)
 I2S Data Width mask. More...
 
Core Control Register masks and shifts
#define XI2S_TX_REG_CTRL_EN_SHIFT   (0)
 Module Enable bit shift. More...
 
#define XI2S_TX_REG_CTRL_EN_MASK   (1 << XI2S_TX_REG_CTRL_EN_SHIFT)
 Module Enable mask. More...
 
Interrupt masks and shifts
#define XI2S_TX_INTR_AES_BLKCMPLT_SHIFT   (0)
 AES Block Complete Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_BLKCMPLT_MASK   (1 << XI2S_TX_INTR_AES_BLKCMPLT_SHIFT)
 AES Block Complete Interrupt mask. More...
 
#define XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT   (1)
 AES Block Synchronization Error Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_BLKSYNCERR_MASK   (1 << XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT)
 AES Block Synchronization Error Interrupt mask. More...
 
#define XI2S_TX_INTR_AES_CHSTSUPD_SHIFT   (2)
 AES Channel Status Updated Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AES_CHSTSUPD_MASK   (1 << XI2S_TX_INTR_AES_CHSTSUPD_SHIFT)
 AES Channel Status Updated Interrupt mask. More...
 
#define XI2S_TX_INTR_AUDUNDRFLW_SHIFT   (3)
 Audio Underflow Detected Interrupt bit shift. More...
 
#define XI2S_TX_INTR_AUDUNDRFLW_MASK   (1 << XI2S_TX_INTR_AUDUNDRFLW_SHIFT)
 Audio Underflow Detected Interrupt mask. More...
 
#define XI2S_TX_GINTR_EN_SHIFT   (31)
 Global Interrupt Enable bit shift. More...
 
#define XI2S_TX_GINTR_EN_MASK   (1 << XI2S_TX_GINTR_EN_SHIFT)
 Global Interrupt Enable mask. More...
 
I2S Timing Control Register masks and shifts
#define XI2S_TX_REG_TMR_SCLKDIV_SHIFT   (0)
 SClk Divider bit shift. More...
 
#define XI2S_TX_REG_TMR_SCLKDIV_MASK   (0xF << XI2S_TX_REG_TMR_SCLKDIV_SHIFT)
 SClk Divider mask. More...
 
Audio Channel Control Register masks and shifts
#define XI2S_TX_REG_CHCTRL_CHMUX_SHIFT   (0)
 Channel MUX bit shift. More...
 
#define XI2S_TX_REG_CHCTRL_CHMUX_MASK   (0x7 << XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)
 Channel MUX mask. More...
 
Register access macro definition
#define XI2s_Tx_In32   Xil_In32
 Input Operations. More...
 
#define XI2s_Tx_Out32   Xil_Out32
 Output Operations. More...
 
#define XI2s_Tx_ReadReg(BaseAddress, RegOffset)   XI2s_Tx_In32((BaseAddress) + ((u32)RegOffset))
 This macro reads a value from a I2S Transmitter register. More...
 
#define XI2s_Tx_WriteReg(BaseAddress, RegOffset, Data)   XI2s_Tx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
 This macro writes a value to a I2S Transmitter register. More...