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dphy
Xilinx SDK Drivers API Documentation
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The configuration structure for DPHY. More...
Data Fields | |
u32 | DeviceId |
Device Id. More... | |
UINTPTR | BaseAddr |
Base address of DPHY. More... | |
u32 | IsRx |
TX or RX Mode. More... | |
u32 | IsRegisterPresent |
Is register access allowed. More... | |
u32 | MaxLanesPresent |
Number of Lanes. More... | |
u32 | EscClkPeriod |
Escape Clock Peroid. More... | |
u32 | EscTimeout |
Escape Timeout. More... | |
u32 | HSLineRate |
High Speed Line Rate. More... | |
u32 | HSTimeOut |
Max Frame Length. More... | |
u32 | Wakeup |
Time to exit ULPS mode. More... | |
u32 | EnableTimeOutRegs |
Enable HS and Esc Timeout Regs. More... | |
The configuration structure for DPHY.
This structure passes the hardware building information to the driver
UINTPTR XDphy_Config::BaseAddr |
Base address of DPHY.
Referenced by DphySelfTestExample(), and XDphy_CfgInitialize().
u32 XDphy_Config::DeviceId |
Device Id.
u32 XDphy_Config::EnableTimeOutRegs |
Enable HS and Esc Timeout Regs.
u32 XDphy_Config::EscClkPeriod |
Escape Clock Peroid.
u32 XDphy_Config::EscTimeout |
Escape Timeout.
u32 XDphy_Config::HSLineRate |
High Speed Line Rate.
u32 XDphy_Config::HSTimeOut |
Max Frame Length.
Referenced by XDphy_SelfTest().
u32 XDphy_Config::IsRegisterPresent |
Is register access allowed.
Referenced by XDphy_Configure(), XDphy_GetInfo(), and XDphy_GetRegIntfcPresent().
u32 XDphy_Config::IsRx |
TX or RX Mode.
u32 XDphy_Config::MaxLanesPresent |
Number of Lanes.
Range 1 - 4
u32 XDphy_Config::Wakeup |
Time to exit ULPS mode.